JP4800235B2 - 処理方法 - Google Patents
処理方法 Download PDFInfo
- Publication number
- JP4800235B2 JP4800235B2 JP2007033632A JP2007033632A JP4800235B2 JP 4800235 B2 JP4800235 B2 JP 4800235B2 JP 2007033632 A JP2007033632 A JP 2007033632A JP 2007033632 A JP2007033632 A JP 2007033632A JP 4800235 B2 JP4800235 B2 JP 4800235B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- pressure
- silylation
- processing
- processing chamber
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000003672 processing method Methods 0.000 title claims description 17
- 238000012545 processing Methods 0.000 claims description 103
- 238000006884 silylation reaction Methods 0.000 claims description 87
- 238000000034 method Methods 0.000 claims description 60
- 238000004380 ashing Methods 0.000 claims description 40
- 239000007789 gas Substances 0.000 claims description 37
- 239000003795 chemical substances by application Substances 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 19
- 238000011084 recovery Methods 0.000 claims description 16
- KAHVZNKZQFSBFW-UHFFFAOYSA-N n-methyl-n-trimethylsilylmethanamine Chemical compound CN(C)[Si](C)(C)C KAHVZNKZQFSBFW-UHFFFAOYSA-N 0.000 claims description 13
- 238000001020 plasma etching Methods 0.000 claims description 8
- LEIMLDGFXIOXMT-UHFFFAOYSA-N trimethylsilyl cyanide Chemical compound C[Si](C)(C)C#N LEIMLDGFXIOXMT-UHFFFAOYSA-N 0.000 claims description 8
- CWMFRHBXRUITQE-UHFFFAOYSA-N trimethylsilylacetylene Chemical compound C[Si](C)(C)C#C CWMFRHBXRUITQE-UHFFFAOYSA-N 0.000 claims description 8
- 239000012159 carrier gas Substances 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 5
- NIZHERJWXFHGGU-UHFFFAOYSA-N isocyanato(trimethyl)silane Chemical compound C[Si](C)(C)N=C=O NIZHERJWXFHGGU-UHFFFAOYSA-N 0.000 claims description 4
- DUZKCWBZZYODQJ-UHFFFAOYSA-N n-trimethylsilylmethanamine Chemical compound CN[Si](C)(C)C DUZKCWBZZYODQJ-UHFFFAOYSA-N 0.000 claims description 4
- 235000012431 wafers Nutrition 0.000 description 88
- 238000005530 etching Methods 0.000 description 43
- 238000012546 transfer Methods 0.000 description 17
- 239000004065 semiconductor Substances 0.000 description 16
- 238000004519 manufacturing process Methods 0.000 description 14
- 239000010949 copper Substances 0.000 description 13
- 239000011248 coating agent Substances 0.000 description 11
- 238000000576 coating method Methods 0.000 description 11
- 230000000694 effects Effects 0.000 description 11
- 238000011068 loading method Methods 0.000 description 10
- 239000011229 interlayer Substances 0.000 description 9
- 239000000463 material Substances 0.000 description 8
- 238000004140 cleaning Methods 0.000 description 7
- 238000003860 storage Methods 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000012298 atmosphere Substances 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000001737 promoting effect Effects 0.000 description 3
- 239000006200 vaporizer Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- GJWAPAVRQYYSTK-UHFFFAOYSA-N [(dimethyl-$l^{3}-silanyl)amino]-dimethylsilicon Chemical compound C[Si](C)N[Si](C)C GJWAPAVRQYYSTK-UHFFFAOYSA-N 0.000 description 2
- 125000000217 alkyl group Chemical group 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- KZFNONVXCZVHRD-UHFFFAOYSA-N dimethylamino(dimethyl)silicon Chemical compound CN(C)[Si](C)C KZFNONVXCZVHRD-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 244000132059 Carica parviflora Species 0.000 description 1
- 235000014653 Carica parviflora Nutrition 0.000 description 1
- 229910018557 Si O Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000005441 aurora Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000007723 transport mechanism Effects 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31058—After-treatment of organic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Description
また、本発明の第2の態様は、基板処理方法であって、第1の処理室内に、ストッパ膜と、該ストッパ膜上に形成されたLow−k膜と、該Low−k膜上に形成された反射防止膜と、該反射防止膜上に所定のパターンで形成されたレジスト膜とを有する被処理基板を搬送する工程と、前記第1の処理室内で、前記反射防止膜及び前記Low−k膜をプラズマエッチング処理し、前記ストッパ膜に達するビアを形成する工程と、前記プラズマエッチング処理された前記被処理基板を第2の処理室内に搬送し、該第2の処理室内で、前記レジスト膜及び前記反射防止膜をプラズマアッシング処理し、前記レジスト膜及び前記反射防止膜を除去する工程と、前記プラズマアッシング処理された前記被処理基板を第3の処理室内に搬送し、該第3の処理室内で、前記プラズマエッチング処理及び前記プラズマアッシング処理により前記Low−kに形成されたダメージ部を回復させるシリル化処理工程とを備え、前記シリル化処理工程は、前記被処理基板を加熱するとともに前記第3の処理室内を減圧する工程と、前記第3の処理室内に、シリル化剤をキャリアガスでキャリアさせて供給する工程と、前記シリル化剤を供給しつつ、前記第3の処理室内の圧力を上昇させる工程と、前記シリル化剤を供給しつつ、前記第3の処理室内の圧力が所定圧力に到達させ、該所定圧力で保持することなく前記第3の処理室内の圧力を減圧する工程とを含むことを特徴とする処理方法を提供する。
104;エッチング・アッシング・シリル化処理システム
122;下部銅配線
123;ストッパ膜
124;含有Low−k膜
125a;反射防止膜
125b;レジスト膜
128:ビア
129;ダメージ部
153;シリル化処理ユニット
171;プロセスコントローラ
173;記憶部(記憶媒体)
W;ウエハ(基板)
Claims (7)
- ストッパ膜と、該ストッパ膜上に形成されたLow−k膜と、該Low−k膜上に形成された反射防止膜と、該反射防止膜上に所定のパターンで形成されたレジスト膜とを有する被処理基板に対してプラズマエッチング処理およびプラズマアッシング処理した際に、前記Low−k膜に形成されたダメージ部を回復するためのシリル化処理を施す処理方法であって、
処理室内にシリル化剤を供給して前記処理室内の圧力を上昇させて所定圧力に到達させ、該所定圧力で保持することなく前記処理室内の圧力を減圧させつつ、前記シリル化剤を供給することを特徴とする処理方法。 - 基板処理方法であって、
第1の処理室内に、ストッパ膜と、該ストッパ膜上に形成されたLow−k膜と、該Low−k膜上に形成された反射防止膜と、該反射防止膜上に所定のパターンで形成されたレジスト膜とを有する被処理基板を搬送する工程と、
前記第1の処理室内で、前記反射防止膜及び前記Low−k膜をプラズマエッチング処理し、前記ストッパ膜に達するビアを形成する工程と、
前記プラズマエッチング処理された前記被処理基板を第2の処理室内に搬送し、該第2の処理室内で、前記レジスト膜及び前記反射防止膜をプラズマアッシング処理し、前記レジスト膜及び前記反射防止膜を除去する工程と、
前記プラズマアッシング処理された前記被処理基板を第3の処理室内に搬送し、該第3の処理室内で、前記プラズマエッチング処理及び前記プラズマアッシング処理により前記Low−kに形成されたダメージ部を回復させるシリル化処理工程とを備え、
前記シリル化処理工程は、
前記被処理基板を加熱するとともに前記第3の処理室内を減圧する工程と、
前記第3の処理室内に、シリル化剤をキャリアガスでキャリアさせて供給する工程と、
前記シリル化剤を供給しつつ、前記第3の処理室内の圧力を上昇させる工程と、
前記シリル化剤を供給しつつ、前記第3の処理室内の圧力が所定圧力に到達させ、該所定圧力で保持することなく前記第3の処理室内の圧力を減圧する工程と
を含むことを特徴とする処理方法。 - 前記シリル化剤は、SiとCH3との結合を有するガスであることを特徴とする請求項1または請求項2に記載の処理方法。
- 前記SiとCH3との結合を有するガスは、TMSDMA(Dimethylaminotrimethylsilane)、TMMAS(Trimethylmethylaminosilane)、TMICS(Trimethyl(isocyanato)silane)、TMSA(Trimethylsilylacetylene)、TMSC(Trimethylsilylcyanide)から選択された少なくとも1つであることを特徴とする請求項3に記載の処理方法。
- 前記所定圧力は、シリル化反応が生じ得る圧力よりも大きい圧力範囲において、前記Low−k膜に形成されたダメージ部の回復特性が得られる圧力の時間積分値に到達している圧力であることを特徴とする請求項1から請求項4のいずれか1項に記載の処理方法。
- 前記所定圧力は、1333Pa(10Torr)であることを特徴とする請求項5に記載の処理方法。
- 被処理基板の温度が100℃以上になるようにして前記シリル化処理を行うことを特徴とする請求項1から請求項6のいずれか1項に記載の処理方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007033632A JP4800235B2 (ja) | 2007-02-14 | 2007-02-14 | 処理方法 |
US12/025,359 US7799703B2 (en) | 2007-02-14 | 2008-02-04 | Processing method and storage medium |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007033632A JP4800235B2 (ja) | 2007-02-14 | 2007-02-14 | 処理方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008198848A JP2008198848A (ja) | 2008-08-28 |
JP4800235B2 true JP4800235B2 (ja) | 2011-10-26 |
Family
ID=39686215
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007033632A Expired - Fee Related JP4800235B2 (ja) | 2007-02-14 | 2007-02-14 | 処理方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7799703B2 (ja) |
JP (1) | JP4800235B2 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8999734B2 (en) | 2009-03-10 | 2015-04-07 | American Air Liquide, Inc. | Cyclic amino compounds for low-k silylation |
JP5261291B2 (ja) * | 2009-06-01 | 2013-08-14 | 東京エレクトロン株式会社 | 処理方法および記憶媒体 |
JP5544893B2 (ja) * | 2010-01-20 | 2014-07-09 | 東京エレクトロン株式会社 | 基板処理方法及び記憶媒体 |
US9017933B2 (en) * | 2010-03-29 | 2015-04-28 | Tokyo Electron Limited | Method for integrating low-k dielectrics |
CN102315156A (zh) * | 2010-07-08 | 2012-01-11 | 中芯国际集成电路制造(上海)有限公司 | 用于制造半导体器件的方法 |
US20130056874A1 (en) * | 2011-09-06 | 2013-03-07 | International Business Machines Corporation | Protection of intermetal dielectric layers in multilevel wiring structures |
WO2013128972A1 (ja) * | 2012-03-02 | 2013-09-06 | 日本電気株式会社 | 動作判定装置、動作判定システムおよび動作判定方法 |
JP5535368B2 (ja) * | 2013-04-26 | 2014-07-02 | 東京エレクトロン株式会社 | 処理装置 |
US11335817B2 (en) * | 2019-08-15 | 2022-05-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Composite etch stop layers for sensor devices |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5925494A (en) * | 1996-02-16 | 1999-07-20 | Massachusetts Institute Of Technology | Vapor deposition of polymer films for photolithography |
KR100728244B1 (ko) * | 1999-11-18 | 2007-06-13 | 동경 엘렉트론 주식회사 | 실리레이션처리장치 및 방법 |
US6787455B2 (en) * | 2001-12-21 | 2004-09-07 | Taiwan Semiconductor Manufacturing Co., Ltd | Bi-layer photoresist method for forming high resolution semiconductor features |
JP5057647B2 (ja) * | 2004-07-02 | 2012-10-24 | 東京エレクトロン株式会社 | 半導体装置の製造方法および半導体装置の製造装置 |
JP2006086411A (ja) * | 2004-09-17 | 2006-03-30 | Dainippon Screen Mfg Co Ltd | 基板処理装置 |
-
2007
- 2007-02-14 JP JP2007033632A patent/JP4800235B2/ja not_active Expired - Fee Related
-
2008
- 2008-02-04 US US12/025,359 patent/US7799703B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US7799703B2 (en) | 2010-09-21 |
US20080194115A1 (en) | 2008-08-14 |
JP2008198848A (ja) | 2008-08-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100810163B1 (ko) | 반도체 장치의 제조 방법, 기판 처리 시스템 및 기록 매체 | |
JP4800235B2 (ja) | 処理方法 | |
JP5057647B2 (ja) | 半導体装置の製造方法および半導体装置の製造装置 | |
JP5100057B2 (ja) | 半導体装置の製造方法 | |
US8026150B2 (en) | Semiconductor device manufacturing method and storage medium | |
TWI317160B (ja) | ||
US20090001046A1 (en) | Substrate processing method, substrate processing apparatus and recording medium | |
US8187981B2 (en) | Substrate processing method, substrate processing system, and computer-readable storage medium | |
JP5452894B2 (ja) | 基板処理方法、基板処理装置および記憶媒体 | |
US8262921B2 (en) | Substrate processing method, substrate processing apparatus and recording medium | |
TW201622029A (zh) | 半導體裝置之製造方法、以及表面覆膜之形成方法及形成裝置 | |
TWI381446B (zh) | Substrate processing methods and memory media | |
JP2003234402A (ja) | 半導体製造方法及び半導体製造装置 | |
JP5247999B2 (ja) | 基板処理方法およびコンピュータ読取可能な記憶媒体 | |
KR20070019774A (ko) | 반도체 디바이스의 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20091116 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110217 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110315 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110516 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110802 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110803 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140812 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4800235 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |