JP2018170473A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2018170473A JP2018170473A JP2017068759A JP2017068759A JP2018170473A JP 2018170473 A JP2018170473 A JP 2018170473A JP 2017068759 A JP2017068759 A JP 2017068759A JP 2017068759 A JP2017068759 A JP 2017068759A JP 2018170473 A JP2018170473 A JP 2018170473A
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- film
- protective layer
- substrate
- dielectric constant
- isocyanate
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Abstract
Description
プラズマ処理においてマスク膜がオーバエッチングされ、電極膜の界面にダメージ層(酸化層)が形成される。このため例えば水素アニールなどで還元処理が行われている。しかしながら還元処理を行っても、ダメージ層の除去が不十分になる懸念がある。
また、非特許文献1には、樹脂の熱分解によるコンセプトにおいては、樹脂の除去温度が下がると当該樹脂の耐熱温度も下がることが開示されている。この中で、PMMAが唯一、配線工程で許容できる温度である400℃において熱除去(Thermal unstuff)できることが示されているが、PMMAの熱安定性が250℃へ低下する。このことは、PMMAによる保護工程中に250℃以上の温度がPMMAに加わり、PMMA膜が変質してしまうため保護膜としては使用が出来なくなることを意味している。
従って非特許文献1に記載された技術は、本発明のように、保護膜の除去温度を超えた熱工程が行われても、当該保護膜が保護膜として機能を有するものではない。
保護すべき被保護膜が形成された基板の表面に重合用の原料を供給して、尿素結合を有する重合体からなる保護層を形成する工程と、
前記保護層が露出している部分を覆うように、前記重合体が解重合する温度よりも低い温度で封止膜を形成する工程と、
その後、前記保護層である重合体が解重合する温度以上の温度で基板に対して処理を行う工程と、
次いで、前記保護層が存在しない場合には前記被保護膜に対して損傷を与えることとなる処理を行う工程と、
しかる後、前記基板を加熱して前記重合体を解重合する工程と、を含むことを特徴とする。
エッチングストッパー膜13の上には、層間絶縁膜である低誘電率膜20が形成されている。低誘電率膜20は、この例ではSiOC膜が用いられ、SiOC膜は例えばDEMS(Diethoxymethylsilane)をプラズマ化してCVD法により成膜される。低誘電率膜20は多孔質であり、図1〜図3では低誘電率膜20内の孔部21を極めて模式的に示している。なお下層側の層間絶縁膜11についてもSiOC膜が用いられる。
本実施形態では、低誘電率膜20内の孔部21を次のように埋め込み材料である、尿素結合を有する重合体(ポリ尿素)により埋める。低誘電率膜20内の孔部21に埋め込まれたポリ尿素は、被保護膜である低誘電率膜20を後述のプラズマ処理におけるプラズマから保護する保護層に相当する。ポリ尿素の製法としては、後述のように共重合などの手法もあるが、この例では自己重合により重合体が生成される手法について述べる。
水蒸気処理を行う装置としては、例えば図10に示す装置を用いることができる。図10中、41は水蒸気雰囲気を形成するための処理容器、42は水蒸気発生部、43は下面に多数の孔部が形成された水蒸気吐出部、44は水蒸気を水蒸気吐出部43内の拡散空間に導く管路、45はヒータ46を内蔵した載置台、47は吸引機構により排気される排気管である。処理容器41の内壁は、図示しない加熱機構により例えば80℃に加熱されている。ウエハWは載置台45の上に載置され、水蒸気吐出部43から吐出された水蒸気の雰囲気に置かれる。
次にハードマスク61の上にビアホールをエッチングするときのマスクとなるマスク用の膜62を形成し(図2(g))、更にマスク用の膜62の上に反射防止膜63及びレジスト膜64をこの順に積層する(図2(h)、図3(i)))。マスク用の膜62は、例えば炭素を主成分とする有機膜が用いられ、この有機膜は、反射防止膜63及びレジスト膜64を形成してレジストパターンを形成する装置内にて、薬液をウエハWにスピンコーティングすることにより得られる。
封止膜60は、ポリイミドに限られるものではなく、ポリ尿素を生成する温度よりも低い温度で成膜することができる膜であれば例えば金属膜あるいは絶縁膜などであってもよい。金属膜としては例えばTiN膜、TaN膜などを挙げることができ、例えば無電解メッキ法などで成膜してもよい。また絶縁膜としては、例えばアミノシラン系のガスとオゾンなどの酸化ガスとを真空雰囲気で反応させて成膜されるシリコン酸化膜などが挙げられる。この場合、シリコン酸化膜は例えば250℃もの低温で成膜ができる。絶縁膜を封止膜60として使用する場合には、例えば絶縁膜の前駆体を含む塗布液をウエハW上に塗布する手法を採用してもよい。
上述の実施形態では、イソシアネートの自己重合によりポリ尿素膜を生成しているが、図12に一例を示すようにイソシアネートとアミンとを用いて共重合によりポリ尿素膜を生成するようにしてもよい。なお、Rは例えばアルキル基(直鎖状アルキル基または環状アルキル基)またはアリール基であり、nは2以上の整数である。
ポリ尿素自体は、固体であって液体にすることができないため、上述のようにポリ尿素となる原料を別々に膜に供給して膜中にてポリ尿素を生成する手法を採用している。
更にまた図14(a)、(b)に示すように、イソシアネートと二級アミンとを用いてもよく、この場合に生成される重合体に含まれる結合も尿素結合である。
本発明の第2の実施形態について説明する。この実施形態は、本発明をRAMの形成工程に適用した実施形態であり、電極のオーバーエッチングによるダメージをポリ尿素からなる保護層により保護する例である。
図17(a)〜(d)は、絶縁膜81で囲まれた下層側の回路の電極82の上に、メモリ素子を形成するためのメモリ素子膜83が形成され、更にメモリ素子膜83の上に電極膜84が形成され、電極膜84の上にポリ尿素からなる保護層(ポリ尿素膜)85が順次形成される様子を示している。メモリ素子としては、例えばReRAM、PcRAM、MRAMなどが挙げられ、メモリ素子膜83は例えばReRAM(抵抗変化型メモリ)に用いられる金属酸化膜が挙げられる。
電極膜84は、例えばチタンナイトライド(TiN)膜及びタングステン膜(W)を下からこの順に積層した積層膜からなる。
ポリ尿素からなる保護層(ポリ尿素膜)85は、例えば既述の図12に示すように、イソシアネートとアミンとを用いて共重合により生成される。保護層85の膜厚は例えば20nm〜50nmに設定される。この場合、保護層を生成するための装置としては、既述の図16に示すCVD装置を挙げることができる。
更にメモリ素子膜83、金属層84及び保護層85からなる積層体の周囲に、素子同士を電気的に分離するための素子分離膜として絶縁膜である例えばシリコン酸化膜88を成膜し、シリコン酸化膜88の中に前記積層体が埋没した状態を形成する(図18(h))。シリコン酸化膜88は、例えば真空雰囲気にて300℃のプロセス温度でCVDにより成膜される。シリコン酸化膜88の成膜工程は、保護層が解重合する温度以上の高い温度でウエハWに対して行われる処理に相当する。
そして保護層85が形成された後に、ポリ尿素の解重合の温度以上で絶縁膜88が成膜されるが、保護層85は封止膜87により覆われているため、ポリ尿素の解重合が抑えられ、保護層85の機能が損なわれない。
保護層85を生成するための原料としては、上述の例に限らず、例えば既述の図13〜図15に示した原料を用いることができる。
ベアウエハ上にSiOC膜からなる低誘電率膜を成膜し、ポリ尿素を埋め込む前の低誘電率膜、ポリ尿素を埋め込んだ状態の低誘電率膜、ポリ尿素を除去した後の低誘電率膜の各々について吸収スペクトルを測定した。測定結果は、図21に示す通りである。図21中、(1)〜(3)は、夫々埋め込み前、埋め込み後、除去後に対応している。埋め込み後(2)においては、NH結合(矢印a)、CH結合(矢印b)、CO結合(矢印c)、CN結合(矢印d)に対応するピークが見られるが、埋め込み前(1)及び除去後(3)には、これらのピークは見られない。
この結果から、第1の実施形態で述べた手法により低誘電率膜内の孔部にポリ尿素が埋め込まれていること、またポリ尿素の除去処理を行うことで、ポリ尿素が低誘電率膜の中に全く残っていないこと、が裏付けられている。
1辺が5cmの正方形状の2つの基板の表面に、既述した真空蒸着により各々ポリ尿素膜を成膜した。そしてこれらの基板を重ね合わせ、窒素ガス雰囲気にて、350℃で5分間加熱した。この加熱処理時において上側に配置した基板の裏面(下面)、下側に配置した基板の表面(上面)を赤外吸収分光法(IR)により夫々吸収スペクトルを測定した。測定結果を図22に示す。実線の波形が上側に配置した基板の裏面のスペクトルを、点線の波形が下側に配置した基板の表面のスペクトルを示している。これらの各スペクトルは、測定した箇所にポリ尿素膜が存在することを示している。また、目視で観察すると、上側に配置した基板の裏面及び下側に配置した基板の表面にはポリ尿素膜が存在しているように見られ、上側に配置した基板の表面及び下側に配置した基板の裏面には、ポリ尿素膜は見られなかった。
一辺が6cmの正方形のシリコン基板の上に、膜厚が400nmのポリ尿素膜を成膜し、その後ポリ尿素膜を窒素ガス雰囲気で5分間加熱した。加熱温度は、150℃から450℃までの温度を50度刻みで設定した。加熱処理(アニール)後のポリ尿素膜の膜厚を測定したところ、図23に示す結果が得られた。この結果からポリ尿素膜は250℃であれば解重合しないが、300℃になると解重合が大幅に進み、350℃では完全に消失することが分かる。
一辺が6cmの正方形のシリコン基板を4個用意し、各シリコン基板の上に、膜厚が400nmのポリ尿素膜を成膜した。3つの基板にはポリ尿素膜の上に夫々膜厚が10nm、30nm、70nmであるポリイミド膜を成膜した。残り1つの基板にはポリイミド膜を成膜しなかった。これら4個の試料を窒素ガス雰囲気にて300℃で5分間加熱処理をし、その後、赤外吸収分光法(IR)により吸収スペクトルを測定した。測定結果を図24に示す。図24中、(1)はポリイミド膜を成膜していない基板、(2)はポリイミド膜を10nmの膜厚で成膜した基板、(3)はポリイミド膜を30nmの膜厚で成膜した基板、(4)はポリイミド膜を70nmの膜厚で成膜した基板に夫々相当する。吸収スペクトルにおいてCH結合等の波数の位置については既に評価試験1の項目にて説明していることから、図24についての同様の説明は省略する。
評価試験4にて用いた試料と同様の4種類の試料を作成した。即ち、ポリ尿素膜の上に封止膜を形成しない試料と、ポリ尿素膜の上に膜厚が夫々10nm、30nm、70nmであるポリイミド膜を成膜した3種類の試料と、を作成した。そして各試料について加熱温度を250℃、275℃、300℃、325℃の4通りに設定して、各加熱温度にて5分間加熱処理を行った。
これら試料について、赤外吸収分光法により吸収スペクトルを測定し、ポリ尿素膜の骨格に相当するCH結合に対応するピーク値を求めた。そして加熱処理前のピーク値に対する加熱処理後のピーク値の割合を求め、加熱処理温度毎にピーク値の割合をプロットして図25のグラフを得た。図25において、PIはポリイミド膜の略称である。なおピーク値の割合を便宜上、結合残存率と呼ぶことにする。
ポリイミド膜を積層していないポリ尿素膜単体について、膜厚と耐熱性との関係を調べた。シリコン基板にポリ尿素膜を夫々280nm、360nm、3000nmの膜厚で成膜し、各試料について加熱温度を変えて、5分間の熱処理を行い、加熱処理前後にて夫々基板上の膜について赤外吸収分光法により吸収スペクトルを測定した。
CH結合について、各試料における加熱処理前のピーク値に対する加熱処理後のピーク値の割合(CH結合残存率)を求め、各ポリ尿素の膜厚ごとにCH結合残存率と、加熱温度との関係を求めた。結果は図27に示すとおりである。また加熱温度が300℃の場合において、ポリ尿素膜の膜厚とCH結合及びC=O結合の各残存率を求めた。結果は図28に示すとおりである。
この結果から、ポリ尿素膜の膜厚を厚くしても、耐熱性の向上は期待できないことがわかった。
12 銅配線
13 エッチングストッパー膜
W 半導体ウエハ
31 バキュームチャック
32 カップモジュール
36 ノズル
41 処理容器
43 水蒸気吐出部
51 処理容器
54 加熱ランプ
60 封止膜
61 ハードマスク
62 マスク用の膜
63 反射防止膜
64 レジスト膜
65 シリコン酸化膜
201 ビアホール
202 トレンチ
70 配線金属
81 絶縁膜
82 電極
83 メモリ素子膜
84 保護層(ポリ尿素)
85 電極膜
86 マスク膜
87 封止膜
89 コンタクトホール
91 導電路
Claims (9)
- 基板に対して処理を行い、半導体装置を製造する方法において、
保護すべき被保護膜が形成された基板の表面に重合用の原料を供給して、尿素結合を有する重合体からなる保護層を形成する工程と、
前記保護層が露出している部分を覆うように、前記重合体が解重合する温度よりも低い温度で封止膜を形成する工程と、
その後、前記保護層である重合体が解重合する温度以上の温度で基板に対して処理を行う工程と、
次いで、前記保護層が存在しない場合には前記被保護膜に対して損傷を与えることとなる処理を行う工程と、
しかる後、前記基板を加熱して前記重合体を解重合する工程と、を含むことを特徴とする半導体装置の製造方法。 - 前記被保護膜は、多孔質の低誘電率膜であり、
前記保護層は、前記低誘電率膜内の孔部に埋め込まれた重合体により構成され、
前記重合体が解重合する温度以上の温度で基板に対して処理を行う工程は、前記封止膜の上に薄膜を形成する工程であり、
前記被保護膜に対して損傷を与えることとなる処理を行う工程は、前記低誘電率膜に凹部を形成するためのプラズマ処理であることを特徴とする請求項1記載の半導体製造装置の製造方法。 - 前記保護層を形成する工程は、イソシアネートの液体またはミストを前記低誘電率膜に染み込ませると共に、前記低誘電率膜に水分を供給してイソシアネートを加水分解してアミンを生成し、前記基板を加熱してイソシアネートとアミンとを重合反応させる工程を含むことを特徴とする請求項2記載の半導体装置の製造方法。
- 前記保護層を形成する工程は、イソシアネートの液体またはミストを前記低誘電率膜に染み込ませた後、基板が置かれる雰囲気を水蒸気雰囲気とする工程であることを特徴とする請求項3載の半導体装置の製造方法。
- 前記保護層を形成する工程は、イソシアネートの蒸気とアミンの蒸気との一方及び他方を前記低誘電率膜内に順番に拡散させると共に前記基板を加熱してイソシアネートとアミンとを重合反応させる工程であることを特徴とする請求項2記載の半導体装置の製造方法。
- 前記被保護膜は金属または金属化合物からなる電極膜であり、
前記電極膜の上に形成された前記保護層の上にパターンマスク膜を形成して当該保護層及び電極膜をエッチングする工程を行い、
前記封止膜を形成する工程は、前記電極膜をエッチングする工程の後、前記パターンマスク膜、前記保護層、前記電極膜の積層体全体を絶縁膜である封止膜により覆う工程であり、
前記重合体が解重合する温度以上の温度で基板に対して処理を行う工程は、前記封止膜の上から絶縁膜を形成する工程であり、
前記被保護膜に対して損傷を与えることとなる処理を行う工程は、前記封止膜の上の絶縁膜及び当該封止膜をエッチングして前記保護層に至るまでのコンタクトホールを形成する工程であることを特徴とする請求項1記載の半導体装置の製造方法。 - 前記電極膜の下方側には、メモリ素子膜が形成され、
前記メモリ素子膜は、前記電極膜をエッチングする工程にてエッチングされることを特徴とする請求項6記載の半導体装置の製造方法。 - 前記保護層を形成する工程は、イソシアネートの蒸気とアミンの蒸気とを基板に供給すると共に基板を加熱してイソシアネートとアミンとを重合反応させる工程であることを特徴とする請求項6または7記載の半導体装置の製造方法。
- 前記保護層を形成する工程は、イソシアネートの液体とアミンの液体とを基板に供給すると共に基板を加熱してイソシアネートとアミンとを当該基板表面で重合反応させる工程であることを特徴とする請求項6または7記載の半導体装置の製造方法。
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20200056304A (ko) * | 2018-11-14 | 2020-05-22 | 도쿄엘렉트론가부시키가이샤 | 디바이스의 제조 방법 |
JP2020080394A (ja) * | 2018-11-14 | 2020-05-28 | 東京エレクトロン株式会社 | 半導体メモリの製造方法 |
JP2020132986A (ja) * | 2019-02-25 | 2020-08-31 | 東京エレクトロン株式会社 | 成膜用組成物および成膜方法 |
JP2020150014A (ja) * | 2019-03-11 | 2020-09-17 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
JP2021163775A (ja) * | 2020-03-30 | 2021-10-11 | 東京エレクトロン株式会社 | エッチング方法及びエッチング装置 |
WO2021220834A1 (ja) * | 2020-04-28 | 2021-11-04 | 東京エレクトロン株式会社 | エッチング方法及びエッチング装置 |
Families Citing this family (4)
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JP6809315B2 (ja) * | 2017-03-15 | 2021-01-06 | 東京エレクトロン株式会社 | 半導体装置の製造方法及び真空処理装置 |
JP6977474B2 (ja) * | 2017-10-23 | 2021-12-08 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
JP6960839B2 (ja) * | 2017-12-13 | 2021-11-05 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
US11837618B1 (en) | 2020-08-21 | 2023-12-05 | Samsung Electronics Co., Ltd. | Image sensor including a protective layer |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005243903A (ja) * | 2004-02-26 | 2005-09-08 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP2006077245A (ja) * | 2004-09-07 | 2006-03-23 | Rohm & Haas Electronic Materials Llc | 多孔質物質およびその製造方法 |
JP2012138503A (ja) * | 2010-12-27 | 2012-07-19 | Fujifilm Corp | 多孔質絶縁膜及びその製造方法 |
US20120329273A1 (en) * | 2010-01-27 | 2012-12-27 | International Business Machines Corporation | Homogeneous porous low dielectric constant materials |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3957246B2 (ja) * | 1998-12-04 | 2007-08-15 | 日東電工株式会社 | 半導体素子封止用シートおよびそれを用いた半導体装置の製法ならびに半導体装置 |
DE10196026B4 (de) * | 2000-04-04 | 2011-02-10 | Asahi Kasei Kabushiki Kaisha | Überzugs-Zusammensetzung, dünner Film, zur Verwendung des dünnen Films und Verfahren zur Herstellung eines dünnen porösen Kieselsäure-Films |
JP2003089769A (ja) | 2001-09-18 | 2003-03-28 | Asahi Kasei Corp | 絶縁薄膜製造用の塗布組成物 |
JP4491283B2 (ja) * | 2004-06-10 | 2010-06-30 | 信越化学工業株式会社 | 反射防止膜形成用組成物を用いたパターン形成方法 |
JP5342811B2 (ja) | 2008-06-09 | 2013-11-13 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
JP2011063865A (ja) * | 2009-09-18 | 2011-03-31 | Ulvac Japan Ltd | ポリ尿素膜およびその成膜方法 |
US8901007B2 (en) * | 2013-01-03 | 2014-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Addition of carboxyl groups plasma during etching for interconnect reliability enhancement |
US9414445B2 (en) | 2013-04-26 | 2016-08-09 | Applied Materials, Inc. | Method and apparatus for microwave treatment of dielectric films |
KR102429873B1 (ko) * | 2015-08-31 | 2022-08-05 | 삼성전자주식회사 | 이방성 도전 재료와 이방성 도전 재료를 포함하는 전자소자 및 그 제조방법 |
-
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- 2017-03-30 JP JP2017068759A patent/JP6792788B2/ja active Active
-
2018
- 2018-03-27 KR KR1020180034815A patent/KR102317400B1/ko active IP Right Grant
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-
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- 2019-09-06 US US16/563,007 patent/US10755971B2/en active Active
-
2021
- 2021-10-19 KR KR1020210139103A patent/KR102459805B1/ko active IP Right Grant
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005243903A (ja) * | 2004-02-26 | 2005-09-08 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP2006077245A (ja) * | 2004-09-07 | 2006-03-23 | Rohm & Haas Electronic Materials Llc | 多孔質物質およびその製造方法 |
US20120329273A1 (en) * | 2010-01-27 | 2012-12-27 | International Business Machines Corporation | Homogeneous porous low dielectric constant materials |
JP2012138503A (ja) * | 2010-12-27 | 2012-07-19 | Fujifilm Corp | 多孔質絶縁膜及びその製造方法 |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7045974B2 (ja) | 2018-11-14 | 2022-04-01 | 東京エレクトロン株式会社 | デバイスの製造方法 |
JP2020080394A (ja) * | 2018-11-14 | 2020-05-28 | 東京エレクトロン株式会社 | 半導体メモリの製造方法 |
JP2020080397A (ja) * | 2018-11-14 | 2020-05-28 | 東京エレクトロン株式会社 | デバイスの製造方法 |
KR102524883B1 (ko) | 2018-11-14 | 2023-04-25 | 도쿄엘렉트론가부시키가이샤 | 디바이스의 제조 방법 |
KR20200056304A (ko) * | 2018-11-14 | 2020-05-22 | 도쿄엘렉트론가부시키가이샤 | 디바이스의 제조 방법 |
JP7154114B2 (ja) | 2018-11-14 | 2022-10-17 | 東京エレクトロン株式会社 | 半導体メモリの製造方法 |
JP2020132986A (ja) * | 2019-02-25 | 2020-08-31 | 東京エレクトロン株式会社 | 成膜用組成物および成膜方法 |
JP7169910B2 (ja) | 2019-03-11 | 2022-11-11 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
JP2020150014A (ja) * | 2019-03-11 | 2020-09-17 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
JP2021163775A (ja) * | 2020-03-30 | 2021-10-11 | 東京エレクトロン株式会社 | エッチング方法及びエッチング装置 |
JP7521229B2 (ja) | 2020-03-30 | 2024-07-24 | 東京エレクトロン株式会社 | エッチング方法及びエッチング装置 |
WO2021220834A1 (ja) * | 2020-04-28 | 2021-11-04 | 東京エレクトロン株式会社 | エッチング方法及びエッチング装置 |
JP7472634B2 (ja) | 2020-04-28 | 2024-04-23 | 東京エレクトロン株式会社 | エッチング方法及びエッチング装置 |
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