TW201831990A - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

Info

Publication number
TW201831990A
TW201831990A TW106141780A TW106141780A TW201831990A TW 201831990 A TW201831990 A TW 201831990A TW 106141780 A TW106141780 A TW 106141780A TW 106141780 A TW106141780 A TW 106141780A TW 201831990 A TW201831990 A TW 201831990A
Authority
TW
Taiwan
Prior art keywords
constant film
isocyanate
low
film
substrate
Prior art date
Application number
TW106141780A
Other languages
English (en)
Other versions
TWI696034B (zh
Inventor
八田浩一
早川崇
山口達也
Original Assignee
日商東京威力科創股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商東京威力科創股份有限公司 filed Critical 日商東京威力科創股份有限公司
Publication of TW201831990A publication Critical patent/TW201831990A/zh
Application granted granted Critical
Publication of TWI696034B publication Critical patent/TWI696034B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02359—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the surface groups of the insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

本發明之課題係提供一種技術，可以抑制在進行蝕刻時對基板上已形成之多孔質的低介電常數膜之損傷，並且可以避免因為熱度而對原本已形成之元件部分導致不良影響的情況。 解決前述課題之手段係讓異氰酸酯(液體)滲入低介電常數膜20，該低介電常數膜20係形成在晶圓W上的SiOC膜；接著供給水蒸氣以使水分滲入。一旦使異氰酸酯與水分反應，異氰酸酯會水解，而異氰酸酯的一部分會成為胺，並與未水解之異氰酸酯及胺反應而產生聚脲，聚脲就會填充低介電常數膜20之孔部21。之後，形成遮罩，並以蝕刻來形成通孔、溝槽；在去除遮罩後，例如以300℃～390℃來加熱低介電常數膜20，使聚脲解聚合以去除。

Description

半導體裝置之製造方法
本發明係有關於一種技術，針對用以製造半導體裝置而形成在基板上的多孔質之低介電常數膜，抑制了在進行蝕刻等等時的損傷。
在多層化之半導體裝置之製造，為了提升動作速度而縮小層間絶緣膜之寄生電容，作為其手法，係使用多孔質的低介電常數膜。作為此種膜，可舉例如含有矽、碳、氧及氫，並具有「矽-碳鍵」的SiOC(碳氧化矽)膜。SiOC膜，為了要埋設例如銅這樣的配線材料，而使用阻劑遮罩(resist mask)及下層遮罩，而以CF(氟碳)類的氣體，例如CF4 氣體的電漿以進行蝕刻，接著再藉由氧氣的電漿以進行阻劑遮罩的灰化。
然而，在對SiOC膜進行蝕刻或灰化等等的電漿處理之情況下，曝露於電漿之SiOC膜的露出面，亦即凹部之側壁及底面，會因為電漿而使例如矽—碳鍵切斷，導致碳(C)從膜中脱離。由於碳脱離而產生不飽和鍵的矽(Si)，在這樣的狀態下並不穩定，因此之後會與例如大氣中的水分等鍵結，而成為Si-OH。
這樣的電漿處理會在SiOC膜露出面導致損傷層之形成，由於此損傷層的碳含量低落，介電常數也會低落。由於配線圖案之線寬日益微細化、配線層和絶緣膜等等日益薄膜化，所以表面部對晶圓W整體所造成之影響的比重也變大，即使僅是表面部，也會因為其介電常數低落而演變成半導體裝置之特性偏離設計値的要因之一。
於專利文獻1記載以下技術：事先在基板上的多孔質之低介電常數膜的孔部埋入PMMA(丙烯醯基樹脂)，並對低介電常數膜進行蝕刻等等的處理後，再加熱基板，供給溶劑，更進一步地供給微波而去除PMMA。然而為了去除PMMA，需要施加電漿長達20分左右，而且還必須將基板加熱至高達400℃以上的溫度，所以產生如下課題：對基板上原本已形成之元件部分，大有導致不良影響之虞。 [習知技術文獻] [專利文獻]
[專利文獻1] 美國專利第9,414,445(第2欄第23行～29行、第13欄第51行～53行、申請專利範圍第3項)
[發明所欲解決的問題] 本發明係在此種背景下而研發者，其目的在於提供一種技術，可以抑制在進行蝕刻時對基板上已形成之多孔質的低介電常數膜之損傷，並且可以避免因為熱度而對原本已形成之元件部分導致不良影響的情況。 [解決問題之技術手段]
本發明的半導體裝置之製造方法，包括以下步驟： 埋入步驟，對於形成在用以製造半導體裝置之基板上的多孔質之低介電常數膜，供給聚合用的原料，而在該低介電常數膜內的孔部，埋入具有尿素鍵結之聚合體； 圖案遮罩形成步驟，接續前一步驟，在該低介電常數膜之表面，形成蝕刻用的圖案遮罩； 蝕刻步驟，在前一步驟後，以電漿蝕刻該低介電常數膜；以及 解聚合步驟，在前一步驟後，去除該圖案遮罩，並且加熱該基板，以使該聚合體解聚合。 [發明之效果]
本發明係對於低介電常數膜供給聚合用的原料，而在低介電常數膜內的孔部，埋入具有尿素鍵結之聚合體，並在蝕刻後加熱基板，而對聚合體進行解聚合。因此，由於在進行低介電常數膜之蝕刻時，係以聚合體加以保護，所以會抑制低介電常數膜發生損傷。然後，由於具有尿素鍵結的聚合體會在較低溫度(400℃以下)就解聚合，因此在去除聚合體時，不會產生對基板上原本已形成之元件部分導致不良影響之虞。再者，聚合體可以輕易地從低介電常數膜去除。
本發明之半導體裝置之製造方法，將套用在以雙鑲嵌法來形成半導體裝置之配線的步驟，以針對實施形態進行說明。圖1～圖3，係分階段繪示在下層側之電路部分上，形成上層側之電路部分的情形的說明圖；11係下層側的例如層間絶緣膜，12係作為埋入層間絶緣膜11的配線材料之銅配線，13係具備蝕刻時的停止層(stopper)功能的阻蝕刻膜。阻蝕刻膜13，例如係由SiC(碳化矽)或SiCN(氮碳化矽)等等所形成。
在阻蝕刻膜13上，形成有作為層間絶緣膜的低介電常數膜20。低介電常數膜20，於此例係使用SiOC(碳氧化矽)膜，SiOC膜例如係使DEMS(Diethoxymethylsilane；二乙氧基甲基矽烷)電漿化，而藉由CVD法來成膜。低介電常數膜20係多孔質，於圖1～圖3，係使低介電常數膜20內的孔部21，極為示意性地繪示。又，下層側的層間絶緣膜11，亦使用SiOC膜。 於本實施形態之方法，係在作為基板之半導體晶圓(以下稱為晶圓)的表面形成有圖1(a)所示的下層側之電路部分、而且在此電路部分上形成有低介電常數膜20之狀態下，開始進行處理。
於本實施形態，低介電常數膜20內的孔部21，係以後文所述之作為埋入材料的「具有尿素鍵結之聚合體(聚脲)」填塞。作為聚脲之製法，如後文所述般，還有共聚合等等的手法，不過在本例中，將針對以「自聚合」來產生聚合體的手法，進行敍述。 首先讓作為自聚合之原料的異氰酸酯(液體)滲入低介電常數膜20之中(圖1(b))，接著使例如係水蒸氣的水分，滲入介電常數膜20之中(圖1(c))。一旦使異氰酸酯與水分反應，異氰酸酯會水解，而馬上產生聚脲，並以聚脲填充低介電常數膜20的孔部21。圖5繪示此反應，異氰酸酯之一部分成為胺，其為不穩定的中間產物；當該中間產物與未水解之異氰酸酯反應，就會產生聚脲。於圖4中，R係例如烷基(直鏈烷基或環烷基)或芳基，n係2以上的整數。
就異氰酸酯而言，可使用例如脂環化合物、脂肪族化合物、芳香族化合物等等。就脂環化合物而言，可使用例如後述圖6(a)所示之1,3-二(異氰酸根合甲基)環己烷(H6XDI；1,3-Bis(isocyanatomethyl)cyclohexane)。再者，就脂肪族化合物而言，可使用如圖7所示之例如六亞甲基二異氰酸酯(HDI；Hexamethylene diisocyanate)。再者，異氰酸酯較佳係融點為100℃以下、在室溫下係液體者。 圖6係以H6XDI用作為原料單體之處理的情形，示意性地與對晶圓W所為之處理、及化學式加以對應而繪示的說明圖。圖6(a)相當於圖1(b)所示之對晶圓W供給異氰酸酯的處理，首先係藉由對晶圓W旋轉塗佈H6XDI液體，而使該液體滲入低介電常數膜20。
作為用以進行旋轉塗佈的旋轉塗佈裝置，可以使用例如圖8所示之裝置。於圖8中，31係將晶圓W吸附保持並藉由旋轉機構30而加以旋轉的真空固定座，32係杯體模組，33係使朝向下方延伸之外周壁及內周壁形成為筒狀之導引構件。34係排出空間，形成在外杯35及該外周壁之間，而可以進行整圈的排氣、排液；排出空間33的下方側形成可以氣液分離之構造。從液體供給源37將上述液體經由噴嘴36而供給至晶圓W的中心部，並使晶圓W以例如1500rpm之轉速旋轉，使液體在晶圓W表面伸展以形成塗布膜。
接著，藉由使晶圓W位於例如80℃的加熱氣體環境、且係水蒸氣氣體環境(相對濕度100％)，而使水蒸氣滲透至低介電常數膜20之中。圖6(b)相當於圖1(c)所示之對晶圓W供給作為水分之水蒸氣的處理。 作為進行水蒸氣處理之裝置，可以使用例如圖9所示之裝置。於圖9中，41係用以形成水蒸氣氣體環境的處理容器，42係水蒸氣產生部，43係於底面形成有許多孔部的水蒸氣釋出部，44係將水蒸氣引導至水蒸氣釋出部43內的擴散空間之管路，45係內建有加熱器46的載置台，47係藉由抽吸機構而進行排氣的排氣管。處理容器41之內壁，係以未圖示之加熱機構，加熱至例如80℃。晶圓W係載置於載置台45上，而處於水蒸氣釋出部43所釋出之水蒸氣的氣體環境。 再者，作為進行水蒸氣處理之裝置，亦可取代水蒸氣產生部42及水蒸氣釋出部43之設置，而採用在載置台45上方設置具有蓋子的扁平容器，並於此容器內容納水的狀態下加熱該容器，而使處理容器內構成為水蒸氣氣體環境。在此情況下，係於搬入搬出晶圓W時，以蓋子關閉容器。
由於在低介電常數膜20內已滲入有H6XDI，因此藉由使水蒸氣滲透至低介電常數膜20內，會如前述般發生水解，並馬上產生聚合反應，而產生聚脲。因此，低介電常數膜20內的孔部21內，就會被聚脲填滿。於圖1中，係將孔部21塞滿原料單體(於此例中，係H6XDI的液體)的狀態，權宜性地以「點狀」繪示，而將孔部21塞滿聚脲的狀態，權宜性地以「斜線」繪示。
接下來加熱晶圓W，以去除存在於低介電常數膜20的殘渣(圖6(c))。就加熱溫度而言，例如係設定於200℃以上，例如250℃；並使晶圓在惰性氣體氣體環境下加熱，例如氮氣氣體環境。此處理係例如圖10所示，可以係將晶圓W載置於處理容器51內的載置台50，並以光源53內的紅外線燈54加熱晶圓W來進行。於圖10中，55係透射窗，56係供給氮氣的供給管，57係排氣管。處理氣體環境係設為例如常壓氣體環境，但亦可係真空氣體環境。
如此這般，將聚脲填入低介電常數膜20的孔部21內之後，對低介電常數膜20進行形成通孔及溝槽(用以埋設配線的凹槽)之步驟。首先如圖1(d)所示，在低介電常數膜20的表面，以公知之手法，形成在對應於溝槽之部位開口的硬遮罩61，以作為蝕刻用圖案遮罩，其例如係以TiN(氮化鈦)膜構成。 接著，在低介電常數膜20及硬遮罩61上，形成作為蝕刻通孔時之遮罩的遮罩用膜62；更進一步地在遮罩用膜62上，依序積層出反射防止膜63及光阻膜64(圖2(e))。遮罩用膜62，例如使用以碳作為主成分的有機膜，此有機膜，係藉由在形成反射防止膜63及光阻膜64以形成光阻圖案之裝置內，對晶圓W旋轉塗佈化學液而得。
然後，藉由光阻膜64之曝光、顯影，而在對應於通孔之部位，形成光阻圖案，該光阻圖案形成有開口部641(圖2(f))；再用此光阻圖案，並使用例如CF類的氣體，來蝕刻反射防止膜63(圖2(g))。接下來以反射防止膜63作為遮罩，藉由例如使氧氣電漿化而得之電漿來蝕刻遮罩用膜62；此時光阻膜64也會被蝕刻而去除(圖2(h))。如此這般，就會在遮罩用膜62上對應通孔之部位，形成開口部621。 接下來使用遮罩用膜62作為蝕刻遮罩，來蝕刻低介電常數膜20，以形成通孔201(圖3(i))。作為蝕刻低介電常數膜20(於此例係SiOC膜)之手法，可以係藉由使C6 F6 氣體電漿化而得之電漿來進行；在此情況下，亦可更進一步地添加微量之氧氣。
之後，將通孔201底部的阻蝕刻膜13加以蝕刻並去除。此蝕刻，在阻蝕刻膜13係例如SiC膜的情況下，可以藉由例如使CF4 氣體電漿化而得之電漿來進行。接下來，藉由使氧氣電漿化而得之電漿，而將遮罩用膜62灰化並去除(圖3(j))。 接著，與形成通孔201之製程同樣地，使用硬遮罩61來蝕刻低介電常數膜20，並在圍繞通孔201的區域形成溝槽202(圖4(k))。之後，去除硬遮罩61(圖4(l))。當硬遮罩61係TiN膜時，可以藉由例如以硫酸、雙氧水及水的混合溶液作為蝕刻液的濕蝕刻來去除。 於上述，進行至此為止的各製程，其溫度必須在低於聚脲解聚合之溫度下實施。
如此這般，在低介電常數膜20形成通孔201及溝槽202後，去除填塞在低介電常數膜20之孔部21的埋入物質，即聚脲(圖4(m))。聚脲若加熱至300℃以上，例如350℃時，就會解聚合成胺並蒸發(圖6(d))，但為了不對晶圓W上原本就已形成之元件部分，特別是為了不對銅配線造成不良影響，要在不到400℃來加熱，較佳係以例如390℃以下，例如以300～350℃加熱。進行聚脲之解聚合的時間，例如在300℃～400℃下加熱之時間，基於抑制熱度對元件的損傷之觀點來看，例如係以5分鐘以下較佳。因此作為加熱製程配方的較佳例，可以舉例如350℃、5分鐘以下。就加熱的手法而言，可以如前述般使用紅外線燈，亦可以將晶圓W載置於內建有加熱器之載置台上來加熱。加熱氣體環境，例如係氮氣等等的惰性氣體環境。
去除了聚脲的低介電常數膜20，會恢復成原本的多孔質膜，接下來通孔201及溝槽202會填塞銅，而多餘的銅就以CMP(Chemical Mechanical Polishing；化學機械研磨)去除而形成銅配線65，以形成上層之電路部分(圖4(n))。於圖4(n)中雖已省略，但在形成銅配線65前，係在通孔201及溝槽202內形成例如由Ti與TiON之積層膜所構成的障壁金屬層與銅所構成的晶種層。
於上述實施形態，係依序對低介電常數膜20供給異氰酸酯與水分，而在低介電常數膜20內之孔部21，埋入具有尿素鍵結之聚合體的聚脲。然後在此狀態下，蝕刻低介電常數膜20而形成通孔201及溝槽202，進行蝕刻遮罩之灰化。因此，於此例中，由於在作為電漿處理所實施之蝕刻時及灰化時，會以聚脲來保護低介電常數膜20，因此會抑制低介電常數膜20發生損傷。然後，由於聚脲會在300℃左右的溫度下解聚合，所以在從低介電常數膜20去除聚脲時，不會對晶圓W上原本就已形成之元件部分——特別是銅配線——導致不良影響；再者由於可以僅憑加熱處理以進行聚脲之去除，因此手法很簡單。
於上述例中，係在晶圓W上旋轉塗佈異氰酸酯，但亦可在使晶圓W停止之狀態下，供給異氰酸酯的霧氣。 於上述實施形態，係藉由異氰酸酯之自聚合以產生聚脲膜，但亦可如圖11所示之一例般，使用異氰酸酯及胺，而藉由共聚合以產生聚脲膜。又，R係例如烷基(直鏈烷基或環烷基)或芳基，n係2以上之整數。 在此情況下，可採用以下手法：如前述般地藉由旋轉塗佈法而對晶圓供給例如異氰酸酯及胺中之一種液體，以使其滲透至低介電常數膜；接著同樣地以旋轉塗佈法對晶圓供給異氰酸酯及胺中之另一種液體，並使其滲透至低介電常數膜。又，亦可藉由氣體(蒸氣)之狀態，依序對晶圓供給異氰酸酯及胺，例如反覆供給複數次。在此情況下，使例如異氰酸酯之蒸氣擴散並吸附至低介電常數膜的孔部，接著胺的蒸氣再擴散至孔部並引起聚合反應，使這種作用反覆而讓孔部以聚脲膜填滿。 由於聚脲本身係固體而無法成為液體，所以如上述般，所採用的手法係分別對膜層供給會成為聚脲之原料，而在膜中產生聚脲。
在使用原料單體之蒸氣的手法下，較佳係使彼此的蒸氣壓有很大的差距，例如差距1個位數以上。其原因在於，在彼此的蒸氣壓較近的組合下，會在例如使胺擴散至低介電常數膜之孔部時，吸附在孔部之表面，而使和異氰酸酯之反應效率變差。 而異氰酸酯及胺的蒸氣壓差在1個位數以上之組合，可舉例如：從異氰酸酯去除了異氰酸酯官能基後的骨架分子與從胺去除了胺官能基後的骨架分子，係相同之例，亦即彼此具備同一骨架分子之異氰酸酯及胺。例如鍵結有胺官能基之H6XDA的蒸氣壓，相較於和該H6XDA之骨架分子係相同之骨架分子，但鍵結有異氰酸酯官能基之H6XDI的蒸氣壓，高出1個位數以上。
再者，如圖12(a)～(d)所示，亦可使用單官能性分子作為原料單體。 更進一步地，又如圖13(a)、(b)所示，亦可使用異氰酸酯及二級胺，而在此情況下所產生之聚合體所含有的鍵結，也是尿素鍵結。 然後，亦可係使具備尿素鍵結之原料單體聚合，以製得聚脲膜。在此情況下之原料單體，可以在液體、霧氣或蒸氣之狀態下，供給至低介電常數膜。圖14繪示此例，係對原料單體照射光線，例如紫外線，藉由賦予光能以發生聚合，產生聚脲膜；若以例如350℃來加熱此聚脲膜，就會解聚合為異氰酸酯和胺。
於圖15繪示CVD裝置，其用以使原料單體作為氣體來進行反應，而在低介電常數膜20內產生聚脲(蒸鍍聚合)。70係隔出真空氣體環境的真空容器。71a、72a分別係以液體狀態容納作為原料單體之異氰酸酯及胺的原料供給源；異氰酸酯的液體及胺的液體，係藉由設於供給管71b、72b途中的氣化器71c、72c而氣化，各蒸氣則被導入至作為氣體釋出部的簇射頭(shower head)73。簇射頭73係於底面形成有許多釋出孔，並構成為從各別之釋出孔，對處理氣體環境釋出異氰酸酯的蒸氣及胺的蒸氣。晶圓W係載置於具備調溫機構的載置台74。首先，對晶圓W供給異氰酸酯的蒸氣，藉此而使異氰酸酯的蒸氣，深入至晶圓W上的低介電常數膜內。接著停止異氰酸酯之蒸氣供給，待真空容器70內真空排氣後，再對晶圓W供給胺的蒸氣，使殘留在低介電常數膜內的異氰酸酯與胺反應，以產生聚脲。 [實施例]
在裸晶片上形成SiOC膜所構成的低介電常數膜，並對此晶圓進行圖6(a)～(d)所示之該操作，而在低介電常數膜內埋入聚脲。之後，進行如圖6(e)所示之操作，使聚脲解聚合，並由低介電常數膜去除。又，用以使聚脲解聚合的加熱處理，係以350℃進行了5分鐘。分別針對埋入聚脲前的低介電常數膜、埋入聚脲之狀態下的低介電常數膜、去除聚脲後的低介電常數膜，量測了膜厚、折射率、電容量、介電常數。量測結果如下。
埋入前　　　　埋入後　　　　去除後 膜厚(nm) 193.7 194.3 196.0 折射率 1.303 1.445 1.286 電容量(pF) 73 91 68 介電常數 2.2 2.5 2.1
又，分別針對埋入聚脲前的低介電常數膜、埋入聚脲之狀態下的低介電常數膜、去除聚脲後的低介電常數膜，量測了吸收光譜。量測結果就如圖16所示。(1)～(3)分別對應埋入前、埋入後、去除後。在埋入後(2)，可觀察到對應NH鍵結(箭頭a)、CH2 鍵結(箭頭b)、CO鍵結(箭頭c)、CN鍵結(箭頭d)的高峰，但在埋入前(1)及去除後(3)，就觀察不到這些高峰。 再者，以掃瞄式顯微鏡拍攝埋入前及埋入後之低介電常數膜的照片，就分別揭露於圖17及圖18。
基於上述，藉由對低介電常數膜埋入聚脲，膜質會發生介電常數稍微變高等等的些許變化，但藉由使聚脲解聚合而去除，就幾乎可以恢復原本的低介電常數膜之膜質。 特別是就介電常數而言，若考量到測定誤差等等，則可說幾乎完全沒有變化。然後從吸收光譜的特性圖可證實，藉由上述實施形態所述之手法對低介電常數膜內的孔部埋入聚脲，再進行聚脲之去除處理，聚脲就完全不會殘留在低介電常數膜之中。 再者，若比較圖17及圖18之照片，可觀察到在埋入後的膜層，散佈著白色粒狀物，可看出聚脲埋在膜層內。然後，雖然從膜厚量測結果看來，在埋入前後膜厚稍有變動，但從照片來看，膜厚可說是幾乎沒有變動。
11‧‧‧下層側的層間絶緣膜
12‧‧‧銅配線
13‧‧‧阻蝕刻膜
W‧‧‧半導體晶圓
20‧‧‧低介電常數膜
21‧‧‧孔部
30‧‧‧旋轉機構
31‧‧‧真空固定座
32‧‧‧杯體模組
33‧‧‧導引構件
34‧‧‧排出空間
35‧‧‧外杯
36‧‧‧噴嘴
37‧‧‧液體供給源
41‧‧‧處理容器
42‧‧‧水蒸氣產生部
43‧‧‧水蒸氣釋出部
44‧‧‧管路
45‧‧‧載置台
46‧‧‧加熱器
47‧‧‧排氣管
50‧‧‧載置台
51‧‧‧處理容器
53‧‧‧光源
54‧‧‧加熱燈(紅外線燈)
55‧‧‧透射窗
56‧‧‧供給管
57‧‧‧排氣管
61‧‧‧硬遮罩
62‧‧‧遮罩用膜
63‧‧‧反射防止膜
64‧‧‧光阻膜
65‧‧‧銅配線
621‧‧‧開口部
641‧‧‧開口部
201‧‧‧通孔
202‧‧‧溝槽
70‧‧‧真空容器
71a、72a‧‧‧原料供給源
71b、72b‧‧‧供給管
71c、72c‧‧‧氣化器
73‧‧‧簇射頭
74‧‧‧載置台
【圖1】(a)～(d)繪示本發明實施形態之半導體裝置之製造方法的步驟之一部分的說明圖。 【圖2】(e)～(h)繪示本發明實施形態之半導體裝置之製造方法的步驟之一部分的說明圖。 【圖3】(i)～(j)繪示本發明實施形態之半導體裝置之製造方法的步驟之一部分的說明圖。 【圖4】(k)～(n)繪示本發明實施形態之半導體裝置之製造方法的步驟之一部分的說明圖。 【圖5】繪示藉由使用異氰酸酯與水而進行自聚合，以產生具有尿素鍵結之聚合體的情形的說明圖。 【圖6】(a)～(d)分階段繪示藉由使用異氰酸酯與水而進行自聚合，以產生具有尿素鍵結之聚合體的處理的說明圖。 【圖7】繪示異氰酸酯之一例的分子構造的分子構造圖。 【圖8】繪示用以對基板供給異氰酸酯之液體的裝置的剖面圖。 【圖9】繪示用以對供給過異氰酸酯之液體後的基板供給水蒸氣的裝置的剖面圖。 【圖10】繪示用以加熱已供給過異氰酸酯與水蒸氣之基板的加熱裝置的剖面圖。 【圖11】繪示藉由共聚合之反應，而產生具有尿素鍵結之聚合體的情形的說明圖。 【圖12】(a)～(d)繪示具有尿素鍵結之聚合體變成寡聚物之反應的說明圖。 【圖13】(a)、(b)繪示使用二級胺以產生具有尿素鍵結之聚合體的情形的說明圖。 【圖14】繪示使具有尿素鍵結之單量體交聯，而產生具有尿素鍵結之聚合體的情形的說明圖。 【圖15】繪示使異氰酸酯和胺，分別以蒸氣進行反應，而產生具有尿素鍵結之聚合體的裝置的剖面圖。 【圖16】繪示在低介電常數膜埋入聚脲前後之吸收光譜的特性圖。 【圖17】顯示埋入聚脲前之低介電常數膜的掃瞄顯微鏡照片的圖。 【圖18】顯示埋入聚脲後之低介電常數膜的掃瞄顯微鏡照片的圖。

Claims (9)

  1. 一種半導體裝置之製造方法，包括以下步驟： 埋入步驟，對於形成在用以製造半導體裝置之基板上的多孔質之低介電常數膜，供給聚合用的原料，而在該低介電常數膜內的孔部，埋入具有尿素鍵結之聚合體； 圖案遮罩形成步驟，接續前一步驟，在該低介電常數膜之表面，形成蝕刻用的圖案遮罩； 蝕刻步驟，在前一步驟後，蝕刻該低介電常數膜；以及 解聚合步驟，在前一步驟後，去除該圖案遮罩，並且加熱該基板，以使該聚合體解聚合。
  2. 如申請專利範圍第1項之半導體裝置之製造方法，其中，該埋入步驟包含以下步驟：使異氰酸酯之液體或霧氣滲入該低介電常數膜，並且對該低介電常數膜供給水分，以使異氰酸酯水解而產生胺，再加熱該基板，而使異氰酸酯與胺發生聚合反應。
  3. 如申請專利範圍第2項之半導體裝置之製造方法，其中，該產生胺的步驟，係在使異氰酸酯之液體或霧氣滲入該低介電常數膜後，使基板所處的氣體環境成為水蒸氣氣體環境。
  4. 如申請專利範圍第2或3項之半導體裝置之製造方法，其中，使該異氰酸酯之液體滲入該低介電常數膜的步驟，係藉由使基板旋轉，而甩掉基板表面的過剩之異氰酸酯液體。
  5. 如申請專利範圍第1項之半導體裝置之製造方法，其中，該埋入步驟，係使異氰酸酯之蒸氣及胺之蒸氣中的一種及另一種，依序在該低介電常數膜內擴散，並且加熱該基板，以使異氰酸酯與胺發生聚合反應。
  6. 如申請專利範圍第1項之半導體裝置之製造方法，其中，該埋入步驟，係使具有尿素鍵結之化合物的液體、霧氣或蒸氣滲入該低介電常數膜，並且對基板照射光線以使該化合物發生聚合反應。
  7. 如申請專利範圍第1項之半導體裝置之製造方法，其中，去除該圖案遮罩並且加熱該基板以使該聚合體解聚合之步驟，係在去除該圖案遮罩後，再加熱該基板以使該聚合體解聚合。
  8. 如申請專利範圍第1項之半導體裝置之製造方法，其中，該低介電常數膜，係包含矽、碳及氧的絶緣膜。
  9. 如申請專利範圍第1項之半導體裝置之製造方法，其中，使該聚合體解聚合之步驟，係將基板加熱至300℃～400℃來進行。
TW106141780A 2016-12-07 2017-11-30 半導體裝置之製造方法 TWI696034B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016237922A JP6729335B2 (ja) 2016-12-07 2016-12-07 半導体装置の製造方法
JP2016-237922 2016-12-07

Publications (2)

Publication Number Publication Date
TW201831990A true TW201831990A (zh) 2018-09-01
TWI696034B TWI696034B (zh) 2020-06-11

Family

ID=62243150

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106141780A TWI696034B (zh) 2016-12-07 2017-11-30 半導體裝置之製造方法

Country Status (4)

Country Link
US (1) US10325780B2 (zh)
JP (1) JP6729335B2 (zh)
KR (1) KR102317534B1 (zh)
TW (1) TWI696034B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI743564B (zh) * 2018-09-25 2021-10-21 日商東京威力科創股份有限公司 半導體裝置之製造方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6960839B2 (ja) * 2017-12-13 2021-11-05 東京エレクトロン株式会社 半導体装置の製造方法
US10861739B2 (en) * 2018-06-15 2020-12-08 Tokyo Electron Limited Method of patterning low-k materials using thermal decomposition materials
JP7169910B2 (ja) * 2019-03-11 2022-11-11 東京エレクトロン株式会社 半導体装置の製造方法
JP7192588B2 (ja) 2019-03-12 2022-12-20 東京エレクトロン株式会社 基板処理装置及び基板処理方法
JP7193731B2 (ja) * 2019-03-29 2022-12-21 東京エレクトロン株式会社 エッチング方法及びエッチング装置
JP7466406B2 (ja) 2020-08-20 2024-04-12 東京エレクトロン株式会社 半導体装置の製造方法および成膜装置
US20220367361A1 (en) * 2021-05-07 2022-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnection structure and methods of forming the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8801736D0 (en) * 1988-01-27 1988-02-24 Ciba Geigy Ag Method of making patterns
JP2003089769A (ja) * 2001-09-18 2003-03-28 Asahi Kasei Corp 絶縁薄膜製造用の塗布組成物
JP2004231932A (ja) * 2002-12-02 2004-08-19 Nitto Denko Corp 接着剤組成物、接着フィルムおよびこれを用いた半導体装置
JP3765289B2 (ja) * 2002-05-27 2006-04-12 Ｊｓｒ株式会社 多層配線間の空洞形成方法
EP1632956A1 (en) * 2004-09-07 2006-03-08 Rohm and Haas Electronic Materials, L.L.C. Compositions comprising an organic polysilica and an arylgroup-capped polyol, and methods for preparing porous organic polysilica films
US8492239B2 (en) * 2010-01-27 2013-07-23 International Business Machines Corporation Homogeneous porous low dielectric constant materials
JP5636277B2 (ja) * 2010-12-27 2014-12-03 富士フイルム株式会社 多孔質絶縁膜及びその製造方法
US9538586B2 (en) 2013-04-26 2017-01-03 Applied Materials, Inc. Method and apparatus for microwave treatment of dielectric films
JP6195786B2 (ja) * 2013-12-06 2017-09-13 アーゼッド・エレクトロニック・マテリアルズ（ルクセンブルグ）ソシエテ・ア・レスポンサビリテ・リミテ 熱分解可能な充填用組成物、ならびにその組成物を用いて形成された空隙を具備した半導体装置、およびその組成物を用いた半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI743564B (zh) * 2018-09-25 2021-10-21 日商東京威力科創股份有限公司 半導體裝置之製造方法

Also Published As

Publication number Publication date
KR20180065925A (ko) 2018-06-18
US20180158693A1 (en) 2018-06-07
US10325780B2 (en) 2019-06-18
JP2018098220A (ja) 2018-06-21
KR102317534B1 (ko) 2021-10-27
JP6729335B2 (ja) 2020-07-22
TWI696034B (zh) 2020-06-11

Similar Documents

Publication Publication Date Title
TWI696034B (zh) 半導體裝置之製造方法
TWI689988B (zh) 半導體裝置之製造方法、真空處理裝置及基板處理裝置
KR102459805B1 (ko) 반도체 장치의 제조 방법
JP6610812B2 (ja) 半導体装置の製造方法、真空処理装置及び基板処理装置
KR102447740B1 (ko) 반도체 장치의 제조 방법 및 기판 처리 장치
US11495490B2 (en) Semiconductor device manufacturing method
JP6696491B2 (ja) 半導体装置の製造方法及び真空処理装置
CN109698115B (zh) 半导体装置的制造方法