GB2330001B - Method of forming an integrated circuit device - Google Patents

Method of forming an integrated circuit device

Info

Publication number
GB2330001B
GB2330001B GB9721152A GB9721152A GB2330001B GB 2330001 B GB2330001 B GB 2330001B GB 9721152 A GB9721152 A GB 9721152A GB 9721152 A GB9721152 A GB 9721152A GB 2330001 B GB2330001 B GB 2330001B
Authority
GB
United Kingdom
Prior art keywords
forming
integrated circuit
circuit device
integrated
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB9721152A
Other versions
GB9721152D0 (en
GB2330001A (en
Inventor
Shih-Wei Sun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to GB9721152A priority Critical patent/GB2330001B/en
Priority to FR9713228A priority patent/FR2770028B1/en
Priority to DE19747559A priority patent/DE19747559A1/en
Publication of GB9721152D0 publication Critical patent/GB9721152D0/en
Publication of GB2330001A publication Critical patent/GB2330001A/en
Application granted granted Critical
Publication of GB2330001B publication Critical patent/GB2330001B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5221—Crossover interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
GB9721152A 1997-10-06 1997-10-06 Method of forming an integrated circuit device Expired - Fee Related GB2330001B (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GB9721152A GB2330001B (en) 1997-10-06 1997-10-06 Method of forming an integrated circuit device
FR9713228A FR2770028B1 (en) 1997-10-06 1997-10-22 METHOD FOR MANUFACTURING AN INTERCONNECTION STRUCTURE FOR AN INTEGRATED CIRCUIT DEVICE
DE19747559A DE19747559A1 (en) 1997-10-06 1997-10-28 Multilevel interconnect structure for high density integrated circuit devices, integrated circuit memories

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB9721152A GB2330001B (en) 1997-10-06 1997-10-06 Method of forming an integrated circuit device
FR9713228A FR2770028B1 (en) 1997-10-06 1997-10-22 METHOD FOR MANUFACTURING AN INTERCONNECTION STRUCTURE FOR AN INTEGRATED CIRCUIT DEVICE
DE19747559A DE19747559A1 (en) 1997-10-06 1997-10-28 Multilevel interconnect structure for high density integrated circuit devices, integrated circuit memories

Publications (3)

Publication Number Publication Date
GB9721152D0 GB9721152D0 (en) 1997-12-03
GB2330001A GB2330001A (en) 1999-04-07
GB2330001B true GB2330001B (en) 1999-09-01

Family

ID=27217867

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9721152A Expired - Fee Related GB2330001B (en) 1997-10-06 1997-10-06 Method of forming an integrated circuit device

Country Status (3)

Country Link
DE (1) DE19747559A1 (en)
FR (1) FR2770028B1 (en)
GB (1) GB2330001B (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6596624B1 (en) 1999-07-31 2003-07-22 International Business Machines Corporation Process for making low dielectric constant hollow chip structures by removing sacrificial dielectric material after the chip is joined to a chip carrier
US6255712B1 (en) * 1999-08-14 2001-07-03 International Business Machines Corporation Semi-sacrificial diamond for air dielectric formation
DE19959966C2 (en) * 1999-12-13 2003-09-11 Mosel Vitelic Inc Process for the formation of dielectric layers with air pockets
FR2803438B1 (en) 1999-12-29 2002-02-08 Commissariat Energie Atomique METHOD FOR PRODUCING AN INTERCONNECTION STRUCTURE INCLUDING ELECTRICAL INSULATION INCLUDING AIR OR VACUUM CAVITES
DE10142223C2 (en) * 2001-08-29 2003-10-16 Infineon Technologies Ag Method for producing cavities with submicron dimensions in a semiconductor device by means of polymerization
DE10142224C2 (en) 2001-08-29 2003-11-06 Infineon Technologies Ag Method for creating cavities with submicron dimensions in a semiconductor device by means of a swelling process
DE10142201C2 (en) * 2001-08-29 2003-10-16 Infineon Technologies Ag Method for creating cavities with submicron structures in a semiconductor device using a freezing process liquid
FR2969375A1 (en) 2010-12-17 2012-06-22 St Microelectronics Crolles 2 INTERCONNECTION STRUCTURE FOR INTEGRATED CIRCUIT
US10707089B2 (en) * 2018-03-27 2020-07-07 Texas Instruments Incorporated Dry etch process landing on metal oxide etch stop layer over metal layer and structure formed thereby

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0241729A2 (en) * 1986-03-27 1987-10-21 General Electric Company Unframed via interconnection with dielectyric etch stop
EP0326293A1 (en) * 1988-01-27 1989-08-02 Advanced Micro Devices, Inc. Method for forming interconnects
US5461003A (en) * 1994-05-27 1995-10-24 Texas Instruments Incorporated Multilevel interconnect structure with air gaps formed between metal leads
US5607773A (en) * 1994-12-20 1997-03-04 Texas Instruments Incorporated Method of forming a multilevel dielectric

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2934353B2 (en) * 1992-06-24 1999-08-16 三菱電機株式会社 Semiconductor device and manufacturing method thereof
JP3887035B2 (en) * 1995-12-28 2007-02-28 株式会社東芝 Manufacturing method of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0241729A2 (en) * 1986-03-27 1987-10-21 General Electric Company Unframed via interconnection with dielectyric etch stop
EP0326293A1 (en) * 1988-01-27 1989-08-02 Advanced Micro Devices, Inc. Method for forming interconnects
US5461003A (en) * 1994-05-27 1995-10-24 Texas Instruments Incorporated Multilevel interconnect structure with air gaps formed between metal leads
US5607773A (en) * 1994-12-20 1997-03-04 Texas Instruments Incorporated Method of forming a multilevel dielectric

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Inspec abstract no. B9605-25550F-020 & VLSI Symp. Digest of Technical Papers, p61-2, 1995, Jeng etal *
Symposium on VLSI Technology, Digest of Technical Papers, pp82-83, 1996, "Gas Dielectric" Anand etal *

Also Published As

Publication number Publication date
FR2770028B1 (en) 2002-08-30
FR2770028A1 (en) 1999-04-23
GB9721152D0 (en) 1997-12-03
DE19747559A1 (en) 1999-05-06
GB2330001A (en) 1999-04-07

Similar Documents

Publication Publication Date Title
GB2376566B (en) Method of forming an electronic device
HK1009684A1 (en) Improved integrated circuit and process for using an integrated circuit of this type
GB9622682D0 (en) An integrated circuit device and method of communication therewith
EP0964415A4 (en) Electronic device and method of producing the same
IL132432A0 (en) An exposure apparatus exposure method using the same and method of manufacture of circuit device
HK1109248A1 (en) Semiconductor integrated circuit and method for designing semiconductor integrated circuit
EP0943157A4 (en) Integrated electronic circuit
IL147177A0 (en) Method of modifying an integrated circuit
EP0736902A3 (en) Integrated circuit device and method for fabricating integrated circuit device
HK1041557B (en) An integrated circuit and method for preparation thereof
GB9622684D0 (en) An integrated circuit device and method of communication therwith
GB0010867D0 (en) Method of semiconductor device fabrication
GB2333669B (en) High-frequency circuit device
SG53076A1 (en) Integrated circuit device and process for its manufacture
SG50865A1 (en) An integrated circuit chip
SG71075A1 (en) Method for packaging an integrated circuit
GB9812633D0 (en) Circuit device
GB2339502B (en) An integrated circuit device
SG65735A1 (en) Carrier film and integrated circuit device using the same and method of making the same
SG63750A1 (en) Integrated circuit device and process for its manufacture
GB9622685D0 (en) An integrated circuit device and method of communication therewith
SG79979A1 (en) Semiconductor integrated circuit testing apparatus
GB2330001B (en) Method of forming an integrated circuit device
GB2307997B (en) An integrated circuit memory device
HK1018517A1 (en) Reference circuit and method

Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20131006