JPH1140665A - 半導体集積回路およびその製造方法 - Google Patents

半導体集積回路およびその製造方法

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Publication number
JPH1140665A
JPH1140665A JP9194381A JP19438197A JPH1140665A JP H1140665 A JPH1140665 A JP H1140665A JP 9194381 A JP9194381 A JP 9194381A JP 19438197 A JP19438197 A JP 19438197A JP H1140665 A JPH1140665 A JP H1140665A
Authority
JP
Japan
Prior art keywords
insulating film
branch
layer wiring
integrated circuit
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9194381A
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English (en)
Inventor
Shiro Morinaga
志郎 森永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
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Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP9194381A priority Critical patent/JPH1140665A/ja
Priority to US09/114,173 priority patent/US6162740A/en
Priority to KR1019980028872A priority patent/KR100273494B1/ko
Priority to CN98103248A priority patent/CN1207580A/zh
Priority to GB9815644A priority patent/GB2327535B/en
Publication of JPH1140665A publication Critical patent/JPH1140665A/ja
Priority to US09/695,839 priority patent/US6333276B1/en
Pending legal-status Critical Current

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Abstract

(57)【要約】 【課題】 半導体集積回路を形成する場合に高速化を行
う。 【解決手段】 多層配線構造の層間絶縁膜１０６を選択
的に形成を行うことにより、空孔１０５を含んだ層間膜
の構造にすることで静電容量を低減させる。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、半導体集積回路及
びその製造方法に関する。
【０００２】
【従来の技術】従来の層間絶縁膜を用いた多層配線構造
を有する半導体集積回路の配線部分を図６に示す。図６
において、下層配線４０１は半導体基板４００上に蒸着
及びパターニングにより所望形状に形成される。その
後、ＣＶＤ法等により層間絶縁膜４０２を堆積して層間
絶縁膜４０２内に下層配線４０１を埋込み、エッチング
又はＣＭＰ法により層間絶縁膜４０２の表面を平坦化さ
せる。
【０００３】その後、層間絶縁膜４０２上に上層配線４
０３を蒸着及びパターニングにより所望形状に形成す
る。
【０００４】また図７（特開平５−２８３５４２号）に
示す方法では、まず、半導体基板５００上に下層配線５
０１を形成する。その後、半導体基板５００、下層配線
５０１を埋めこむようにキャップ用絶縁膜５０４を形成
する。そして、キャップ用絶縁膜５０４上に、サブミク
ロン径のＡｌ微粒子を混合したガラス塗布材を含む層間
絶縁膜５０２を塗布し、これを４００℃程度に加熱しガ
ラス化する。その後、ガラス塗布材に付着したＡｌのの
みを選択的にエッチングすることで層間絶縁膜５０２内
に空孔５０５を形成する。その後、第２のキャップ用絶
縁膜５０６を形成して上層配線５０３を形成していた。
【０００５】
【発明が解決しようとする課題】しかしながら、図６に
示す従来例は、回路の動作速度が配線容量に律速され、
高速化が困難であるという問題があった。
【０００６】その理由は、層間絶縁膜４０２が、材料固
有の誘電率を有しており、その容量値は空気より大き
く、高速化を阻止するためである。
【０００７】また、図７に示す従来例では、層間絶縁膜
５０２内に空孔５０３を形成することが困難であるとい
う問題があった。
【０００８】その理由は、Ａｌを選択的にエッチング
し、エアギャップ構造を形成するためには、Ａｌの粒子
を塗布材の大半に混合させる必要があり、また、そうし
ないと粒子間が塗布材により分離され、選択的にエッチ
ングができないためである。
【０００９】本発明の目的は、上記のような問題を解消
するためになされたものであり、層間絶縁膜による静電
容量を低減する半導体集積回路及びその製造方法を提供
することにある。
【００１０】
【課題を解決するための手段】前記目的を達成するた
め、本発明に係る半導体集積回路は、上層配線と下層配
線との間に層間絶縁膜を有する半導体集積回路であっ
て、層間絶縁膜は、絶縁枝と、絶縁膜とからなり、前記
絶縁枝は、下層配線から上方に糸状に伸長して前記配線
相互間に空孔を確保するものであり、前記絶縁膜は、前
記絶縁枝の上端に層状に形成され、上層配線を支えるも
のである。
【００１１】また本発明に係る半導体集積回路の製造方
法は、絶縁枝形成工程と、絶縁膜形成工程とを有し、層
間絶縁膜を挾んで上層と下層の配線を形成する半導体集
積回路の製造方法であって、絶縁枝形成工程は、下層配
線上に薄膜の絶縁膜を形成し、かつ、該絶縁膜上に成長
核を形成し、該成長核から絶縁膜を糸状に成長させるも
のであり、絶縁膜形成工程は、前記糸状の絶縁枝の上端
部に絶縁膜を層状に成長させる処理を行うものである。
【００１２】また前記成長核として金属を用いるもので
ある。
【００１３】また前記絶縁枝は、下地依存性が強い成膜
方法を用いて成膜するものである。
【００１４】また前記絶縁膜は、下地依存性が少ない成
膜方法を用いて成膜するものである。
【００１５】
【発明の実施の形態】以下、本発明の実施の形態を図に
より説明する。
【００１６】（実施形態１）図１は、本発明の実施形態
１に係る半導体集積回路を示す断面図、図２〜図４は、
本発明の実施形態１に係る半導体集積回路の製造方法を
工程順に示す断面図である。
【００１７】図１において、本発明の実施形態１に係る
半導体集積回路は、半導体基板１０１上で上層配線１０
３と下層配線１０１との間に層間絶縁膜１０２を有する
構造のものであり、層間絶縁膜１０２は、絶縁枝１０６
ａと絶縁膜１０６ｂとから構成されている。
【００１８】層間絶縁膜１０２の絶縁枝１０６ａは、下
層配線１０１から上方に糸状に伸長して配線１０１、１
０３相互間に空孔１０５を確保するようになっている。
【００１９】絶縁膜１０６ｂは、絶縁枝１０６ａの上端
に層状に形成され、上層配線１０３を支えるようになっ
ている。
【００２０】また絶縁枝１０６ａは、下層配線１０１上
に薄く形成した絶縁膜１０４から成長核を中心として枝
状に伸長し、空孔１０５を確保するようになっている。
【００２１】図１に示す本発明の実施形態１によれば、
上層配線１０３と下層配線１０１との間に絶縁枝１０６
ａによる空孔１０５が確保されることとなり、この空孔
１０５の存在によって上層配線１０３と下層配線１０１
との間の静電容量が低下するため、この静電容量による
影響を最小限に抑制することができる。
【００２２】次に図１に示す本発明の実施形態１に係る
半導体集積回路の製造方法を説明する。
【００２３】まず図２（ａ）に示すように、半導体基板
２００上に下層配線２０１を所望形状のパターンに形成
する。
【００２４】次に図２（ｂ）に示すように、ＣＶＤ法等
により下層配線２０１上に第１のキャップ絶縁膜２０４
を、金属配線の有無等の下地依存性のない条件にて１０
００Åの膜厚に薄く形成する。具体的には、第１のキャ
ップ絶縁膜２０４は、例えばプラズマＣＶＤ法によるシ
リコン酸化膜、或いはＳｉＨ4系常圧ＣＶＤ法によるシ
リコン酸化膜を用いて形成する。
【００２５】次に図２（ｃ）に示すように、第１のキャ
ップ絶縁膜２０４上に、成長核２０７となる金属、例え
ばＦｅ，Ｚｎ，Ｐｔ等の微粒子を吹付ける。この成長核
２０７は、層間絶縁膜の膜質に合わせて選択する。ま
た、成長核は、絶縁膜を糸状にするためにミクロン以下
のサイズが好ましく、粒状或いは島状の微細パターンを
有する金属を用いる。
【００２６】次に図３（ｄ）、（ｅ）に示すように、成
長核２０７の部分から絶縁膜を糸状に伸長成長させ、層
間絶縁膜２０２内に空孔２０５を確保する。ここで、実
験の結果、触媒としての成長核２０７が付着した絶縁膜
２０４の成長の割合は、それ以外の場所と比較すると、
約１００倍以上の速さで形成することが得られている。
これは、成長核としての金属が触媒として作用するもの
と考えられる。
【００２７】また、金属を触媒として絶縁膜を付着させ
るにあたっては、Ｆｅ，Ｚｎ，Ｐｔ等の微粒子を分散さ
せた液を塗布する、前記液を霧状に吹き付ける、金属を
溶解した溶液を霧状に吹き付ける等の方法を行なう。ま
た、サブミクロン開口パターンを有するレジスト膜を形
成して金属膜を全面に蒸着法等で成膜し、硫酸過水等で
レジストを溶解除去することにより、レジスト上の不要
な金属膜を除去して必要なパターンに金属を形成すると
いうレフト法等を用いて付着するようにしてよい。
【００２８】また、糸状の絶縁膜を成膜させるには、素
材としてＨＴＯ、原料ガスとしてＳｉＨ4，Ｎ2Ｏガスを
用い、温度７００〜８５０゜Ｃ、約１Ｔｏｒｒに設定し
た減圧ＣＶＤ法を用いる。金属微細パターン上では、第
１キャップ絶縁膜上の約１００倍の速度で成長するた
め、糸状となる。
【００２９】次に図３（ｆ）に示すように、絶縁枝２０
２の上端に層状の絶縁膜２０６をＣＶＤ法等により形成
する。絶縁膜２０６は、第１のキャップ絶縁膜と同様に
下地依存性のない条件で等方的に成長するため、層状と
なる。
【００３０】そして図４（ｇ）に示すように、絶縁膜２
０６の表面を平坦化し、図４（ｈ）に示すように平坦化
した絶縁膜２０６の上面に上層配線２０３を所望形状の
パターンに形成する。
【００３１】（実施形態２）図５は、本発明の実施形態
２に係る半導体集積回路の製造方法を工程順に示す断面
図である。
【００３２】まず図５（ａ）に示すように、第１のキャ
ップ絶縁膜３０４上に有機化合物３０７を塗布し、その
後、有機化合物３０７をパターニングして部分的に有機
化合物３０７を絶縁膜３０４上に選択的に残留させる。
【００３３】その後、残留した有機化合物３０７を選択
的に成長させるように、有機系の反応ガスを用いて有機
化合物３０７を成長させる。これにより成長した有機化
合物３０７間に空孔３０５が確保される。
【００３４】次に図５（ｂ）に示すように、有機系の反
応ガスを用いてＣＶＤ法により第２のキャップ絶縁膜３
０６を形成する。その後、絶縁膜３０６の表面を平坦化
し、その表面上に上層配線を形成する。
【００３５】
【発明の効果】以上説明したように本発明によれば、上
下層配線間の層間絶縁膜に空孔を有するため、静電容量
を小さくして集積回路の動作速度を速くすることができ
る。
【００３６】さらに絶縁枝を糸状に伸長成長させて空孔
を確保するため、製造工程が容易かつ簡素化することが
できる。
【図面の簡単な説明】
【図１】本発明の実施形態１に係る半導体集積回路を示
す断面図である。
【図２】本発明の実施形態１に係る半導体集積回路の製
造方法を工程順に示す断面図である。
【図３】本発明の実施形態１に係る半導体集積回路の製
造方法を工程順に示す断面図である。
【図４】本発明の実施形態１に係る半導体集積回路の製
造方法を工程順に示す断面図である。
【図５】本発明の実施形態２に係る半導体集積回路の製
造方法を工程順に示す断面図である。
【図６】従来例を示す断面図である。
【図７】従来例を示す断面図である。
【符号の説明】
１００、２００ 半導体基板 １０１、２０１ 下層配線 １０２、２０２ 層間絶縁膜 １０３、２０３ 上層配線 １０４、２０４ 第１のキャップ絶縁膜 １０５、２０５ 空孔 １０６、２０６ 第２のキャップ絶縁膜 ２０７ 成長核

Claims (5)

    【特許請求の範囲】
  1. 【請求項１】 上層配線と下層配線との間に層間絶縁膜
    を有する半導体集積回路であって、 層間絶縁膜は、絶縁枝と、絶縁膜とからなり、 前記絶縁枝は、下層配線から上方に糸状に伸長して前記
    配線相互間に空孔を確保するものであり、 前記絶縁膜は、前記絶縁枝の上端に層状に形成され、上
    層配線を支えるものであることを特徴とする半導体集積
    回路。
  2. 【請求項２】 絶縁枝形成工程と、絶縁膜形成工程とを
    有し、層間絶縁膜を挾んで上層と下層の配線を形成する
    半導体集積回路の製造方法であって、 絶縁枝形成工程は、下層配線上に薄膜の絶縁膜を形成
    し、かつ、該絶縁膜上に成長核を形成し、該成長核から
    絶縁膜を糸状に成長させるものであり、 絶縁膜形成工程は、前記糸状の絶縁枝の上端部に絶縁膜
    を層状に成長させる処理を行うものであることを特徴と
    する半導体集積回路の製造方法。
  3. 【請求項３】 前記成長核として金属を用いることを特
    徴とする請求項２に記載の半導体集積回路の製造方法。
  4. 【請求項４】 前記絶縁枝は、下地依存性が強い成膜方
    法を用いて成膜することを特徴とする請求項２に記載の
    半導体集積回路の製造方法。
  5. 【請求項５】 前記絶縁膜は、下地依存性が少ない成膜
    方法を用いて成膜することを特徴とする請求項２に記載
    の半導体集積回路の製造方法。
JP9194381A 1997-07-18 1997-07-18 半導体集積回路およびその製造方法 Pending JPH1140665A (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP9194381A JPH1140665A (ja) 1997-07-18 1997-07-18 半導体集積回路およびその製造方法
US09/114,173 US6162740A (en) 1997-07-18 1998-07-13 Semiconductor device and method of forming semiconductor device
KR1019980028872A KR100273494B1 (ko) 1997-07-18 1998-07-16 반도체 장치 및 그 제조 방법
CN98103248A CN1207580A (zh) 1997-07-18 1998-07-17 半导体器件及其制作方法
GB9815644A GB2327535B (en) 1997-07-18 1998-07-17 Semiconductor device and method of forming semiconductor device
US09/695,839 US6333276B1 (en) 1997-07-18 2000-10-26 Semiconductor device and method of forming semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9194381A JPH1140665A (ja) 1997-07-18 1997-07-18 半導体集積回路およびその製造方法

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Publication Number Publication Date
JPH1140665A true JPH1140665A (ja) 1999-02-12

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Country Link
US (2) US6162740A (ja)
JP (1) JPH1140665A (ja)
KR (1) KR100273494B1 (ja)
CN (1) CN1207580A (ja)
GB (1) GB2327535B (ja)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6831370B2 (en) * 2001-07-19 2004-12-14 Micron Technology, Inc. Method of using foamed insulators in three dimensional multichip structures
DE10161312A1 (de) 2001-12-13 2003-07-10 Infineon Technologies Ag Verfahren zum Herstellen einer Schicht-Anordnung und Schicht-Anordnung
US6984579B2 (en) * 2003-02-27 2006-01-10 Applied Materials, Inc. Ultra low k plasma CVD nanotube/spin-on dielectrics with improved properties for advanced nanoelectronic device fabrication

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05283542A (ja) * 1992-03-31 1993-10-29 Mitsubishi Electric Corp 半導体集積回路装置及びその製造方法
JPH0722583A (ja) * 1992-12-15 1995-01-24 Internatl Business Mach Corp <Ibm> 多層回路装置
USRE36475E (en) * 1993-09-15 1999-12-28 Hyundai Electronics Industries Co., Ltd. Method of forming a via plug in a semiconductor device
US5470802A (en) * 1994-05-20 1995-11-28 Texas Instruments Incorporated Method of making a semiconductor device using a low dielectric constant material
US5461003A (en) * 1994-05-27 1995-10-24 Texas Instruments Incorporated Multilevel interconnect structure with air gaps formed between metal leads
DE69531571T2 (de) * 1994-05-27 2004-04-08 Texas Instruments Inc., Dallas Verbesserungen in Bezug auf Halbleitervorrichtungen
US5548159A (en) * 1994-05-27 1996-08-20 Texas Instruments Incorporated Porous insulator for line-to-line capacitance reduction
US5504042A (en) * 1994-06-23 1996-04-02 Texas Instruments Incorporated Porous dielectric material with improved pore surface properties for electronics applications
US5567982A (en) * 1994-09-30 1996-10-22 Bartelink; Dirk J. Air-dielectric transmission lines for integrated circuits
US5955786A (en) * 1995-06-07 1999-09-21 Advanced Micro Devices, Inc. Semiconductor device using uniform nonconformal deposition for forming low dielectric constant insulation between certain conductive lines
US5847464A (en) * 1995-09-27 1998-12-08 Sgs-Thomson Microelectronics, Inc. Method for forming controlled voids in interlevel dielectric
US5994776A (en) * 1996-01-11 1999-11-30 Advanced Micro Devices, Inc. Interlevel dielectric with multiple air gaps between conductive lines of an integrated circuit
US5945203A (en) * 1997-10-14 1999-08-31 Zms Llc Stratified composite dielectric and method of fabrication

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Publication number Publication date
KR19990013948A (ko) 1999-02-25
GB2327535B (en) 1999-09-15
US6162740A (en) 2000-12-19
CN1207580A (zh) 1999-02-10
KR100273494B1 (ko) 2001-02-01
GB2327535A (en) 1999-01-27
US6333276B1 (en) 2001-12-25
GB9815644D0 (en) 1998-09-16

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