TW201310605A - 抗扭斜多晶粒封裝 - Google Patents

抗扭斜多晶粒封裝 Download PDF

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Publication number
TW201310605A
TW201310605A TW101125197A TW101125197A TW201310605A TW 201310605 A TW201310605 A TW 201310605A TW 101125197 A TW101125197 A TW 101125197A TW 101125197 A TW101125197 A TW 101125197A TW 201310605 A TW201310605 A TW 201310605A
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Taiwan
Prior art keywords
microelectronic
package
contacts
connections
terminals
Prior art date
Application number
TW101125197A
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English (en)
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TWI470764B (zh
Inventor
Richard Dewitt Crisp
Belgacem Haba
Wael Zohni
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Tessera Inc
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Publication of TW201310605A publication Critical patent/TW201310605A/zh
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Publication of TWI470764B publication Critical patent/TWI470764B/zh

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    • H—ELECTRICITY
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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Abstract

本發明揭示一種微電子封裝，其可具有安置於其一面處之複數個端子，該等端子係組態用於連接至至少一個外部組件，例如，一電路面板。第一及第二微電子元件可附加於封裝結構中。一第一電連接可自該封裝之一各別端子延伸至該第一微電子元件上之一對應觸點，且一第二電連接可自該各別端子延伸至該第二微電子元件上之一對應觸點，該等第一及第二連接經組態以使得由每一群組中之該等第一及第二連接載運之一各別信號在該各別端子與耦合至其之該等對應觸點之每一者之間經受相同持續時間之傳播延遲。

Description

抗扭斜多晶粒封裝
本發明係關於微電子封裝或總成及製作此等總成之方法，且係關於可用於此等總成中之組件。
本申請案主張2011年7月12日提出申請之美國臨時申請案61/506,889之申請日期之權益且主張對2011年11月29日提出申請之美國申請案13/306,068之優先權，該等申請案之揭示內容以引用方式併入本文中。
半導體晶片通常係提供為個別經預封裝單元。一標準晶片具有一扁平矩形主體，其中一大的前面具有連接至該晶片之內部電路之觸點。每一個別晶片通常安裝於一封裝中，該封裝又安裝於一電路面板(諸如一印刷電路板)上且將該晶片之觸點連接至該電路面板之導體。在諸多習用設計中，晶片封裝佔據與該晶片自身之面積相比相當大的該電路面板之一面積。如此揭示內容中參考具有一前面之一扁平晶片所使用，應將「晶片之面積」理解為係指該前面之面積。在「覆晶」設計中，晶片之前面面對一封裝基板(亦即，晶片載體)之面，且該晶片上之觸點藉由焊料球或其他連接元件直接接合至該晶片載體之觸點。該晶片載體又可透過上覆於該晶片之前面上之端子接合至一電路面板。該「覆晶」設計提供一相對緊密配置；每一晶片佔據等於或稍微大於該晶片之前面之面積的該電路面板之一面積，諸如在(舉例而言)共同受讓之美國專利第5,148,265 號、第5,148,266及第5,679,977號之某些實施例中所揭示，該等專利之揭示內容以引用方式併入本文中。
某些新穎安裝技術提供接近或等於習用覆晶接合之緊密性之緊密性。可在等於或稍微大於晶片自身之面積的電路面板之一面積中容納一單個晶片之封裝通常稱為「晶片大小之封裝」。
大小在晶片之任何實體配置中皆係一重要考量。對晶片之更緊密實體配置之需求隨著可攜式電子裝置之迅速發展已變得甚至更強烈。僅以實例之方式，通常稱為「智慧型電話」之裝置整合一蜂巢式電話之功能與強大的資料處理器、記憶體及輔助裝置(諸如全球定位系統接收器、電子攝影機及區域網路連接)以及高解析度顯示器及相關聯影像處理晶片。此等裝置可將諸如全網際網路連接性、包含全解析度視訊之娛樂、導航、電子銀行業務等等能力全部提供於一袖珍型裝置中。複雜的可攜式裝置需要將眾多晶片封裝至一小的空間中。此外，該等晶片中之某些晶片具有通常稱為「I/O」之諸多輸入及輸出連接。此等I/O必須與其他晶片之I/O互連。該等互連件應係短的且應具有低阻抗以使信號傳播延遲最小化。形成該等互連件之組件不應大大增加總成之大小。類似需要出現於其他應用中，如(舉例而言)資料伺服器(諸如用於網際網路搜尋引擎中之彼等資料伺服器)中。舉例而言，在複雜晶片之間提供眾多短的低阻抗互連件之結構可增加搜尋引擎之頻寬並減小其電力消耗。
含有多個晶片之封裝及總成對於含有記憶體儲存陣列之封裝晶片、尤其是對於動態隨機存取記憶體晶片(DRAM)及快閃記憶體晶片係常見的。每一封裝具有用於在端子(亦即，封裝之外部連接點)與其中的晶片之間載運信號、電力及接地之諸多電連接。該等電連接可包含不同種類之導體，諸如：水平導體(例如，跡線、樑式引線等)，其相對於一晶片之一觸點承載表面沿一水平方向延伸；垂直導體(諸如導通體)，其相對於該晶片之該表面沿一垂直方向延伸；及線接合，其相對於該晶片之該表面沿水平方向及垂直方向兩者延伸。
信號在封裝內傳輸至多晶片封裝中之晶片構成特別挑戰，尤其是對於封裝中之兩個或兩個以上晶片共同之信號(諸如用於記憶體晶片之時脈信號及位址及選通信號)而言。在此等多晶片封裝內，封裝之端子與晶片之間的連接路徑之長度可變化。不同路徑長度可致使信號花費較長或較短時間在端子與每一晶片之間行進。
一信號自一個點至另一點之行進時間稱作「傳播延遲」，且隨導體長度、導體之結構(亦即，寬度)及與其緊密接近之其他電介質或導體結構而變。
一特定信號到達不同位置之時間差稱作「扭斜」。兩個不同信號到達一特定位置之時間差亦可稱作「扭斜」。一特定信號到達兩個或兩個以上位置之時間之扭斜係傳播延遲及該特定信號開始朝向該等位置行進之時間兩者之一結果。扭斜可或可不影響電路效能。當一同步信號群組中之 所有信號一起扭斜時(在此情形中操作所需之所有信號在需要時一起到達)，扭斜對效能經常幾乎不具有影響。然而，當操作所需之一同步信號群組中之不同信號在不同時間到達時並非如此。在此情形中扭斜影響效能，此乃因在所有所需要信號已到達之前不可執行該操作。
圖1圖解說明信號扭斜及其對效能之潛在影響之一實例。圖1係圖解說明由複數個記憶體晶片(例如，一封裝或模組內之DRAM晶片)之每一者操作所需之信號Addr0、Addr1及Addr2之轉變之一圖表。如圖1中所繪示，由於不同傳播延遲，該等Addr信號在不同時間到達DRAM晶片。因此，在Addr1在信號位準之間轉變之前，Addr0在低信號位準與高信號位準之間(或在高信號位準與低信號位準之間)轉變。同樣地，在Addr2在信號位準之間轉變之前Addr1在信號位準之間轉變。
關於來自封裝之同步信號在不同時間到達一晶片之觸點之問題係此限制該晶片可傳輸或接收該等信號之速度或頻率。為正確地起作用，一操作所要求之所有同步信號需要在可執行該操作之前已到達。同步信號在不同時間到達之一結果係用以將該等信號記錄至晶片中之頻率可必須減小。圖1進一步圖解說明基於所涉及信號之不同到達時間之兩個間隔。第一間隔係基於最晚到達信號與圖1中之標識為CK之取樣時脈轉變之間的間隔之設置時間102。第二間隔係基於取樣時脈轉變CK與操作之下一連續時脈循環中最早到達信號之間的間隔之保持時間104。將信號鎖存 至封裝內之晶片中之時間係由「CK」指示。為達成每一既定時脈頻率之最好效能，期望使設置時間及保持時間兩者最大化。
鑒於上文所闡述之背景，可對多晶片封裝及總成做出進一步改良以解決扭斜。
根據本發明之一態樣之一微電子封裝包含具有安置於其一面處之複數個端子之封裝結構，該等端子係組態用於將該微電子封裝連接至封裝外部之至少一個組件。第一及第二微電子元件可附加於該封裝結構處。該封裝包含電耦合該封裝之該等端子與該等第一及第二微電子元件之連接。該等連接可包含用於載運各別信號之連接群組，每一群組包含兩個或兩個以上連接，例如，自該封裝之一各別端子延伸至該第一微電子元件上之一對應觸點之一第一連接及自該各別端子延伸至該第二微電子元件上之一對應觸點之一第二連接。該等第一及第二連接可經組態以使得由每一群組中之該等第一及第二連接載運之一各別信號在該各別端子與耦合至其之該等對應觸點之每一者之間經受相同持續時間之傳播延遲。
根據本發明之一特定態樣，甚至當沿著藉由該等連接之一各別群組耦合之端子與各別觸點之間的直線之距離變化達大於10%時，此連接群組中之該等連接之總電長度之間的一差亦可不大於10%。
根據本發明之一態樣，匹配延遲可至少部分地由該等電 連接中之導體相對於基板之其他導電結構之一間距差引起。
根據本發明之一態樣，一微電子封裝可進一步包含具有電路觸點之一電路面板，其中該封裝之該等端子電連接至該等電路觸點。
根據本發明之一特定態樣，該等信號之至少一者可係一時脈信號或一命令信號。
根據本發明之一特定態樣，該等信號可包含複數個位址信號及用以取樣該等位址信號之一取樣信號。
根據本發明之一特定態樣，該等信號可進一步包含一命令選通信號。
根據本發明之一特定態樣，各別信號在每一群組內之該等第一及第二連接上之傳播延遲之相同持續時間可係在彼信號之循環時間之10%之一容差內。
根據本發明之一特定態樣，一第三微電子元件可附加於該封裝結構處，其中該等連接群組之至少一者包含將該各別端子電耦合至該第三微電子元件之一對應觸點用於將該各別信號載運至其之一第三連接，其中由該等第一、第二及第三連接載運之信號在該各別端子與耦合至其之該等對應觸點之每一者之間經受相同持續時間之傳播延遲。在一特定實例中，一第四微電子元件亦可附加於該封裝結構處，其中該等連接群組之至少一者包含將該各別端子電耦合至該第四微電子元件之一對應觸點用於將該各別信號載運至其之一第四連接，其中由該等第一、第二、第三及第 四連接載運之信號在該各別端子與耦合至其之該等對應觸點之每一者之間經受相同持續時間之傳播延遲。
根據本發明之一特定態樣，該封裝結構可具有定界該面之邊緣，該面具有佔據其一中心部分之一中心區域及佔據該中心部分與該等邊緣之至少一者之間的面之一部分之一第二區域。該等端子可包含曝露於該中心區域處之第一端子及曝露於該第二區域處之第二端子，且該等連接群組耦合該等第一端子與該等對應觸點。在此情形中，在一特定實例中，該微電子封裝可包含電耦合該等第二端子與微電子元件之觸點之進一步連接。
根據本發明之一特定態樣，該封裝結構可包含具有第一及第二相對表面之一基板，該第一表面背對該等微電子元件且該第二表面面朝該等微電子元件，至少第一及第二孔隙延伸於該等第一與第二表面之間。在一特定實例中，該等孔隙可具有帶有沿著彼此平行之軸延伸之長度之長尺寸。該中心區域可至少部分地由該等第一及第二孔隙定界，且該等連接可包含具有與該等第一或第二孔隙之至少一者對準之部分之引線。根據本發明之一特定態樣，具有與該等孔隙之至少一者對準之部分之引線可包含線接合。在其一特定實例中，該微電子封裝可進一步包含各自附加於該封裝結構處之第三及第四微電子元件，其中該等連接群組之至少一者包含將該各別端子電耦合至該等第三及第四微電子元件之對應觸點用於將該各別信號載運至其之第三及第四連接，其中由該等第一、第二、第三及第四連接 載運之該信號在該各別端子與耦合至其之該等對應觸點之每一者之間經受相同持續時間之傳播延遲。根據一特定態樣，該等平行軸可係第一平行軸，且該基板可進一步包含延伸於該等第一與第二表面之間的第三及第四孔隙。該等第三及第四孔隙可具有帶有沿著彼此平行之第二軸延伸之長度之長尺寸，該等第二平行軸橫向於該等第一平行軸，其中該中心區域至少部分地由該等第三及第四孔隙定界，且該等連接包含具有與該等第三或第四孔隙之至少一者對準之部分之引線。
根據本發明之一特定態樣，第一、第二、第三及第四微電子元件之每一者經組態以主要提供一記憶體儲存功能。
根據一特定實例，第三及第四微電子元件可附加於該封裝結構處，其中該等連接群組之至少一者包含將該各別端子電耦合至該等第三及第四微電子元件之對應觸點用於將該各別信號載運至其之第三及第四連接。該等第一、第二、第三及第四連接可經組態以使得由該等第一、第二、第三及第四連接載運之信號在該各別端子與耦合至其之該等對應觸點之每一者之間經受相同持續時間之傳播延遲。在一特定實例中，該面之中心區域可由第一平行軸及橫向於該等第一平行軸之第二平行軸定界。每一第一軸可分別平分該等第一及第二微電子元件中之一者之一面積，且可沿平行於該等第一及第二微電子元件之每一者之第一及第二相對邊緣之一方向延伸。每一第二軸可分別平分該等第三及第四微電子元件中之一者之一面積，且可沿平行於該 等第三及第四微電子元件之每一者之第一及第二相對邊緣之一方向延伸。
根據本發明之一特定態樣，該封裝結構可包含具有在面向該等微電子元件之一表面處之觸點之一基板，該等微電子元件之該等觸點面向該等基板觸點且結合至其。根據一特定實例，該等第一平行軸之每一者可橫穿該等第三或第四微電子元件中之恰好一者，且該等第二平行軸之每一者可橫穿該等第一或第二微電子元件中之恰好一者。
根據本發明之一特定態樣，該微電子封裝可進一步包含具有毗鄰且電連接至該等端子之面板觸點之一電路面板，該電路面板上具有提供延遲匹配之導電元件，以使得由每一連接群組載運至該等微電子元件之信號穿過該封裝結構及該電路面板經受相同持續時間之延遲。
根據本發明之一特定態樣，該等第一及第二微電子元件可沿平行於該封裝結構之該面之一方向彼此間隔開。
根據本發明之一特定態樣，該封裝結構可包含一基板，該基板具有延伸穿過其之至少一個孔隙，且該第二微電子元件可部分地上覆於該第一微電子元件上以使得該第二微電子元件之觸點係超過該第一微電子元件之一邊緣安置，其中對該第二微電子元件之該等對應觸點之連接包含具有與該至少一個孔隙對準之部分之引線。
根據本發明之一特定態樣，該等引線可包含延伸穿過該至少一個孔隙之線接合。
根據本發明之一特定態樣，該至少一個孔隙可包含第一 及第二接合窗，且該等連接可包含耦合至具有與該第一接合窗對準之部分之該第一微電子元件之第一引線及耦合至具有與該第二接合窗對準之部分之該第二微電子元件之第二引線。
根據本發明之一特定態樣，該等端子中之該等第一及第二引線與其耦合之至少某些端子可安置於該等第一與第二接合窗之間。
根據本發明之一特定態樣，該第一微電子元件可具有在其一前面處及在與該前面相對之一後面處之觸點。該後面可係安裝至該封裝結構，且該等引線可包含連接於該等觸點與該封裝結構之間的線接合。
根據本發明之一特定態樣，該等第一或第二微電子元件之至少一者可包含一記憶體儲存陣列且該等第一或第二微電子元件之至少一者可包含一微控制器。
根據本發明之一特定態樣，該封裝結構可包含：一電介質層，其形成於該等第一及第二微電子元件之觸點承載表面上；跡線，其沿平行於該電介質層之一方向延伸；及金屬化導通體，其至少部分地延伸穿過該電介質層之一厚度且與該等第一及第二微電子元件之該等觸點電耦合，其中該等端子藉由該等跡線及該等導通體電連接至該等觸點。
一種根據本發明之一態樣製作一微電子封裝之方法可包含形成耦合第一及第二微電子元件與具有安置於其一面處之複數個端子之封裝結構之電連接，該等端子係組態用於將該微電子封裝連接至該封裝外部之至少一個組件。該等 連接可包含用於載運各別信號之連接群組，每一群組包含兩個或兩個以上連接，例如，自該封裝之一各別端子延伸至該第一微電子元件上之一對應觸點之一第一連接及自該各別端子延伸至該第二微電子元件上之一對應觸點之一第二連接。該等第一及第二連接可經組態以使得由每一群組中之該等第一及第二連接載運之一各別信號在該各別端子與耦合至其之該等對應觸點之每一者之間經受相同持續時間之傳播延遲。
根據本發明之一特定態樣，該封裝結構可具有定界該面之邊緣，且該面可具有佔據其一中心部分之一中心區域及佔據該中心部分與該等邊緣之至少一者之間的該面之一部分之一第二區域。該等端子可包含曝露於該中心區域處之第一端子及曝露於該第二區域處之第二端子。該等連接群組可耦合該等第一端子與該等對應觸點，且該微電子封裝可包含電耦合該等第二端子與該等微電子元件之觸點之進一步連接。
根據本發明之一特定態樣，該封裝結構可包含一基板，該基板具有延伸穿過其之至少一個孔隙，且該第二微電子元件可部分地上覆於該第一微電子元件上。以此方式，可超過該第一微電子元件之一邊緣安置該第二微電子元件之觸點。對該第二微電子元件之該等對應觸點之連接可包含具有與該至少一個孔隙對準之部分之引線。
本文中之本發明之實施例提供其中具有一個以上半導體 晶片(亦即，一微電子元件)之封裝。一多晶片封裝可減小將其中之晶片連接至一電路面板(例如，印刷佈線板，該封裝可透過諸如一球形柵格陣列、平台柵格陣列或針形柵格陣列以及其他陣列等一端子陣列電連接及機械連接至其)所需之面積或空間之量。此連接空間在小的或可攜式計算裝置(例如，諸如「智慧型電話」或平板電腦之手持式裝置，其通常組合個人電腦之功能與對更寬廣世界之無線連接性)中尤其受限。多晶片封裝可尤其有利於製作一系統可用之大量相對廉價記憶體，諸如進階高效能動態隨機存取記憶體(「DRAM」)晶片，例如在DDR3型DRAM晶片及其後續產品中。
可藉由在封裝上提供共同端子來減小將多晶片封裝連接至其所需之電路面板之面積量，其中至少某些信號透過該等共同端子沿其路線行進至封裝內之兩個或兩個以上晶片或自封裝內之兩個或兩個以上晶片行進。然而，以支援高效能操作之一方式如此做會引發挑戰。為避免諸如封裝內之雜訊及傳播延遲之不期望效應，電連接在封裝之外部處之端子與其中之晶片之跡線、導通體及其他導體必須不太長或太窄以避免過度電感及過量短截線長度，且必須不具有過量電容。熱耗散亦引發對進階晶片之一挑戰，以使得每一晶片之大的扁平表面之至少一者耦合至一散熱片或曝露至一已安裝系統內之一流體或空氣或與其熱連通係所期望的。下文所闡述之封裝可幫助促進此等目標。
本文中之本發明之實施例提供使載運於具有至少兩個微 電子元件之微電子封裝內之信號抗扭斜之方式，其中封裝中之複數個微電子元件之每一者透過封裝中之一組共同端子傳輸或接收該等相同信號中之某些信號。因此，封裝內之多個晶片之對應觸點可與組態用於與封裝外部之一組件(例如，諸如印刷電路板之一電路面板、外部微電子元件或其他組件)連接之該封裝之一單個共同端子電連接。
本文中之結構及製程有助於透過以下操作中之一或多者達成自一共同封裝端子至一個以上晶片上之觸點之一信號之一抗扭斜時序：用於載運時變信號之該封裝之至少某些共同端子在該等晶片之至少兩者之間的該封裝之一區域中之放置；及使得每一共同端子與連接至其之每一晶片之對應觸點之間的信號傳播延遲相同(亦即，在一有限容差內)的封裝之跡線或其他導體之設計。
圖1A至圖1B圖解說明其中根據本發明之一實施例可達成信號之抗扭斜之一特定類型之微電子總成或封裝10。如其中所見，封裝10包含具有一前面16及在其一前面處之複數個導電觸點20之一第一微電子元件12。舉例而言，如圖1A至圖1B中所圖解說明，觸點20可配置成安置於前面16之一中心區域13中之一或多個列，該中心區域佔據前面之一區之一中心部分。第一微電子元件12之前面16可視為具有毗鄰一周邊邊緣27之一第一外部區域、毗鄰另一周邊邊緣29之一第二外部區域及安置於該等第一與第二外部區域之間的中心區域13。
如本文中所使用，一微電子元件之一表面或面(例如， 該微電子元件之一前面)之中心區域意指安置於該面之第一與第二周邊區域之間的該面之部分，該等周邊區域係毗鄰於微電子元件之各別第一及第二相對周邊邊緣(舉例而言，第一微電子元件之相對周邊邊緣27、29)安置，其中該等第一及第二周邊區域以及該中心區域之每一者具有相等寬度，以使得該中心區域佔據延伸此微電子元件之相對第一與第二周邊邊緣之間的最短距離之中間三分之一的該面之一區。
在一項實例中，第一及第二微電子元件可係各自經組態以主要提供記憶體儲存陣列功能之裸晶片或微電子單元。因此，在一項實例中，每一微電子元件可併入有一動態隨機存取記憶體(「DRAM」)儲存陣列或經組態以主要充當一DRAM儲存陣列之元件。此「記憶體」微電子元件或「記憶體晶片」可具有經組態以提供記憶體儲存陣列功能而非微電子元件之任何其他功能之較大數目個主動電路元件(例如，主動半導體裝置)。
該封裝包含封裝結構，舉例而言，其上具有端子36(例如，導電墊36、連接盤(land)或導電柱)之一選用基板30。在某些情形中，該基板可基本上由具有一低的熱膨脹係數(「CTE」)(亦即，少於每攝氏度每百萬(下文中稱「ppm/℃」)10部分之一CTE)之一材料構成，諸如一半導體材料(例如，矽)或一電介質材料(諸如陶瓷材料或二氧化矽(例如，玻璃))。另一選擇係，該基板可包含一薄片狀電介質元件，該薄片狀電介質元件可基本上由一聚合材料構 成，諸如聚醯亞胺、環氧樹脂、熱塑性塑膠、熱固性塑膠或其他適合之聚合材料，或該薄片狀電介質元件包含或基本上由複合聚合無機材料構成，諸如BT樹脂(雙馬來醯亞胺三嗪)之一玻璃強化結構或環氧樹脂玻璃(諸如FR-4)以及其他材料。觸點20與端子36之間的電連接可包含選用引線(例如，線接合72、74)或其中該等引線之至少部分與延伸於基板之表面32、34之間的一孔隙33對準之其他可能結構。舉例而言，如圖1E中所見，該等連接可包含沿著面向微電子元件12之該基板之一表面34延伸之一樑式引線73，此引線延伸超過基板之一邊緣或延伸超過基板中之一孔隙33之一邊緣且結合至觸點20。另一選擇係，結合至觸點20之一樑式引線75可替代地沿著背對微電子元件12之該基板之一表面32延伸。
端子36充當用於微電子封裝10與一外部組件(諸如一電路面板(例如，印刷佈線板、撓性電路面板)、插座、其他微電子總成或封裝、插入件或被動組件總成以及其他組件)之對應導電元件之連接之端點。在一特定實例中，封裝10之端子可包含結合元件38，例如，附接至該等端子之導電塊(諸如焊料球)、導電材料(諸如導電膏、導電基質材料或導電膠)之塊。
如圖1A中進一步所見，封裝10可進一步包含具有一前面22(其上具有複數個觸點26)之一第二微電子元件14。在圖1A之特定實例中，第二微電子元件14之觸點26係超過第一微電子元件之一周邊邊緣29安置。此准許觸點26與端子36 之間的電連接包含引線，例如，自第二微電子元件14之觸點26至少部分地延伸至封裝結構10之一孔隙39或間隙內之線接合52、54。在一特定實施例中，結合至觸點26之引線可如上文關於圖1E所展示及所闡述經配置。在一項實例中，第二微電子元件14之觸點26可安置於如上文所定義之其前面22之中心區域14A內，其中前面22之第一及第二周邊區域14B及14C係如圖1A中所展示。
在如圖1A中所見之一特定實施例中，該封裝結構可定義孔隙或間隙33、39，其中諸如線接合72、74之引線或其他類型之電連接可在孔隙或間隙33、39內或透過孔隙或間隙33、39對準。舉例而言，如圖1A至圖1B中所見，孔隙33、39可延伸於一基板30之相對之第一表面32與第二表面34之間。在圖1A至圖1B之實例中，引線72、74可具有與孔隙33、39對準之部分。在一項實施例中，如圖1A中所見，引線可包含或係自第一微電子元件12之觸點20或自第二微電子元件14之觸點26延伸至基板之表面32處之導電元件40之線接合或樑式引線。該等導電元件可與端子36進一步連接。
在一特定實施例中，該等引線可包含或係樑式引線73，其沿著面向第一或第二微電子元件或兩個微電子元件之表面16、22之該基板之一表面34延伸且延伸超過一孔隙33或39之一邊緣至觸點20或觸點26或兩者。在另一實施例中，樑式引線75可沿著在封裝結構之面處之該基板之一表面32延伸。在一項實施例中，樑式引線73及75可存在於同一封 裝中。一囊封材料82可視情況覆蓋該等引線之至少一部分且延伸至封裝結構之孔隙或間隙中。
如圖1A中進一步所見，該封裝可進一步包含在第二微電子元件14與基板30之間的一第三元件，諸如一間隔件31或其他元件。在一項實施例中，該第三元件可係具有一低的熱膨脹係數(「CTE」)之一元件，諸如具有小於每攝氏度每百萬(下文中稱「ppm/℃」)10部分之一低CTE之一元件。在一項實施例中，該第三元件可基本上由半導體、玻璃或陶瓷材料構成，或可基本上由液晶聚合物材料或包含具有一低CTE之填充顆粒之一填充聚合材料構成。
該封裝可進一步包含在第一及第二微電子元件12、14之毗鄰面之間的一黏合劑60，及接觸邊緣表面27、29、40、42之一囊封材料62。該囊封材料可視情況覆蓋、部分覆蓋或不覆蓋微電子元件12、14之後表面15、24。舉例而言，在圖1A中所展示之封裝中，囊封材料62可係流動、模版印刷、絲網印刷或分配至微電子元件之後表面15、24上。在另一實例中，該囊封材料可係藉由外模製而形成於其上之一模製合成物。
如圖1B中之微電子封裝10之仰視平面圖中所繪示，中心端子36之位置係安置於佔據孔隙33、39之間的基板之表面32之區之基板之一對應中心區域44中。可安置於各別孔隙33、39與基板之邊緣132、134之間的基板之周邊區域46、48可分別容納周邊端子136、137。
在圖1A至圖1B之實施例中，通過封裝之中心端子36之 至少某些信號對於兩個微電子元件係共同的。此等信號係透過諸如沿平行於基板之表面32之一方向自端子36延伸至第一及第二微電子元件12、14之對應觸點20、26之導電跡線之連接來路由。舉例而言，如圖1B中所展示，端子36A(安置於基板表面32之一中心區域44中之諸多端子36中之一者)可透過一導電跡線51A、導電元件40A(例如，一接合墊)及結合至第一微電子元件12之觸點40A及觸點20A之一線接合74A而與第一微電子元件12之導電觸點20A電連接。端子36A亦可透過一導電跡線53A、導電元件40B(例如，一接合墊)及結合至第二微電子元件14之觸點40B及觸點26A之一線接合52A而與第二微電子元件14之導電觸點26A電連接。
參考圖1C，封裝之端子可透過結合元件38結合至諸如一電路板70之一外部組件之對應觸點71。在本文中之特定配置中，微電子封裝10透過封裝之一共同中心端子36A(而非透過各自專用於該等微電子元件中之特定一者之封裝之兩個或兩個以上端子)路由對於多個微電子元件12、14係共同的之一信號。以此方式，可減小由此等端子佔據之封裝基板30之一面積量。
圖1D圖解說明根據上文所闡述之實施例之一變化形式之一微電子封裝110，其中該封裝結構包含形成於第一及第二微電子元件12、14之表面上之一電介質層90及電耦合至微電子元件之觸點20、26且至少部分地延伸穿過電介質層之一厚度之金屬化導通體92。導電跡線94沿通常平行於電 介質層之一表面93之一或多個方向延伸且電連接該等金屬化導通體與端子36、136、137。該等跡線可與金屬化導通體形成整體，且某些或所有跡線及導通體可包含一單個單片金屬層之部分，例如，一單個沈積金屬層(諸如電鍍或以其他方式沈積(例如，絲網印刷、模版印刷、分配等)至電介質層90上且至電介質層中之開口中以形成製成跡線及導通體之單片金屬層的一金屬層)之部分。
封裝110可係其上具有一平台柵格陣列(「LGA」)或球形柵格陣列(「BGA」)型端子連接配置之一扇出晶圓級封裝。封裝110可具有延伸超過微電子元件12、14之邊緣27、42之一囊封材料62。囊封材料62可係具有與第一微電子元件12之一觸點承載表面16共面或大體共面之一表面17之一外模製件。電介質層90可上覆於囊封材料62上且該等端子或跡線中之某些端子或跡線可上覆於囊封材料62上。
可根據如2010年11月24日提出申請之共同所有之美國申請案12/953,994中闡述之一或多個實施例中所闡述之技術來製作封裝110，該申請案之揭示內容以引用方式併入本文中。然而，特定特徵(例如，一端子與耦合至其之對應觸點之間的相對跡線長度、相對傳播延遲及用於載運特定信號之封裝端子之指派及放置)係如本文中所闡述。
如圖1D中進一步所展示，封裝110可進一步包含導電柱96，例如，經沈積、結合、接合或蝕刻之金屬或含金屬結構，其有效提供突出於第二微電子元件之觸點承載表面25上方之觸點。在一特定實施例中，儘管未展示，但此等柱 亦可提供於第一微電子元件之觸點20上。如圖1D中所展示，金屬化導通體92可透過柱96耦合至觸點26。
參考圖2，最好透過中心端子(在基板之中心區域44中)進行路由之信號係由每一微電子元件用於由兩個微電子元件共同執行之操作之信號。在上文所闡述之實例中，其中第一及第二微電子元件12、14各自併入有一DRAM儲存陣列，將位址信號用於由該等微電子元件執行之共同操作且在可能時透過共同中心端子進行路由。亦將諸如位址信號、時脈信號、選通(例如，列位址選通、行位址選通及寫入啟用信號)之計時操作之信號用於共同操作且最好透過對於封裝10內之微電子元件係共同的之中心端子進行路由。此等信號可用於取樣進入或退出每一微電子元件12、14之信號。不涉及關鍵時序路徑且可透過基板30之周邊區域46、48中之周邊端子進行路由之其他電連接包含資料信號(例如，雙向資料輸入-輸出信號)、資料選通、對電源及接地之連接、行選擇信號及時脈啟用信號。藉由實例之方式，一時脈啟用信號可在作用時用以在需要一微電子元件執行操作時將該微電子元件切換至一作用操作模式中，且另一選擇係在不作用時可用以在不需要該微電子元件執行操作時將該微電子元件切換至一不作用操作模式(例如，一待用模式或靜止模式)中。
然而，甚至當信號透過共同中心端子進行路由時，該結構亦可進一步經組態以抗扭斜通過其至每一微電子元件且自每一微電子元件通過其之信號。可藉由以下操作提供信 號抗扭斜：確保每一共同端子與連接至其之每一微電子元件上之觸點之間的電連接具有匹配延遲，以使得載運於電連接之每一者上之信號在各別共同中心端子與第一及第二微電子元件之每一者上之對應觸點之間經受相同持續時間之傳播延遲。
可在一共同端子與每一微電子元件之間達成匹配傳播延遲之一個方式係結構化自該共同端子至各別微電子元件之每一路徑或連接(例如，如圖1B中所見，包含導電元件51A、40A及74A之一個路徑或一第一連接，以及包含導電元件53A、40B及52A之另一路徑或第二連接)上之跡線及其他導電元件，以使得由自該各別共同端子延伸之連接群組中之第一及第二連接載運之一信號在該各別端子與耦合至此端子之對應觸點之每一者之間經受相同持續時間之傳播延遲。在某種程度上，自共同端子延伸之不同路徑或不同連接上之延遲隨各別路徑或連接之長度而變。因此，在某些情形中，可藉由將該等路徑結構化為具有相同長度而使得延遲相同。然而，該等傳播延遲亦隨每一路徑上之電感、電容及電阻及由於毗鄰於每一路徑之其他導電特徵之接近所致的效應而變。因此，當結構化構成該等路徑或連接之導電元件時，亦必須考量此等額外因素。當穿過一特定共同端子至對應觸點之每一路徑或連接上之延遲相同時，可認為該等路徑具有相同「總電長度」。
圖3及圖4進一步圖解說明上文所闡述之原理。如圖3中所見，共同端子36A至36B可居中於基板之中心區域44 內，其中時脈信號透過共同端子36A至36B行進至各別微電子元件12、14(在圖3中標示為晶片1及晶片2)之觸點。 以此方式，至各別微電子元件之觸點20、26之路徑80、82之長度可在針對其之一允許容差內係相同的。在一項實例中，該容差可係用於取樣輸入至微電子元件12、14之信號之一時脈信號之循環時間之10%。在另一實例中，該容差可較小，諸如用於取樣輸入至微電子元件12、14之信號之時脈信號之循環時間之5%。圖4圖解說明在每一晶片之各別觸點20、26(20或26，分別地)處接收之時脈信號在時間tCK之一特定點處轉變於高位準與低位準之間。
圖3進一步圖解說明電連接一端子36C與各別微電子元件晶片1及晶片2之觸點20、26之路徑84及86。此處，路徑84、86需經不同地結構化，此乃因端子36C與其相對於晶片1之觸點20相比更接近於晶片2之觸點26。因此，路徑84可係相對直的，而路徑86在其中具有增加其長度之凹凸部。以此方式，可使得路徑84、86之總電長度相同(亦即，在容差內相同)。因此，在端子36C處接收之一位址1信號在如圖4中所見之相同時間tCK處到達每一微電子元件之觸點。應注意，在具有端子36C之實例中，路徑84、86之長度可在容差內係相同的，甚至當端子36C與觸點20、26(端子36C電連接至其)之間的直線距離遠遠大於針對其之容差時亦如此。
另外，當路徑包含線接合及跡線時，線接合之長度可針對包含一較短跡線之路徑而增加，或線接合之長度可針對 包含一較長跡線之路徑而減小。
在另一實例中，針對一封裝中之一路徑存在之遮蔽程度可選擇性地減小以相對於一個路徑減小另一路徑上之延遲，或可選擇性地增加以相對於一路徑增加另一路徑上之延遲。舉例而言，若該封裝包含上覆於各別路徑之導體上之一接地或電源平面，則可移除上覆於一個導體上之此接地或電源平面之一部分以使得此導體之長度之一部分未遮蔽，因此減小此導體與接地或電源平面之間的電容。以此方式，針對導體之未遮蔽部分之經減小電容具有減小此導體上之延遲之一效應。
另外，另一選擇係，可在適當處形成一空氣間隙以減小沿著一特定路徑之延遲，或可藉由允許具有一不同電介質常量之一特定電介質材料(例如，一囊封材料、焊料遮罩等)在製造期間流動至適合位置中而使在基板之一特定位置處之電介質常量發生變化。
圖5A至圖5B圖解說明根據上文所闡述之實施例(圖1A至圖1C)之一變化形式之一微電子封裝，其中第一及第二微電子元件212、214彼此間隔開且各自接合至基板。在此情形中，在基板230上存在未由第一或第二微電子元件212、214覆蓋之一空間238，空間238安置於微電子元件212、214之周邊邊緣229、240之間。圖5A圖解說明可根據上文所闡述之原理配置端子236及該等端子與各別微電子元件之間的路徑以針對來自一共同中心端子236(諸如展示於236A處之實例中)之每一對電連接達成匹配延遲。
圖5C圖解說明一變化形式，其中每一微電子元件312、314具有毗鄰其一周邊邊緣332安置之觸點，且至每一微電子元件之線接合352延伸穿過同一孔隙333。可根據上文所闡述之原理配置該等端子與各別微電子元件之間的路徑以針對來自封裝上之一共同端子336之每一對電連接達成匹配延遲。
圖6A至圖6B圖解說明又一變化形式，其中每一微電子元件412、414面朝上安裝於基板430上方，以使得線接合452延伸於微電子元件上之觸點至曝露於與該等端子相對之基板之一表面434處之觸點(未展示)之間。在此情形中，共同端子436A可安置於其上方安置有微電子元件之區外側之基板表面432之周邊區域處。另外或另一選擇係，端子可安置於下伏於該等微電子元件之下的基板表面之區域中(如在端子436B之情形中)，或安置於微電子元件之間的區域中(如在端子436C之情形中)。同樣，可根據上文所闡述之原理配置共同端子436與各別微電子元件之間的路徑，以針對來自封裝上之一共同端子436之每一對電連接達成匹配延遲。舉例而言，如上文所指示，可使得自一各別端子至其耦合至之觸點之連接之總電長度相同。另一選擇係或除此之外，亦可使用如上文所闡述之選擇性遮蔽或其他構件以在一各別端子與耦合至此端子之微電子元件之每一者之觸點之間的連接上達成匹配延遲。
圖6C圖解說明又一變化形式，其中每一微電子元件512、514面朝上安裝於基板上且每一微電子元件具有沿著 其一周邊邊緣532安置之觸點。至每一微電子元件之線接合552延伸超過微電子元件之毗鄰邊緣532。可根據上文所闡述之原理配置端子與各別微電子元件之間的路徑以針對來自封裝上之一共同端子536之每一對電連接達成匹配延遲。
圖7A至圖7B圖解說明又一變化形式，其中每一微電子元件612、614係覆晶安裝至基板，以使得每一微電子元件具有面向基板之一表面634上之對應基板觸點640、諸如透過一結合元件642(諸如一焊料凸塊或其他導電塊或接頭642)結合至其之觸點620。可根據上文所闡述之原理配置端子與各別微電子元件之間的路徑，以針對自封裝上之一共同端子636至第一及第二微電子元件612、614之每一者上之對應觸點之每一對電連接或每一電連接群組達成匹配延遲。
圖8圖解說明圖7A至圖7B中所展示之實施例之一變化形式，其中微電子元件712、714之一經堆疊總成790可取代微電子元件612、614中之一或多者。微電子元件712及714可係為相同或不同類型。在此情形中，每一經堆疊總成內之微電子元件之間的電連接可包含穿矽導通體730或沿著該總成之一或多個邊緣或周邊邊緣延伸之邊緣連接(未展示)或其一組合。每一微電子總成可係未封裝半導體晶片之一經堆疊總成，或可係個別經封裝晶片之一經堆疊且經電連接總成。
圖9A圖解說明又一變化形式，其中微電子封裝800包含 如其中所展示來安置之第一、第二、第三及第四微電子元件。在一特定實例中，每一微電子元件可係一DRAM晶片或可併入有一DRAM儲存陣列。在另一實例中，該等晶片可包含另一類型之記憶體，其可係非揮發性的，諸如快閃記憶體。第一及第二微電子元件812、814可間隔開並安裝至基板之一表面，同時第三及第四微電子元件816、818部分地上覆於第一及第二微電子元件上。第三及第四微電子元件816、818可彼此間隔開，每一者至少部分地上覆於第一及第二微電子元件上。沿基板之一厚度之一方向延伸穿過基板之孔隙(例如，接合窗)係展示於833、839、843及849處。微電子封裝800可以類似於2011年4月21日提出申請之共同所有之美國臨時申請案61/477,877中闡述之一實施例(圖7至圖9)之一方式配置及製造，該申請案之揭示內容以引用方式併入本文中，但特定特徵(例如，一端子與耦合至其之對應觸點之間的相對跡線長度、相對傳播延遲及用於載運特定信號之封裝端子之指派及放置)係如本文中所闡述。
如圖9A中最好所見，第一及第二孔隙833、839可經配置以使得孔隙之最長尺寸(亦即，孔隙833、839之長度)沿著由線9C-9C及線9E-9E定義之第一平行軸延伸。如進一步所見，孔隙833、839之長度沿其延伸之此等第一平行軸9C、9E橫向於孔隙843、849之最長尺寸(長度)沿其延伸之第二平行軸850、852。孔隙843、849可超過第一及第二微電子元件816、818之各別相對邊緣820、822安置。以此方式， 引線74(圖9C)可與該等第三及第四微電子元件之觸點826電耦合，引線74具有與孔隙843、849對準之部分。如上文關於圖1A至圖1D所闡述，引線74以及連接至第一及第二微電子元件812、814之觸點之引線72(圖9B)可包含或可係線接合或樑式引線。
圖9B係透過圖9A之線9B-9B之微電子封裝之一剖視圖。如其中所見，第一及第二微電子元件可彼此間隔開，其中其觸點承載表面16面向基板，且引線72具有與孔隙833、839對準之部分。如圖9A中所見，孔隙833之長度沿著其延伸之一軸9C-9C可橫穿孔隙849、843。如圖9A中進一步所見，沿孔隙839之長度之一方向延伸之軸9E-9E可橫穿孔隙843及849。圖9D係透過圖9A之線9E-9E之封裝之一視圖。在沿著線9D-9D(見圖9A)之剖面伸展於第一與第二微電子元件之間時，使用一虛線顯著地展示封裝內之第一微電子元件812之位置。
圖10中進一步圖解說明圖9A至圖9E之基板830之一中心區域及一第二或周邊區域之位置。中心區域870具有如展示於860處之邊界，該中心區域由孔隙(例如，接合窗)853、855、857、859(或更特定而言，該等孔隙之最長尺寸)定界。第一端子36通常貫穿中心區域分佈，該等第一端子中之至少某些端子之每一者電耦合至微電子元件812、814、816、818中之兩者或兩者以上之觸點。如上文所闡述，第一端子及第一端子與觸點之間的電連接可用於載運時序關鍵信號(諸如時脈信號、位址信號及命令信 號)。
第二端子136通常貫穿超過基板之中心區域870之邊緣安置之該基板之一周邊區域872分佈。該周邊區域可超過孔隙853、855、857、859安置，由基板之邊緣832、834及孔隙之邊緣(如例示性地展示於862處)定界。通常，一第二端子僅連接至一單個微電子元件之一單個觸點，但當然存在例外情況。配置封裝內之結構以使由該等第二端子載運之信號抗扭斜(亦即，使得自第二端子至觸點之傳播延遲相同)之需要並不關鍵。此乃因封裝連接至之一電路面板或板上之導電元件可經配置以在需要時將抗扭斜選擇性地提供至第二端子中之個別者。然而，一第二端子可能電耦合至封裝內之一微電子元件812、814、816或818之一個以上觸點，或電耦合至微電子元件中之一個以上微電子元件上之對應觸點。在此情形中，電位(例如，電源或接地)或由此第二端子載運之信號可係對電位或信號之到達時間之差(亦即，對「扭斜」)較不敏感之一者，且因此，在封裝上可不需要特殊配置以補償扭斜。
圖11圖解說明上文關於圖9A至圖9D及圖10所闡述之實施例之一變化形式，其中已藉由使該等微電子元件彼此間隔更遠來擴大基板之中心區域950。其上之端子及引線類似於上文所闡述之彼等端子及引線，且可為清晰起見自圖中省略。虛線960標記中心區域950與周邊區域952之間的一邊界。如在圖9A至圖9D及圖10之實施例中，中心區域960可安置於定義孔隙933、939、943、949之最長尺寸之 邊緣944、946之間。周邊區域佔據超過中心區域之基板之區。在如圖11中所見之一配置中，在某些情形中基板之中心區域可具有比周邊區域大之面積以便允許較大數目個端子配置於中心區域中。如上文所論述，可針對此中心區域內之共用端子實施用於來自共用端子之信號之抗扭斜(亦即，用於提供匹配延遲)之上文所論述組態。
圖12圖解說明微電子元件1012、1014、1016、1018在一基板上之一特定配置，類似於一風車之形狀。同樣，其上之端子及引線類似於上文所闡述之彼等端子及引線，且可為清晰起見自圖中省略。在此情形中，孔隙1043、1049之最長尺寸定義第一平行軸1050、1052，且孔隙1033、1039之最長尺寸定義第二平行軸1054、1056。該等第二平行軸橫向於該等第一平行軸。在圖12中所展示之特定實例中，當將每一微電子元件之觸點1020配置於該微電子元件之一中心區域中時，觸點1020可沿著平分微電子元件1012之一觸點承載面之一面積之一軸1050配置。另一選擇係，觸點1020可以其他方式配置成平行於軸1050延伸之一或多個平行觸點行。軸1050橫穿封裝1000中之恰好另一個微電子元件之區，亦即，軸1050橫穿微電子元件1018之區。類似地，平分微電子元件1016之觸點承載面之一面積之一軸1052可橫穿恰好另一個微電子元件1014之區。軸1054亦同樣為真，其可平分微電子元件1014之觸點承載面之面積且橫穿恰好另一個微電子元件1012之區。事實上，對微電子元件1018之一經類似地定義之軸1056而言此亦為真，其橫 穿恰好另一個微電子元件1016之區。
基板1030上之微電子元件1012、1014、1016、1018之配置定義具有大體如由虛線1072所展示之一邊界之基板之一中心區域1070，亦即，由孔隙1033、1039、1043及1049定界之一矩形區。周邊區域1074位於邊界1072外側。圖12中所展示之配置可係如圖9A至圖9D及圖10中所展示之一尤其緊密配置，但在圖12中每一微電子元件係毗鄰於基板安置而非如在圖9A至圖9D之微電子元件816、818之情形中部分地上覆於另一微電子元件上。因此，該配置可在不要求一微電子元件上覆於任何其他微電子元件上之情況下提供微電子元件與基板之一相對廣闊中心區域之一緊密配置。
在上文所闡述之實施例之變化形式中，可能將微電子元件之觸點不安置於各別微電子元件之表面之中心區域中。而是，可將該等觸點安置成毗鄰此微電子元件之一邊緣之一或多個列。在另一變化形式中，一微電子元件之觸點可毗鄰此微電子元件之兩個相對邊緣安置。在再一變化形式中，一微電子元件之觸點可毗鄰任何兩個邊緣安置，或毗鄰此微電子元件之兩個以上邊緣安置。在此等情形中，基板中之孔隙之位置可經修改以對應於毗鄰微電子元件之此邊緣或此等邊緣安置之觸點之此等位置。
圖13圖解說明圖12中所展示之實施例之一變化形式，其中省略了封裝結構中之孔隙。第一平行軸1150、1152平分微電子元件1112、1116之觸點承載面之總面積且沿平行於 彼等微電子元件之周邊邊緣1160之方向延伸。第二平行軸1154、1156平分微電子元件1114、1118之觸點承載面之總面積且沿平行於彼等微電子元件之周邊邊緣1162之方向延伸。如在圖12之實施例中，且每一軸橫穿除其平分之微電子元件外之恰好一個微電子元件之區。
在一項實施例中，該封裝結構可包含形成於微電子元件之表面上之一電介質層及定義其上之一再分佈層之導電結構(諸如上文關於圖1D所闡述)。舉例而言，金屬化導通體可耦合至每一微電子元件之觸點，且導電結構(例如，跡線)可電耦合至封裝之金屬化導通體及端子。
在另一實施例中，該封裝結構可包含具有基板觸點之一基板，該等基板觸點在該基板之一表面上。微電子元件之對應觸點可經配置以使得該等觸點面向基板觸點且以一覆晶組態結合至其，諸如藉助導電塊(例如，一種接合金屬(諸如焊料、錫、銦)、共晶組合物或其組合之塊)或其他結合材料(諸如一導電膏)。在一特定實施例中，觸點與基板觸點之間的接頭可包含一導電矩陣材料，諸如2011年6月8日提出申請及2011年6月13日提出申請之共同所有之美國申請案13/155,719及13/158,797中所闡述，該等申請案之揭示內容以引用方式併入本文中。在一特定實施例中，該等接頭可具有一類似結構或以如其中所闡述之一方式形成。
在一特定實施例中，微電子元件中之一或多者可包含具有在其上安置成一個、兩個或兩個以上平行毗鄰列之接合墊之一半導體晶片。在一特定實施例中，可將所有列之觸 點安置於此晶片之面之一中心區域中。此微電子元件可具有形成於其上之一導電再分佈層。舉例而言，此微電子元件可包含具有耦合至微電子元件之觸點20且上覆於微電子元件12之觸點承載面上之金屬化導通體92及跡線94之一再分佈層，如圖1D中所見，但此微電子元件省略半導體晶片14及連接至其之導電結構。該再分佈層可將半導體晶片12上之細節距觸點20再分佈至適合於覆晶接合至一基板1130之再分佈觸點。
在另一變化形式中，第一、第二、第三及第四微電子元件(例如，其上具有觸點(例如，接合墊)之半導體晶片1112、1114、1116及1118)可如圖13中所見來配置，一電介質層可形成於微電子元件之觸點承載面上，且可形成具有電耦合至該等觸點及電耦合至封裝之一面處之端子之金屬化導通體之一導電再分佈層。如在上文所闡述之實施例中，端子在封裝之面處可用於諸如透過結合單元(例如，焊料球以及其他)連接至一外部組件(諸如一電路面板或電路板)。
可將微電子元件1112、1114、1116、1118之觸點安置成在微電子元件之面之一中心區域內之一或多個列，例如，如上文關於圖12所闡述。另一選擇係，可跨越此微電子元件之一觸點承載面分佈一微電子元件之觸點。在此情形中，該等觸點可係微電子元件之現有導電墊，諸如在用於製造藉以製作微電子元件之一晶圓之製程期間製作。另一選擇係，該等觸點可以與起初所製造之觸點電連通地形 成。另一可能性係針對將係再分佈觸點之觸點，其亦係與起初所製造之觸點電連通地形成，其中之至少某些觸點係自起初所製造之觸點沿著微電子元件之一表面沿一或多個側向方向位移。在圖13中所展示之實施例之再一變化形式中，一微電子元件之觸點可係毗鄰此微電子元件之邊緣中之一或多者安置之周邊觸點。
圖14進一步圖解說明提供其中可安置共用端子之封裝結構之面之一中心區域1260之上文所闡述原理可適用於具有三個微電子元件之封裝。一共用端子或諸多「第一端子」中之一者可安置於中心區域1260內，其中一電連接群組可將一第一端子電耦合至第一、第二及第三微電子元件1112、1114及1116之每一者上之觸點。該封裝結構可係如上文所闡述之實施例中之任一者中所闡述。
圖15圖解說明另一實施例，其中三個微電子元件可一起封裝成一個單元。在一特定實例中，基板1130可具有第一及第二微電子元件1112、1114，第一及第二微電子元件1112、1114上各自具有與延伸於基板之第一與第二表面之間的一孔隙或接合窗1122、1124對準之觸點。如圖15中所見，該等孔隙可具有長尺寸，該等長尺寸具有沿著平行軸1132、1134延伸之長度。一軸1126沿正交於第三微電子元件之相對邊緣1118、1119之一方向平分第三微電子元件1116之一觸點承載面之一面積。平行軸1132、1134及軸1126或孔隙1122、1124及軸1126可至少部分地定界基板之中心區域1140。
在圖15中所繪示之實施例中，微電子元件1112、1114可經組態以主要提供諸如上文所闡述之記憶體儲存陣列功能。另一微電子元件1116亦可經組態以主要提供記憶體儲存陣列功能或另一功能(諸如邏輯)。
在如前述圖中之任一者中所圖解說明之上文所闡述實施例之變化形式中，其中之一或多個微電子元件可各自經組態以主要提供一記憶體儲存陣列功能，(例如)作為快閃記憶體、DRAM或其他類型之記憶體。此「記憶體」微電子元件或「記憶體晶片」可具有經組態以提供記憶體儲存陣列功能而非微電子元件之任何其他功能之較大數目個主動電路元件(例如，主動半導體裝置)。此一或多個記憶體微電子元件可與經組態以主要提供邏輯功能之另一「邏輯」微電子元件或「邏輯晶片」一起配置於一封裝中。此「邏輯」微電子元件或晶片可具有經組態以提供邏輯功能而非微電子元件之任何其他功能之較大數目個主動電路元件(例如，主動半導體裝置)。
在一特定實施例中，該邏輯晶片可係一可程式化或處理器元件(諸如一微處理器)或另一通用計算元件。該邏輯晶片可係一微控制器元件、圖形處理器、浮點處理器、共處理器、數位信號處理器等。在一特定實施例中，該邏輯晶片可主要執行硬體狀態機功能，或以其他方式經硬編碼以伺服一特定功能或目的。另一選擇係，該邏輯晶片可係一特殊應用積體電路(「ASIC」)或場可程式化閘陣列(「FPGA」)晶片。在此變化形式中，該封裝則可係一「系 統級封裝」(「SIP」)。
在另一變化形式中，封裝中之一微電子元件可具有嵌入於其中之邏輯及記憶體功能兩者，諸如在同一微電子元件中具有嵌入於其中之一或多個相關聯記憶體儲存陣列之一可程式化處理器。此微電子元件有時被稱為一「系統單晶片」(「SOC」)，此乃因邏輯件(諸如一處理器)係與用於執行某一其他功能(其可係一專用功能)之其他電路(諸如一記憶體儲存陣列或電路)一起嵌入。
上文所論述之結構可用於多種電子系統之構造。舉例而言，如圖16中所展示，根據本發明之又一實施例之一系統1200包含如上文連同其他電子組件1208及1210所闡述之一微電子封裝或結構1206。在所繪示之實例中，組件1208可係一半導體晶片或微電子封裝，而組件1210係一顯示螢幕，但亦可使用任何其他組件。當然，雖然為圖解說明之清晰起見在圖16中僅繪示兩個額外組件，但該系統可包含任一數目個此等組件。如上文所闡述之結構1206可係(舉例而言)如上文結合上文所闡述之實施例中之任一者所論述之一微電子封裝。在又一變化形式中，可提供一個以上封裝，且可使用任一數目個此等封裝。封裝1206及組件1208及1210係安裝於以虛線示意性地繪示之一共同外殼1201中，且在必要時彼此電互連以形成所期望電路。在所展示之實例性系統中，該系統包含一電路面板1202(諸如一撓性印刷電路面板或電路板)，且該電路面板包含使該等組件彼此互連之大量導體1204，圖16中僅繪示導體1204 中之一者。然而，此僅係實例性的；可使用任一適合結構來進行電連接。外殼1201係繪示為(舉例而言)可用於一蜂巢式電話或個人數位助理中之類型之一可攜式外殼，且螢幕1210曝露於該外殼之表面處。在結構1206包含一光敏元件(諸如一成像晶片)時，亦可提供一透鏡1211或其他光學裝置用於將光路由至該結構。同樣，圖16中所展示之簡化系統僅係實例性的；可使用上文所論述之結構製作其他系統(包含通常視為固定結構之系統，諸如桌上型電腦、路由器及諸如此類)。
如關於本文中之任何或所有圖所闡述之本發明之原理可適用於製造，亦即，一種製作一微電子封裝之方法。因此，一種根據本發明之一實施例製作一微電子封裝之方法可包含形成耦合第一及第二微電子元件與具有安置於其一面處之複數個端子之封裝結構之電連接(諸如在如上文所闡述之圖中所見)，該等端子係組態用於將微電子封裝連接至封裝外部之至少一個組件。該等連接可包含用於載運各別信號之連接群組，每一群組包含自封裝之一各別端子延伸至第一微電子元件上之一對應觸點之一第一連接及自該各別端子延伸至第二微電子元件上之一對應觸點之一第二連接，以使得由每一群組中之該等第一及第二連接載運之一各別信號在該各別端子與耦合至其之對應觸點之每一者之間經受相同持續時間之傳播延遲。
可根據本文中之揭示內容進行製造微電子封裝之方法，實現如上文所闡述之額外特徵或進一步增強。
在不背離本發明之精神或範疇之情況下可以除上文所具體闡述之方式外的方式組合本發明之上文所闡述實施例之各種特徵。預期本揭示內容涵蓋上文所闡述之本發明實施例之所有此等組合及變化形式。
此外，在前述內容中所闡述之實施例中之任一者中，該一或多個第二半導體晶片可以下列技術中之一或多者實施：DRAM、NAND快閃記憶體、RRAM(「電阻式RAM」或「電阻式隨機存取記憶體」)、相變記憶體(「PCM」)、磁阻式隨機存取記憶體(例如，諸如可實現穿隧接面裝置、自旋力矩RAM或內容可定址記憶體)以及其他記憶體。
雖然本文中已參考特定實施例闡述了本發明，但應理解，此等實施例僅圖解說明本發明之原理及應用。因此，應理解，在不背離隨附申請專利範圍所定義之本發明之精神及範疇之情況下，可對例示性實施例做出眾多修改且可設想出其他配置。
9B-9B‧‧‧線
9C-9C‧‧‧第一平行軸/線/軸
9D-9D‧‧‧線
9E-9E‧‧‧第一平行軸/線/軸
10‧‧‧微電子總成/封裝/微電子封裝/封裝結構
12‧‧‧第一微電子元件/微電子元件/半導體晶片
13‧‧‧中心區域
14‧‧‧微電子元件/第二微電子元件/半導體晶片
14A‧‧‧中心區域
14B‧‧‧第一周邊區域
14C‧‧‧第二周邊區域
15‧‧‧後表面
16‧‧‧前面/表面/觸點承載表面
17‧‧‧表面
20‧‧‧導電觸點/觸點/細節距觸點
20A‧‧‧導電觸點/觸點
22‧‧‧前面/表面
24‧‧‧後表面
25‧‧‧觸點承載表面
26‧‧‧觸點
26A‧‧‧導電觸點/觸點
27‧‧‧周邊邊緣/邊緣表面/邊緣
29‧‧‧周邊邊緣/邊緣表面
30‧‧‧選用基板/基板/封裝基板
31‧‧‧間隔件
32‧‧‧表面/基板表面
33‧‧‧孔隙/間隙
34‧‧‧表面
36‧‧‧端子/導電墊/中心端子
36A‧‧‧端子/共同端子/共同中心端子
36B‧‧‧端子/共同端子
36C‧‧‧端子
38‧‧‧元件
39‧‧‧孔隙/間隙
40‧‧‧導電元件/邊緣表面
40A‧‧‧導電元件/觸點
40B‧‧‧導電元件/觸點
42‧‧‧邊緣表面/邊緣
44‧‧‧中心區域
46‧‧‧周邊區域
48‧‧‧周邊區域
51A‧‧‧導電跡線/導電元件
52‧‧‧線接合
52A‧‧‧線接合/導電元件
53A‧‧‧導電跡線/導電元件
54‧‧‧線接合
60‧‧‧黏合劑
62‧‧‧囊封材料
70‧‧‧電路板
71‧‧‧觸點
72‧‧‧線接合/引線
73‧‧‧樑式引線
74‧‧‧線接合/引線
74A‧‧‧導電元件/線接合
75‧‧‧樑式引線
80‧‧‧路徑
82‧‧‧路徑/囊封材料
84‧‧‧路徑
86‧‧‧路徑
90‧‧‧電介質層
92‧‧‧金屬化導通體
94‧‧‧導電跡線/跡線
96‧‧‧導電柱/柱
102‧‧‧設置時間
104‧‧‧保持時間
110‧‧‧微電子封裝/封裝
132‧‧‧邊緣
134‧‧‧邊緣
136‧‧‧周邊端子/端子/第二端子
137‧‧‧周邊端子/端子
212‧‧‧第一微電子元件/微電子元件
214‧‧‧第二微電子元件/微電子元件
229‧‧‧周邊邊緣
236‧‧‧端子/共同中心端子
236A‧‧‧端子/共同中心端子
238‧‧‧空間
240‧‧‧周邊邊緣
312‧‧‧微電子元件
314‧‧‧微電子元件
332‧‧‧周邊邊緣
333‧‧‧孔隙
336‧‧‧共同端子
352‧‧‧線接合
412‧‧‧微電子元件
414‧‧‧微電子元件
430‧‧‧基板
432‧‧‧基板表面
434‧‧‧表面
436‧‧‧共同端子
436A‧‧‧共同端子
436B‧‧‧端子
436C‧‧‧端子
452‧‧‧線接合
512‧‧‧微電子元件
514‧‧‧微電子元件
532‧‧‧周邊邊緣/邊緣
536‧‧‧共同端子
552‧‧‧線接合
612‧‧‧微電子元件/第一微電子元件
614‧‧‧微電子元件/第二微電子元件
620‧‧‧觸點
634‧‧‧表面
636‧‧‧共同端子
640‧‧‧基板觸點
642‧‧‧結合元件/接頭
712‧‧‧微電子元件
714‧‧‧微電子元件
730‧‧‧穿矽導通體
790‧‧‧經堆疊總成
800‧‧‧微電子封裝
812‧‧‧第一微電子元件/微電子元件
814‧‧‧第二微電子元件/微電子元件
816‧‧‧第三微電子元件/微電子元件
818‧‧‧第四微電子元件/微電子元件
820‧‧‧邊緣
822‧‧‧邊緣
826‧‧‧觸點
830‧‧‧基板
832‧‧‧邊緣
833‧‧‧孔隙/第一孔隙
834‧‧‧邊緣
839‧‧‧孔隙/第二孔隙
843‧‧‧孔隙
849‧‧‧孔隙
850‧‧‧第二平行軸
852‧‧‧第二平行軸
853‧‧‧孔隙
855‧‧‧孔隙
857‧‧‧孔隙
859‧‧‧孔隙
860‧‧‧邊界
862‧‧‧邊緣
870‧‧‧中心區域
872‧‧‧周邊區域
933‧‧‧孔隙
939‧‧‧孔隙
943‧‧‧孔隙
944‧‧‧邊緣
946‧‧‧邊緣
949‧‧‧孔隙
950‧‧‧中心區域
952‧‧‧周邊區域
960‧‧‧邊界/中心區域/虛線
1000‧‧‧封裝
1012‧‧‧微電子元件
1014‧‧‧微電子元件
1016‧‧‧微電子元件
1018‧‧‧微電子元件
1020‧‧‧觸點
1030‧‧‧基板
1033‧‧‧孔隙
1039‧‧‧孔隙
1043‧‧‧孔隙
1049‧‧‧孔隙
1050‧‧‧第一平行軸/軸
1052‧‧‧第一平行軸/軸
1054‧‧‧第二平行軸/軸
1056‧‧‧第二平行軸/軸
1070‧‧‧中心區域
1072‧‧‧虛線/邊界
1074‧‧‧周邊區域
1112‧‧‧微電子元件/半導體晶片/第一微電子元件
1114‧‧‧半導體晶片/第二微電子元件/微電子元件
1116‧‧‧微電子元件/半導體晶片/第三微電子元件
1118‧‧‧微電子元件/半導體晶片/相對邊緣
1119‧‧‧相對邊緣
1122‧‧‧孔隙/接合窗
1124‧‧‧孔隙/接合窗
1126‧‧‧軸
1130‧‧‧基板
1132‧‧‧平行軸
1134‧‧‧平行軸
1140‧‧‧中心區域
1150‧‧‧第一平行軸
1152‧‧‧第一平行軸
1154‧‧‧第二平行軸
1156‧‧‧第二平行軸
1160‧‧‧周邊邊緣
1162‧‧‧周邊邊緣
1200‧‧‧系統
1201‧‧‧共同外殼/外殼
1202‧‧‧電路面板
1204‧‧‧導體
1206‧‧‧微電子封裝/結構/封裝
1208‧‧‧電子組件/組件
1210‧‧‧電子組件/組件/螢幕
1211‧‧‧透鏡
1260‧‧‧中心區域
Addr0‧‧‧信號
Addr1‧‧‧信號
Addr2‧‧‧信號
tCK‧‧‧時間
圖1係圖解說明根據先前技術在信號到達時之扭斜之一時序圖。
圖1A係圖解說明根據本發明之一實施例之一微電子封裝之一剖視圖。
圖1B係根據本發明之一實施例朝向一封裝之一端子承載表面或底部表面觀看之平面圖。
圖1C係圖解說明根據本發明之一實施例裝配有一電路面 板之一微電子封裝之一剖視圖。
圖1D係圖解說明根據圖1A至圖1C中所展示之本發明之實施例之一變化形式之一微電子封裝之一剖視圖。
圖1E係圖解說明根據圖1A至圖1C中所展示之實施例之特定實施方案之樑式引線電連接之部分片段圖。
圖2係圖解說明根據本發明之一實施例之一中心區域及周邊區域以及其中之信號端子指派之一配置之一平面圖。
圖3係圖解說明根據本發明之一實施例之第一及第二微電子元件之每一者之各別端子與觸點之間的電連接之一平面圖。
圖4係圖解說明根據本發明之一實施例之一微電子封裝之操作之一時序圖。
圖5A及圖5B係根據圖1A至圖1C中所展示之實施例之一變化形式之一微電子封裝之一平面圖及一對應剖視圖。
圖5C係根據圖1A至圖1C中所展示之實施例之一變化形式之一微電子封裝之一剖視圖。
圖6A及圖6B係根據圖1A至圖1C中所展示之實施例之一變化形式之一微電子封裝之一平面圖及一對應剖視圖。
圖6C係根據圖6A及圖6B中所展示之實施例之一變化形式之一微電子封裝之一剖視圖。
圖7A及圖7B係根據圖1A至圖1C中所展示之實施例之一變化形式之一微電子封裝之一平面圖及一對應剖視圖。
圖8係根據圖7A及圖7B中所展示之實施例之一變化形式之一微電子封裝之一剖視圖。
圖9A係根據圖1A至圖1C中所展示之實施例之一變化形式朝向一微電子封裝之一底部表面觀看之一平面圖。
圖9B係透過圖9A之線9B-9B之一剖視圖。
圖9C係透過圖9A之線9C-9C之一剖視圖。
圖9D係透過圖9A之線9D-9D之一剖視圖。
圖9E係透過圖9A之線9E-9E之一剖視圖。
圖10係進一步圖解說明如圖9A至圖9E中所展示之本發明之一實施例內之一端子配置之一平面圖。
圖11係圖解說明在圖9A至圖9E及圖10中所圖解說明之一實施例之一變化形式中之微電子元件之相對位置之一平面圖。
圖12係圖解說明在圖9A至圖9E及圖10之一實施例之一變化形式中之微電子元件之相對位置之一平面圖。
圖13係圖解說明在圖12之一實施例之一變化形式中之微電子元件之相對位置之一平面圖。
圖14係圖解說明在圖13之一實施例之一變化形式中之微電子元件之相對位置之一平面圖。
圖15係圖解說明在圖11之一實施例之一變化形式中之微電子元件之相對位置之一平面圖。
圖16係根據本發明之一實施例圖解說明一系統之一示意性剖視圖。
12‧‧‧第一微電子元件/微電子元件/半導體晶片
14‧‧‧微電子元件/第二微電子元件
20A‧‧‧導電觸點/觸點
26A‧‧‧導電觸點/觸點
32‧‧‧表面/基板表面
33‧‧‧孔隙/間隙
36‧‧‧端子/導電墊/中心端子
36A‧‧‧端子/共同端子/共同中心端子
39‧‧‧孔隙/間隙
40‧‧‧導電元件/邊緣表面
40A‧‧‧導電元件/觸點
40B‧‧‧導電元件/觸點
44‧‧‧中心區域
46‧‧‧周邊區域
48‧‧‧周邊區域
51A‧‧‧導電跡線/導電元件
52‧‧‧線接合
52A‧‧‧線接合/導電元件
53A‧‧‧導電跡線/導電元件
54‧‧‧線接合
72‧‧‧線接合/引線
74‧‧‧線接合/引線
74A‧‧‧導電元件/線接合
132‧‧‧邊緣
134‧‧‧邊緣
136‧‧‧周邊端子/端子/第二端子
137‧‧‧周邊端子/端子

Claims (32)

  1. 一種微電子封裝，其包括：封裝結構，其具有安置於其一面處之複數個端子，該等端子係組態用於將該微電子封裝連接至該封裝外部之至少一個組件；第一及第二微電子元件，其附加於該封裝結構處；連接，其等電耦合該封裝之該等端子與該等第一及第二微電子元件，該等連接包含用於載運各別信號之連接群組，每一群組包含自該封裝之一各別端子延伸至該第一微電子元件上之一對應觸點之一第一連接及自該各別端子延伸至該第二微電子元件上之一對應觸點之一第二連接，該等第一及第二連接經組態以使得由每一群組中之該等第一及第二連接載運之一各別信號在該各別端子與耦合至其之該等對應觸點之每一者之間經受相同持續時間之傳播延遲。
  2. 如請求項1之微電子封裝，其中甚至當沿著藉由該等連接之一各別群組耦合之該端子與該等各別觸點之間的直線之距離變化達大於10%時，此連接群組中之該等連接之總電長度之間的一差亦不大於10%。
  3. 如請求項1之微電子封裝，其中匹配延遲至少部分地由該等電連接中之導體相對於基板之其他導電結構之一間距差引起。
  4. 一種包含如請求項1之微電子封裝之微電子總成，其進一步包括具有電路觸點之一電路面板，其中該封裝之該 等端子電連接至該等電路觸點。
  5. 如請求項1之微電子封裝，其中該等信號之至少一者係一時脈信號或一命令信號。
  6. 如請求項1之微電子封裝，其中該等信號包含複數個位址信號及用以取樣該等位址信號之一取樣信號。
  7. 如請求項6之微電子封裝，其中該等信號進一步包含一命令選通信號。
  8. 如請求項1之微電子封裝，其中該各別信號在每一群組內之該等第一及第二連接上之該傳播延遲之該相同持續時間係在彼信號之循環時間之10%之一容差內。
  9. 如請求項1之微電子封裝，其進一步包括附加於該封裝結構處之一第三微電子元件，其中該等連接群組之至少一者包含將該各別端子電耦合至該第三微電子元件之一對應觸點用於將該各別信號載運至其之一第三連接，其中由該等第一、第二及第三連接載運之該信號在該各別端子與耦合至其之該等對應觸點之每一者之間經受該相同持續時間之傳播延遲。
  10. 如請求項9之微電子封裝，其進一步包括附加於該封裝結構處之一第四微電子元件，其中該等連接群組之至少一者包含將該各別端子電耦合至該第四微電子元件之一對應觸點用於將該各別信號載運至其之一第四連接，其中由該等第一、第二、第三及第四連接載運之該信號在該各別端子與耦合至其之該等對應觸點之每一者之間經受該相同持續時間之傳播延遲。
  11. 如請求項1之微電子封裝，其中該封裝結構具有定界該面之邊緣，該面具有佔據其一中心部分之一中心區域及佔據該中心部分與該等邊緣之至少一者之間的該面之一部分之一第二區域，該等端子包含曝露於該中心區域處之第一端子及曝露於該第二區域處之第二端子，其中該等連接群組耦合該等第一端子與該等對應觸點，其中該微電子封裝包含電耦合該等第二端子與該等微電子元件之觸點之進一步連接。
  12. 如請求項11之微電子封裝，其中該封裝結構包含具有第一及第二相對表面之一基板，該第一表面背對該等微電子元件且該第二表面面朝該等微電子元件，至少第一及第二孔隙延伸於該等第一與第二表面之間，該等孔隙具有帶有沿著彼此平行之軸延伸之長度之長尺寸，其中該中心區域至少部分地由該等第一及第二孔隙定界，且該等連接包含具有與該等第一或第二孔隙之至少一者對準之部分之引線。
  13. 如請求項12之微電子封裝，其進一步包括各自附加於該封裝結構處之第三及第四微電子元件，其中該等連接群組之至少一者包含將該各別端子電耦合至該等第三及第四微電子元件之對應觸點用於將該各別信號載運至其之第三及第四連接，其中由該等第一、第二、第三及第四連接載運之該信號在該各別端子與耦合至其之該等對應觸點之每一者之間經受該相同持續時間之傳播延遲，其中該等平行軸係第一平行軸，且 該基板進一步包含延伸於該等第一與第二表面之間的第三及第四孔隙，該等第三及第四孔隙具有帶有沿著彼此平行之第二軸延伸之長度之長尺寸，該等第二平行軸橫向於該等第一平行軸，其中該中心區域至少部分地由該等第三及第四孔隙定界，且該等連接包含具有與該等第三或第四孔隙之至少一者對準之部分之引線。
  14. 如請求項13之微電子封裝，其中具有與該等孔隙之至少一者對準之部分之該等引線包含線接合。
  15. 如請求項14之微電子封裝，其中該等第一、第二、第三及第四微電子元件之每一者經組態以主要提供一記憶體儲存功能。
  16. 如請求項11之微電子封裝，其進一步包括各自附加於該封裝結構處之第三及第四微電子元件，其中該等連接群組之至少一者包含將該各別端子電耦合至該等第三及第四微電子元件之對應觸點用於將該各別信號載運至其之第三及第四連接，其中由該等第一、第二、第三及第四連接載運之該信號在該各別端子與耦合至其之該等對應觸點之每一者之間經受該相同持續時間之傳播延遲，其中該面之該中心區域由第一平行軸及橫向於該等第一平行軸之第二平行軸定界，每一第一軸分別平分該等第一及第二微電子元件中之一者之一面積且沿平行於該等第一及第二微電子元件之每一者之第一及第二相對邊緣之一方向延伸，且每一第二軸分別平分該等第三及第 四微電子元件中之一者之一面積且沿平行於該等第三及第四微電子元件之每一者之第一及第二相對邊緣之一方向延伸。
  17. 如請求項16之微電子封裝，其中該封裝結構包含具有在面向該等微電子元件之一表面處之觸點之一基板，該等微電子元件之該等觸點面向該等基板觸點且結合至其。
  18. 如請求項16之微電子封裝，其中該等第一平行軸之每一者橫穿該等第三或第四微電子元件中之恰好一者，且該等第二平行軸之每一者橫穿該等第一或第二微電子元件中之恰好一者。
  19. 一種包含如請求項1之微電子封裝之微電子總成，其進一步包括具有毗鄰且電連接至該等端子之面板觸點之一電路面板，該電路面板上具有提供延遲匹配之導電元件，以使得由每一連接群組載運至該等微電子元件之信號穿過該封裝封裝結構及該電路面板經受相同持續時間之延遲。
  20. 如請求項1之微電子封裝，其中該等第一及第二微電子元件沿平行於該封裝結構之該面之一方向彼此間隔開。
  21. 如請求項1之微電子封裝，其中該封裝結構包含一基板，該基板具有延伸穿過其之至少一個孔隙，且該第二微電子元件部分地上覆於該第一微電子元件上以使得該第二微電子元件之觸點係超過該第一微電子元件之一邊緣安置，其中對該第二微電子元件之該等對應觸點之該等連接包含具有與該至少一個孔隙對準之部分之引線。
  22. 如請求項21之微電子封裝，其中該第二微電子元件之一面係朝向該第一微電子元件及該基板定向，且該第二微電子元件之該等觸點係安置於該第二微電子元件之該面之一中心區域中。
  23. 如請求項22之微電子封裝，其中該第一微電子元件之一面係朝向該基板且背對該第二微電子元件定向，且該第一微電子元件之該等觸點係安置於該第一微電子元件之該面之一中心區域中。
  24. 如請求項21之微電子封裝，其中該等引線包含延伸穿過該至少一個孔隙之線接合。
  25. 如請求項21之微電子封裝，其中該至少一個孔隙包含第一及第二接合窗，該等連接包含耦合至具有與該第一接合窗對準之部分之該第一微電子元件之第一引線及耦合至具有與該第二接合窗對準之部分之該第二微電子元件之第二引線。
  26. 如請求項25之微電子封裝，其中該等端子中之該等第一及第二引線與其耦合之至少某些端子係安置於該等第一與第二接合窗之間。
  27. 如請求項1之微電子封裝，其中該第一微電子元件具有在其一前面處及與該前面相對之一後面處之觸點，該後面係安裝至該封裝結構，其中該等引線包含連接於該等觸點與該封裝結構之間的線接合。
  28. 如請求項1之微電子封裝，其中該等第一或第二微電子元件之至少一者包含一記憶體儲存陣列且該等第一或第 二微電子元件之至少一者包含一微控制器。
  29. 如請求項1之微電子封裝，其中該封裝結構包含：一電介質層，其形成於該等第一及第二微電子元件之該等觸點承載表面上；跡線，其沿平行於該電介質層之一方向延伸；及金屬化導通體，其至少部分地延伸穿過該電介質層之一厚度且與該等第一及第二微電子元件之該等觸點電耦合，其中該等端子藉由該等跡線及該等導通體電連接至該等觸點。
  30. 一種製作一微電子封裝之方法，其包括：形成耦合第一及第二微電子元件與具有安置於其一面處之複數個端子之封裝結構之電連接，該等端子係組態用於將該微電子封裝連接至該封裝外部之至少一個組件，該等連接包含用於載運各別信號之連接群組，每一群組包含自該封裝之一各別端子延伸至該第一微電子元件上之一對應觸點之一第一連接及自該各別端子延伸至該第二微電子元件上之一對應觸點之一第二連接，該等第一及第二連接經組態以使得由每一群組中之該等第一及第二連接載運之一各別信號在該各別端子與耦合至其之該等對應觸點之每一者之間經受相同持續時間之傳播延遲。
  31. 如請求項30之製作該微電子封裝之方法，其中該封裝結構具有定界該面之邊緣，該面具有佔據其一中心部分之一中心區域及佔據該中心部分與該等邊 緣之至少一者之間的該面之一部分之一第二區域，該等端子包含曝露於該中心區域處之第一端子及曝露於該第二區域處之第二端子，其中該等連接群組耦合該等第一端子與該等對應觸點，且其中該微電子封裝包含電耦合該等第二端子與該等微電子元件之觸點之進一步連接。
  32. 如請求項30之製作該微電子封裝之方法，其中該封裝結構包含一基板，該基板具有延伸穿過其之至少一個孔隙，且該第二微電子元件部分地上覆於該第一微電子元件上以使得超過該第一微電子元件之一邊緣安置該第二微電子元件之觸點，其中對該第二微電子元件之該等對應觸點之該等連接包含具有與該至少一個孔隙對準之部分之引線。
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Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8553420B2 (en) 2010-10-19 2013-10-08 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
US8633576B2 (en) 2011-04-21 2014-01-21 Tessera, Inc. Stacked chip-on-board module with edge connector
US8928153B2 (en) 2011-04-21 2015-01-06 Tessera, Inc. Flip-chip, face-up and face-down centerbond memory wirebond assemblies
US8970028B2 (en) 2011-12-29 2015-03-03 Invensas Corporation Embedded heat spreader for package with multiple microelectronic elements and face-down connection
US9013033B2 (en) 2011-04-21 2015-04-21 Tessera, Inc. Multiple die face-down stacking for two or more die
US8952516B2 (en) 2011-04-21 2015-02-10 Tessera, Inc. Multiple die stacking for two or more die
US8502390B2 (en) * 2011-07-12 2013-08-06 Tessera, Inc. De-skewed multi-die packages
US8823165B2 (en) 2011-07-12 2014-09-02 Invensas Corporation Memory module in a package
JP5887415B2 (ja) 2011-10-03 2016-03-16 インヴェンサス・コーポレイション 平行な窓を有するマルチダイのワイヤボンドアセンブリのスタブ最小化
US8653646B2 (en) 2011-10-03 2014-02-18 Invensas Corporation Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
KR20140069343A (ko) 2011-10-03 2014-06-09 인벤사스 코포레이션 패키지의 중심으로부터 옵셋된 단자 그리드를 구비하는 스터드 최소화
US8659139B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
JP5947904B2 (ja) 2011-10-03 2016-07-06 インヴェンサス・コーポレイション 直交するウインドウを有するマルチダイ・ワイヤボンド・アセンブリのためのスタブ最小化
US8610260B2 (en) 2011-10-03 2013-12-17 Invensas Corporation Stub minimization for assemblies without wirebonds to package substrate
US8659143B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization for wirebond assemblies without windows
US10136516B2 (en) * 2012-03-13 2018-11-20 Intel Corporation Microelectronic device attachment on a reverse microelectronic package
US8787034B2 (en) 2012-08-27 2014-07-22 Invensas Corporation Co-support system and microelectronic assembly
US8848391B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support component and microelectronic assembly
US9368477B2 (en) 2012-08-27 2016-06-14 Invensas Corporation Co-support circuit panel and microelectronic packages
US8848392B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support module and microelectronic assembly
US9070423B2 (en) 2013-06-11 2015-06-30 Invensas Corporation Single package dual channel memory with co-support
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US9123555B2 (en) 2013-10-25 2015-09-01 Invensas Corporation Co-support for XFD packaging
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
JP2015216263A (ja) * 2014-05-12 2015-12-03 マイクロン テクノロジー， インク． 半導体装置
US9281296B2 (en) 2014-07-31 2016-03-08 Invensas Corporation Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design
US9991239B2 (en) 2014-09-18 2018-06-05 Intel Corporation Method of embedding WLCSP components in e-WLB and e-PLB
US9691437B2 (en) 2014-09-25 2017-06-27 Invensas Corporation Compact microelectronic assembly having reduced spacing between controller and memory packages
US9245870B1 (en) 2014-10-17 2016-01-26 Qualcomm Incorporated Systems and methods for providing data channels at a die-to-die interface
US9799628B2 (en) 2015-03-31 2017-10-24 Qualcomm Incorporated Stacked package configurations and methods of making the same
US9484080B1 (en) 2015-11-09 2016-11-01 Invensas Corporation High-bandwidth memory application with controlled impedance loading
US9679613B1 (en) 2016-05-06 2017-06-13 Invensas Corporation TFD I/O partition for high-speed, high-density applications
US10297575B2 (en) * 2016-05-06 2019-05-21 Amkor Technology, Inc. Semiconductor device utilizing an adhesive to attach an upper package to a lower die
US10354976B2 (en) 2016-07-22 2019-07-16 Invensas Corporation Dies-on-package devices and methods therefor
KR102509049B1 (ko) * 2016-08-22 2023-03-13 에스케이하이닉스 주식회사 수직 적층된 칩들을 포함하는 팬 아웃 패키지
US10424921B2 (en) 2017-02-16 2019-09-24 Qualcomm Incorporated Die-to-die interface configuration and methods of use thereof
CN112802835A (zh) * 2017-06-02 2021-05-14 超极存储器股份有限公司 半导体模块
CN108364878B (zh) * 2018-02-01 2019-09-17 深圳市华讯方舟微电子科技有限公司 微组装方法及芯片装置

Family Cites Families (152)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3670208A (en) 1970-07-13 1972-06-13 Logic Dynamics Inc Microelectronic package, buss strip and printed circuit base assembly
JPS56107845A (en) * 1980-01-30 1981-08-27 Tokai Rubber Ind Ltd Method of press fitting aluminum pipe into aluminum piece
US5679977A (en) 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US5148266A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5369552A (en) 1992-07-14 1994-11-29 Ncr Corporation Multi-chip module with multiple compartments
JPH0823149A (ja) 1994-05-06 1996-01-23 Seiko Epson Corp 半導体装置及びその製造方法
SE509201C2 (sv) 1994-07-20 1998-12-14 Sandvik Ab Aluminiumoxidbelagt verktyg
JP3487524B2 (ja) 1994-12-20 2004-01-19 株式会社ルネサステクノロジ 半導体装置及びその製造方法
US5929517A (en) 1994-12-29 1999-07-27 Tessera, Inc. Compliant integrated circuit package and method of fabricating the same
EP0829187A2 (en) 1995-05-26 1998-03-18 Rambus Inc. Chip socket assembly and chip file assembly for semiconductor chips
JP3869045B2 (ja) 1995-11-09 2007-01-17 株式会社日立製作所 半導体記憶装置
US5696031A (en) 1996-11-20 1997-12-09 Micron Technology, Inc. Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
TW312044B (en) * 1996-02-23 1997-08-01 Mitsubishi Electric Corp The semiconductor package
US6460245B1 (en) 1996-03-07 2002-10-08 Tessera, Inc. Method of fabricating semiconductor chip assemblies
JP2000512065A (ja) 1996-05-24 2000-09-12 テセラ，インコーポレイテッド 超小型電子素子のコネクタ
US6130116A (en) 1996-12-13 2000-10-10 Tessera, Inc. Method of encapsulating a microelectronic assembly utilizing a barrier
US6323436B1 (en) 1997-04-08 2001-11-27 International Business Machines Corporation High density printed wiring board possessing controlled coefficient of thermal expansion with thin film redistribution layer
JPH1143503A (ja) 1997-07-25 1999-02-16 Nippon Mektron Ltd 変性アクリル系ゴムの製造法
US6525414B2 (en) 1997-09-16 2003-02-25 Matsushita Electric Industrial Co., Ltd. Semiconductor device including a wiring board and semiconductor elements mounted thereon
US5899705A (en) 1997-11-20 1999-05-04 Akram; Salman Stacked leads-over chip multi-chip module
US6343019B1 (en) 1997-12-22 2002-01-29 Micron Technology, Inc. Apparatus and method of stacking die on a substrate
US6742098B1 (en) 2000-10-03 2004-05-25 Intel Corporation Dual-port buffer-to-memory interface
US6261867B1 (en) 1998-03-13 2001-07-17 Stratedge Corporation Method of making a package for microelectronic devices using iron oxide as a bonding agent
US6197665B1 (en) 1998-04-15 2001-03-06 Tessera, Inc. Lamination machine and method to laminate a coverlay to a microelectronic package
US6297960B1 (en) 1998-06-30 2001-10-02 Micron Technology, Inc. Heat sink with alignment and retaining features
US6815251B1 (en) 1999-02-01 2004-11-09 Micron Technology, Inc. High density modularity for IC's
JP3914651B2 (ja) 1999-02-26 2007-05-16 エルピーダメモリ株式会社 メモリモジュールおよびその製造方法
JP2000315776A (ja) 1999-05-06 2000-11-14 Hitachi Ltd 半導体装置
US6376769B1 (en) 1999-05-18 2002-04-23 Amerasia International Technology, Inc. High-density electronic package, and method for making same
JP2000340737A (ja) 1999-05-31 2000-12-08 Mitsubishi Electric Corp 半導体パッケージとその実装体
KR100393095B1 (ko) 1999-06-12 2003-07-31 앰코 테크놀로지 코리아 주식회사 반도체패키지와 그 제조방법
US6252264B1 (en) 1999-07-30 2001-06-26 International Business Machines Corporation Integrated circuit chip with features that facilitate a multi-chip module having a number of the chips
JP2001053243A (ja) 1999-08-06 2001-02-23 Hitachi Ltd 半導体記憶装置とメモリモジュール
SG83742A1 (en) 1999-08-17 2001-10-16 Micron Technology Inc Multi-chip module with extension
US6255899B1 (en) * 1999-09-01 2001-07-03 International Business Machines Corporation Method and apparatus for increasing interchip communications rates
US6307769B1 (en) 1999-09-02 2001-10-23 Micron Technology, Inc. Semiconductor devices having mirrored terminal arrangements, devices including same, and methods of testing such semiconductor devices
JP2001203318A (ja) 1999-12-17 2001-07-27 Texas Instr Inc <Ti> 複数のフリップチップを備えた半導体アセンブリ
JP3768761B2 (ja) 2000-01-31 2006-04-19 株式会社日立製作所 半導体装置およびその製造方法
JP2001223324A (ja) 2000-02-10 2001-08-17 Mitsubishi Electric Corp 半導体装置
US6713854B1 (en) 2000-10-16 2004-03-30 Legacy Electronics, Inc Electronic circuit module with a carrier having a mounting pad array
KR100408616B1 (ko) 2000-03-21 2003-12-03 미쓰비시덴키 가부시키가이샤 반도체 장치, 전자 기기의 제조 방법, 전자 기기 및 휴대정보 단말
US6384473B1 (en) 2000-05-16 2002-05-07 Sandia Corporation Microelectronic device package with an integral window
TW445608B (en) 2000-05-19 2001-07-11 Siliconware Precision Industries Co Ltd Semiconductor package and manufacturing method thereof of lead frame without flashing
JP2001339043A (ja) 2000-05-30 2001-12-07 Mitsubishi Electric Corp 半導体装置及びそれを用いた半導体モジュール
US6462423B1 (en) * 2000-08-31 2002-10-08 Micron Technology, Inc. Flip-chip with matched lines and ground plane
JP2002076252A (ja) 2000-08-31 2002-03-15 Nec Kyushu Ltd 半導体装置
US6577004B1 (en) 2000-08-31 2003-06-10 Micron Technology, Inc. Solder ball landpad design to improve laminate performance
JP3874062B2 (ja) 2000-09-05 2007-01-31 セイコーエプソン株式会社 半導体装置
US6980184B1 (en) 2000-09-27 2005-12-27 Alien Technology Corporation Display devices and integrated circuits
DE10055001A1 (de) 2000-11-07 2002-05-16 Infineon Technologies Ag Speicheranordnung mit einem zentralen Anschlussfeld
US20020122902A1 (en) 2000-11-30 2002-09-05 Tetsuji Ueda Blank for an optical member as well as vessel and method of producing the same
US6628528B2 (en) * 2000-11-30 2003-09-30 Theodore Zale Schoenborn Current sharing in memory packages
US6798044B2 (en) 2000-12-04 2004-09-28 Fairchild Semiconductor Corporation Flip chip in leaded molded package with two dies
US6528408B2 (en) 2001-05-21 2003-03-04 Micron Technology, Inc. Method for bumped die and wire bonded board-on-chip package
DE10126310B4 (de) 2001-05-30 2006-05-18 Infineon Technologies Ag Leiterplattenvorrichtung, deren Verwendung und Halbleiterspeichervorrichtung
KR100415281B1 (ko) 2001-06-29 2004-01-16 삼성전자주식회사 양면 실장형 회로 기판 및 이를 포함하는 멀티 칩 패키지
DE10139085A1 (de) 2001-08-16 2003-05-22 Infineon Technologies Ag Leiterplattensystem, Verfahren zum Betreiben eines Leiterplattensystems, Leiterplatteneinrichtung und deren Verwendung, und Halbleitervorrichtung und deren Verwendung
KR100454123B1 (ko) 2001-12-06 2004-10-26 삼성전자주식회사 반도체 집적 회로 장치 및 그것을 구비한 모듈
US6692987B2 (en) 2001-12-12 2004-02-17 Micron Technology, Inc. BOC BGA package for die with I-shaped bond pad layout
SG118103A1 (en) 2001-12-12 2006-01-27 Micron Technology Inc BOC BGA package for die with I-shaped bond pad layout
US6686819B2 (en) 2002-02-01 2004-02-03 Intel Corporation Dual referenced microstrip
US6982485B1 (en) 2002-02-13 2006-01-03 Amkor Technology, Inc. Stacking structure for semiconductor chips and a semiconductor package using it
US7109588B2 (en) 2002-04-04 2006-09-19 Micron Technology, Inc. Method and apparatus for attaching microelectronic substrates and support members
KR100460063B1 (ko) 2002-05-03 2004-12-04 주식회사 하이닉스반도체 센터 패드 칩 적층 볼 그리드 어레이 패키지 및 그 제조방법
US6906415B2 (en) 2002-06-27 2005-06-14 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor devices and methods
JP2004063767A (ja) 2002-07-29 2004-02-26 Renesas Technology Corp 半導体装置
DE10234951B4 (de) * 2002-07-31 2009-01-02 Qimonda Ag Verfahren zur Herstellung von Halbleiterschaltungsmodulen
US6765288B2 (en) 2002-08-05 2004-07-20 Tessera, Inc. Microelectronic adaptors, assemblies and methods
JP4221238B2 (ja) 2002-09-26 2009-02-12 エルピーダメモリ株式会社 メモリモジュール
JP2004128155A (ja) 2002-10-01 2004-04-22 Renesas Technology Corp 半導体パッケージ
TWI221664B (en) 2002-11-07 2004-10-01 Via Tech Inc Structure of chip package and process thereof
US7550842B2 (en) 2002-12-12 2009-06-23 Formfactor, Inc. Integrated circuit assembly
DE10259221B4 (de) 2002-12-17 2007-01-25 Infineon Technologies Ag Elektronisches Bauteil mit einem Stapel aus Halbleiterchips und Verfahren zur Herstellung desselben
JP2004221215A (ja) 2003-01-14 2004-08-05 Renesas Technology Corp 半導体装置
US6876088B2 (en) 2003-01-16 2005-04-05 International Business Machines Corporation Flex-based IC package construction employing a balanced lamination
US6879028B2 (en) 2003-02-21 2005-04-12 Freescale Semiconductor, Inc. Multi-die semiconductor package
JP4072505B2 (ja) 2003-02-28 2008-04-09 エルピーダメモリ株式会社 積層型半導体パッケージ
TW200419752A (en) 2003-03-18 2004-10-01 United Test Ct Inc Semiconductor package with heat sink
JP4046026B2 (ja) 2003-06-27 2008-02-13 株式会社日立製作所 半導体装置
US7145226B2 (en) 2003-06-30 2006-12-05 Intel Corporation Scalable microelectronic package using conductive risers
US7183643B2 (en) 2003-11-04 2007-02-27 Tessera, Inc. Stacked packages and systems incorporating the same
US7061121B2 (en) 2003-11-12 2006-06-13 Tessera, Inc. Stacked microelectronic assemblies with central contacts
US7989940B2 (en) 2003-12-19 2011-08-02 Tessera, Inc. System and method for increasing the number of IO-s on a ball grid package by wire bond stacking of same size packages through apertures
CN1638120A (zh) 2003-12-26 2005-07-13 恩益禧电子股份有限公司 半导体组装体及其制造方法
US7181584B2 (en) 2004-02-05 2007-02-20 Micron Technology, Inc. Dynamic command and/or address mirroring system and method for memory modules
JP4647243B2 (ja) 2004-05-24 2011-03-09 ルネサスエレクトロニクス株式会社 半導体装置
JP4543755B2 (ja) * 2004-05-31 2010-09-15 パナソニック株式会社 半導体集積回路
KR20050119414A (ko) 2004-06-16 2005-12-21 삼성전자주식회사 에지 패드형 반도체 칩의 스택 패키지 및 그 제조방법
JP4865197B2 (ja) 2004-06-30 2012-02-01 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US7260691B2 (en) 2004-06-30 2007-08-21 Intel Corporation Apparatus and method for initialization of a double-sided DIMM having at least one pair of mirrored pins
JP4058642B2 (ja) 2004-08-23 2008-03-12 セイコーエプソン株式会社 半導体装置
US6943057B1 (en) 2004-08-31 2005-09-13 Stats Chippac Ltd. Multichip module package and fabrication method
US7324352B2 (en) 2004-09-03 2008-01-29 Staktek Group L.P. High capacity thin module system and method
US20060081983A1 (en) 2004-10-14 2006-04-20 Giles Humpston Wafer level microelectronic packaging with double isolation
TWI256092B (en) 2004-12-02 2006-06-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabrication method thereof
JP2006172122A (ja) 2004-12-15 2006-06-29 Toshiba Corp カード状記憶装置
KR100615606B1 (ko) 2005-03-15 2006-08-25 삼성전자주식회사 메모리 모듈 및 이 모듈의 신호 라인 배치 방법
JP4707446B2 (ja) * 2005-04-26 2011-06-22 富士通セミコンダクター株式会社 半導体装置
KR101070913B1 (ko) 2005-05-19 2011-10-06 삼성테크윈 주식회사 반도체 칩 적층 패키지
US7414312B2 (en) 2005-05-24 2008-08-19 Kingston Technology Corp. Memory-module board layout for use with memory chips of different data widths
US7402911B2 (en) 2005-06-28 2008-07-22 Infineon Technologies Ag Multi-chip device and method for producing a multi-chip device
US7414917B2 (en) 2005-07-29 2008-08-19 Infineon Technologies Re-driving CAwD and rD signal lines
US7372169B2 (en) 2005-10-11 2008-05-13 Via Technologies, Inc. Arrangement of conductive pads on grid array package and on circuit board
JP4906047B2 (ja) 2005-11-28 2012-03-28 ルネサスエレクトロニクス株式会社 半導体装置
TWI279897B (en) 2005-12-23 2007-04-21 Phoenix Prec Technology Corp Embedded semiconductor chip structure and method for fabricating the same
US20080185705A1 (en) 2005-12-23 2008-08-07 Tessera, Inc. Microelectronic packages and methods therefor
US20070187836A1 (en) 2006-02-15 2007-08-16 Texas Instruments Incorporated Package on package design a combination of laminate and tape substrate, with back-to-back die combination
KR20070088177A (ko) 2006-02-24 2007-08-29 삼성테크윈 주식회사 반도체 패키지 및 그 제조 방법
US7368319B2 (en) 2006-03-17 2008-05-06 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
US20070241441A1 (en) 2006-04-17 2007-10-18 Stats Chippac Ltd. Multichip package system
JP5026736B2 (ja) 2006-05-15 2012-09-19 パナソニックヘルスケア株式会社 冷凍装置
US7535110B2 (en) 2006-06-15 2009-05-19 Marvell World Trade Ltd. Stack die packages
SG139573A1 (en) 2006-07-17 2008-02-29 Micron Technology Inc Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods
DE102006042775B3 (de) 2006-09-12 2008-03-27 Qimonda Ag Schaltungsmodul und Verfahren zur Herstellung eines Schaltungsmoduls
US7472477B2 (en) 2006-10-12 2009-01-06 International Business Machines Corporation Method for manufacturing a socket that compensates for differing coefficients of thermal expansion
US20080088030A1 (en) * 2006-10-16 2008-04-17 Formfactor, Inc. Attaching and interconnecting dies to a substrate
US7719121B2 (en) 2006-10-17 2010-05-18 Tessera, Inc. Microelectronic packages and methods therefor
US7870459B2 (en) 2006-10-23 2011-01-11 International Business Machines Corporation High density high reliability memory module with power gating and a fault tolerant address and command bus
US7692278B2 (en) 2006-12-20 2010-04-06 Intel Corporation Stacked-die packages with silicon vias and surface activated bonding
US7518226B2 (en) 2007-02-06 2009-04-14 Stats Chippac Ltd. Integrated circuit packaging system with interposer
JP2008198841A (ja) 2007-02-14 2008-08-28 Elpida Memory Inc 半導体装置
CN101617371B (zh) * 2007-02-16 2014-03-26 莫塞德技术公司 具有多个外部电源的非易失性半导体存储器
JP4751351B2 (ja) 2007-02-20 2011-08-17 株式会社東芝 半導体装置とそれを用いた半導体モジュール
JP4913640B2 (ja) 2007-03-19 2012-04-11 ルネサスエレクトロニクス株式会社 半導体装置
US7696629B2 (en) 2007-04-30 2010-04-13 Chipmos Technology Inc. Chip-stacked package structure
US7906853B2 (en) 2007-09-06 2011-03-15 Micron Technology, Inc. Package structure for multiple die stack
KR20090043898A (ko) 2007-10-30 2009-05-07 삼성전자주식회사 스택 패키지 및 그 제조 방법, 및 스택 패키지를 포함하는카드 및 시스템
US9460951B2 (en) 2007-12-03 2016-10-04 STATS ChipPAC Pte. Ltd. Semiconductor device and method of wafer level package integration
JP5207868B2 (ja) 2008-02-08 2013-06-12 ルネサスエレクトロニクス株式会社 半導体装置
TWM338433U (en) 2008-02-14 2008-08-11 Orient Semiconductor Elect Ltd Multi-chip package structure
JP2009200101A (ja) 2008-02-19 2009-09-03 Liquid Design Systems:Kk 半導体チップ及び半導体装置
US8228679B2 (en) 2008-04-02 2012-07-24 Spansion Llc Connections for electronic devices on double-sided circuit board
TWI362732B (en) 2008-04-07 2012-04-21 Nanya Technology Corp Multi-chip stack package
US7838975B2 (en) 2008-05-27 2010-11-23 Mediatek Inc. Flip-chip package with fan-out WLCSP
US7745920B2 (en) 2008-06-10 2010-06-29 Micron Technology, Inc. Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
US8276269B2 (en) 2008-06-20 2012-10-02 Intel Corporation Dual epoxy dielectric and photosensitive solder mask coatings, and processes of making same
JP2010056139A (ja) 2008-08-26 2010-03-11 Toshiba Corp 積層型半導体装置
JP5056718B2 (ja) 2008-10-16 2012-10-24 株式会社デンソー 電子装置の製造方法
KR20100046760A (ko) 2008-10-28 2010-05-07 삼성전자주식회사 반도체 패키지
US7839163B2 (en) 2009-01-22 2010-11-23 International Business Machines Corporation Programmable through silicon via
TWI401785B (zh) 2009-03-27 2013-07-11 Chipmos Technologies Inc 多晶片堆疊封裝
EP2419971A4 (en) 2009-04-17 2013-03-27 Hewlett Packard Co METHOD AND SYSTEM FOR REDUCING LENGTH AND TRACE CAPACITY IN IMPORTANT MEMORY FOOTPRINT
KR101601847B1 (ko) 2009-05-21 2016-03-09 삼성전자주식회사 반도체 패키지
JP2010278318A (ja) 2009-05-29 2010-12-09 Renesas Electronics Corp 半導体装置
JP5635247B2 (ja) 2009-08-20 2014-12-03 富士通株式会社 マルチチップモジュール
US8907457B2 (en) 2010-02-08 2014-12-09 Micron Technology, Inc. Microelectronic devices with through-substrate interconnects and associated methods of manufacturing
US8395195B2 (en) 2010-02-09 2013-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Bottom-notched SiGe FinFET formation using condensation
US8847376B2 (en) 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
JP4979097B2 (ja) * 2010-12-06 2012-07-18 ルネサスエレクトロニクス株式会社 マルチチップモジュール
US8502390B2 (en) * 2011-07-12 2013-08-06 Tessera, Inc. De-skewed multi-die packages

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US20130015586A1 (en) 2013-01-17
US8759982B2 (en) 2014-06-24
KR20140057544A (ko) 2014-05-13
US20130307138A1 (en) 2013-11-21
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