TW200721163A - Low power memory control circuits and methods - Google Patents
Low power memory control circuits and methodsInfo
- Publication number
- TW200721163A TW200721163A TW095134955A TW95134955A TW200721163A TW 200721163 A TW200721163 A TW 200721163A TW 095134955 A TW095134955 A TW 095134955A TW 95134955 A TW95134955 A TW 95134955A TW 200721163 A TW200721163 A TW 200721163A
- Authority
- TW
- Taiwan
- Prior art keywords
- methods
- circuits
- source transistors
- taught
- integrated circuit
- Prior art date
Links
- 230000007246 mechanism Effects 0.000 abstract 1
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/065—Differential amplifiers of latching type
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/08—Control thereof
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/06—Sense amplifier related aspects
- G11C2207/065—Sense amplifier drivers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2227—Standby or low power modes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4068—Voltage or leakage in refresh operations
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US72018505P | 2005-09-23 | 2005-09-23 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW200721163A true TW200721163A (en) | 2007-06-01 |
Family
ID=37900366
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW095134955A TW200721163A (en) | 2005-09-23 | 2006-09-21 | Low power memory control circuits and methods |
Country Status (7)
Country | Link |
---|---|
US (2) | US7929367B2 (zh) |
EP (1) | EP1934981A4 (zh) |
JP (1) | JP2009512961A (zh) |
KR (1) | KR101350920B1 (zh) |
CN (1) | CN101501778A (zh) |
TW (1) | TW200721163A (zh) |
WO (1) | WO2007038448A2 (zh) |
Cited By (2)
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TWI418987B (zh) * | 2008-06-30 | 2013-12-11 | Intel Corp | 藉由細微間隔之預充電管理使記憶體處理量增加之技術 |
TWI824233B (zh) * | 2020-02-12 | 2023-12-01 | 美商新思科技股份有限公司 | 具有漏電流中的統計變化之動態隨機存取記憶體通路電晶體的設計 |
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KR20090113560A (ko) * | 2008-04-28 | 2009-11-02 | 삼성전자주식회사 | 안정적인 동작을 보장하는 반도체 장치 |
US7692975B2 (en) * | 2008-05-09 | 2010-04-06 | Micron Technology, Inc. | System and method for mitigating reverse bias leakage |
KR101001145B1 (ko) | 2008-12-26 | 2010-12-17 | 주식회사 하이닉스반도체 | 상변환 메모리 장치의 내부전압 생성회로 및 생성방법 |
US20110044121A1 (en) * | 2009-08-20 | 2011-02-24 | Kim Joung-Yeal | Semiconductor memory device having device for controlling bit line loading and improving sensing efficiency of bit line sense amplifier |
KR20110054773A (ko) * | 2009-11-18 | 2011-05-25 | 삼성전자주식회사 | 비트라인 디스털번스를 개선하는 반도체 메모리 장치 |
KR101036926B1 (ko) * | 2009-12-30 | 2011-05-25 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
US8351272B2 (en) * | 2010-07-02 | 2013-01-08 | Micron Technology, Inc. | Apparatuses and methods to reduce power consumption in digital circuits |
KR20130038030A (ko) * | 2011-10-07 | 2013-04-17 | 삼성전자주식회사 | 반도체 메모리 장치 |
KR20130082004A (ko) * | 2012-01-10 | 2013-07-18 | 에스케이하이닉스 주식회사 | 반도체메모리장치 |
US9087559B2 (en) * | 2012-12-27 | 2015-07-21 | Intel Corporation | Memory sense amplifier voltage modulation |
US9147465B2 (en) | 2013-01-17 | 2015-09-29 | Samsung Electronics Co., Ltd. | Circuit for controlling sense amplifier source node in semiconductor memory device and controlling method thereof |
JP2014149884A (ja) * | 2013-01-31 | 2014-08-21 | Micron Technology Inc | 半導体装置 |
KR102126436B1 (ko) | 2013-12-20 | 2020-06-24 | 삼성전자주식회사 | 저장 장치 및 그것의 래치 관리 방법 |
JP2015176617A (ja) * | 2014-03-14 | 2015-10-05 | マイクロン テクノロジー, インク. | 半導体装置 |
US9431398B2 (en) | 2014-04-28 | 2016-08-30 | Infineon Technologies Ag | Semiconductor chip having a circuit with cross-coupled transistors to thwart reverse engineering |
US9564441B2 (en) * | 2014-09-25 | 2017-02-07 | Kilopass Technology, Inc. | Two-transistor SRAM semiconductor structure and methods of fabrication |
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CN107452418A (zh) * | 2016-06-01 | 2017-12-08 | 华邦电子股份有限公司 | 半导体存储器装置 |
US9978435B1 (en) * | 2017-01-25 | 2018-05-22 | Winbond Electronics Corporation | Memory device and operation methods thereof |
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US10566036B2 (en) * | 2018-06-15 | 2020-02-18 | Micron Technology, Inc. | Apparatuses and method for reducing sense amplifier leakage current during active power-down |
DE102019123555B4 (de) | 2019-09-03 | 2022-12-01 | Infineon Technologies Ag | Physisch obfuskierter schaltkreis |
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JP4032039B2 (ja) * | 2004-04-06 | 2008-01-16 | 株式会社東芝 | 半導体記憶装置 |
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KR100702004B1 (ko) * | 2004-08-02 | 2007-03-30 | 삼성전자주식회사 | 반도체 메모리 장치 및 이 장치의 비트 라인 센싱 방법 |
KR100652414B1 (ko) * | 2005-06-10 | 2006-12-01 | 삼성전자주식회사 | 딥 파워 다운 모드일 때 일부 데이터를 보존할 수 있는메모리 장치 및 그 동작 방법 |
US7330388B1 (en) * | 2005-09-23 | 2008-02-12 | Cypress Semiconductor Corporation | Sense amplifier circuit and method of operation |
US7375999B2 (en) * | 2005-09-29 | 2008-05-20 | Infineon Technologies Ag | Low equalized sense-amp for twin cell DRAMs |
US7408813B2 (en) * | 2006-08-03 | 2008-08-05 | Micron Technology, Inc. | Block erase for volatile memory |
JP2008146727A (ja) * | 2006-12-07 | 2008-06-26 | Elpida Memory Inc | 半導体記憶装置及びその制御方法 |
JP4498374B2 (ja) * | 2007-03-22 | 2010-07-07 | 株式会社東芝 | 半導体記憶装置 |
-
2006
- 2006-09-21 TW TW095134955A patent/TW200721163A/zh unknown
- 2006-09-22 WO PCT/US2006/037285 patent/WO2007038448A2/en active Application Filing
- 2006-09-22 KR KR1020087006507A patent/KR101350920B1/ko not_active IP Right Cessation
- 2006-09-22 CN CNA200680042999XA patent/CN101501778A/zh active Pending
- 2006-09-22 EP EP06825107A patent/EP1934981A4/en not_active Withdrawn
- 2006-09-22 JP JP2008532479A patent/JP2009512961A/ja active Pending
- 2006-09-22 US US11/534,609 patent/US7929367B2/en not_active Expired - Fee Related
-
2011
- 2011-04-19 US US13/089,486 patent/US20120201085A1/en not_active Abandoned
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI418987B (zh) * | 2008-06-30 | 2013-12-11 | Intel Corp | 藉由細微間隔之預充電管理使記憶體處理量增加之技術 |
TWI824233B (zh) * | 2020-02-12 | 2023-12-01 | 美商新思科技股份有限公司 | 具有漏電流中的統計變化之動態隨機存取記憶體通路電晶體的設計 |
Also Published As
Publication number | Publication date |
---|---|
US7929367B2 (en) | 2011-04-19 |
EP1934981A2 (en) | 2008-06-25 |
EP1934981A4 (en) | 2009-11-18 |
US20070081405A1 (en) | 2007-04-12 |
JP2009512961A (ja) | 2009-03-26 |
WO2007038448A2 (en) | 2007-04-05 |
CN101501778A (zh) | 2009-08-05 |
KR101350920B1 (ko) | 2014-01-15 |
WO2007038448A3 (en) | 2009-04-23 |
KR20080048485A (ko) | 2008-06-02 |
US20120201085A1 (en) | 2012-08-09 |
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