KR950034678A - 집적 회로내에 전도성 접속부 형성 방법 및, 그 회로내의 전도성 부재 - Google Patents

집적 회로내에 전도성 접속부 형성 방법 및, 그 회로내의 전도성 부재 Download PDF

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KR950034678A
KR950034678A KR1019950010894A KR19950010894A KR950034678A KR 950034678 A KR950034678 A KR 950034678A KR 1019950010894 A KR1019950010894 A KR 1019950010894A KR 19950010894 A KR19950010894 A KR 19950010894A KR 950034678 A KR950034678 A KR 950034678A
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silicon
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시. 태프트 로버트
디. 군더슨 크레이그
시타램 아칼구드
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빈세트 비. 인그라시아
모토로라 인코포레이티드
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Abstract

일 실시예에서, 아래에 놓이는 패턴 형성된 텅스텐 규화물층(32)으로부터 패턴형성된 실리콘 규화물 반사층(26)의 박리는 패턴 형성된 텅스텐 규화물 층(32)과 그 위에 패턴 형성된 실리콘 질화물 무반사층(26) 사이에서 얇은 실리콘 층(30)을 형성하는 단계에 의해 보호된다.

Description

집적 회로내의 전도성 접속부 형성 방법 및, 그 회로내의 전도성 부재
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제5도는 본 발명의 일 실시예에 따른 공정 단계의 단면도.

Claims (5)

  1. 집적회로내에 전도성 접속부를 형성하는 방법에 있어서, 반도체 기판을 제공하는 단계와, 상기 반도체 기판위에 유전체층을 형성하는 단계와, 상기 유전체층 위에 금속층을 형성하는 단계, 상기 금속층 위에 실리콘층을 형성하는 단계와, 상기 실리콘층 위에 무반사 층을 형성하는 단계와, 상기 무반사 층의 나머지 부분을 형성하기 위해 상기 무반사 층을 에칭하는 단계 및, 상기 전도성 접속부를 형성하기 위해 상기 금속층을 에칭하는 단계를 포함하되, 상기 무반사층의 나머지 부분이 상기 전도성 접속부 위에 놓이는 것을 특징으로 하는 집적 회로내에 전도성 접속부 형성방법.
  2. 집적회로내에 전도성 접속부를 형성하는 방법에 있어서, 반도체 기판을 제공하는 단계와, 상기 반도체 기판위에 유전체층을 형성하는 단계와, 상기 유전체 층 위에 금속 규화물층을 형성하는 단계와, 상기 금속 규화물 층 위에 실리콘 층을 형성하는 단계와, 상기 실리콘 층위에 실리콘 및 질소를 함유하는 질화물층을 형성하는 단계와, 상기 질화물층의 나머지 부분을 형성하기 위해 상기 질화물층을 에칭하는 단계 및, 상기 전도성 접속부를 형성하기 위해 상기 금속 질화물층을 에칭하는 단계를 포함하되, 상기 질화물층의 나머지 부분이 상기 전도성 접속부 위에 놓이는 것을 특징으로 하는 집적 회로내에 전도성 접속부 형성방법.
  3. 집적회로내에 전도성 접속부를 형성하는 방법에 있어서, 반도체 기판을 제공하는 단계와, 상기 반도체 기판위에 유전체층을 형성하는 단계와, 상기 유전체 층 위에 폴리실리콘 층을 형성하는 단계와, 상기 폴리실리콘 층 위에 텅스텐 규화물 층을 형성하는 단계와, 상기 텅스턴 규화물 층위에 비정실 실리콘 층을 형성하는 단계와, 상기 비정질 실리콘 층위에 실리콘 및 질소를 함유한 무반사층을 형성하는 단계와; 상기 무반사층의 나머지 부분을 형성하기 위해 상기 무반사 층을 에칭하는 단계 및, 상기 전도성 접속부를 형성하기 위해 상기 폴리실리콘층을 에칭하는 단계를 포함하되, 상기 무반사층의 나머지 부분은 상기 전도성 접속부 위에 놓이는 것을 특징으로 하는 집적 회로내에 전도성 접속부 형성방법.
  4. 집적 회로내의 전도성 부재에 있어서, 패턴 형성된 금속층과, 상기 패턴 형성된 금속층 위에 놓이면서 접촉되는 패턴 형성된 실리콘층 및, 상기 패턴 형성된 실리콘 층위에 놓이면서 접촉되는 패턴 형성된 무반사층을 포함하는 것을 특징으로 하는 집적 회로내의 전도성 부재.
  5. 집적 회로내의 전도성 부재에 있어서, 패턴형성된 폴리실리콘 층과, 상기 패턴 형성된 폴리실리콘 층 위에 놓이면서 접촉되는 패턴 형성된 금속 규화물층과, 상기 패턴 형성된 금속 규화물층 위에 놓이면서 접촉되는 패턴형성된 실리콘 층 및, 상기 패턴형성된 실리콘 층위에 놓이면서 접촉되는 실리콘 및 질소를 함유한 패턴형성된 질화물 층을 포함하는 것을 특징으로 하는 집적 회로내의 전도성 부재.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950010894A 1994-05-02 1995-04-29 집적회로내의전도성상호접속구조및전도성상호접속형성방법 KR100376628B1 (ko)

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US08/236,076 US5441914A (en) 1994-05-02 1994-05-02 Method of forming conductive interconnect structure
US236076 1994-05-02

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