KR920022372A - 게이트와 드레인이 중첩된 모오스 트랜지스터의 제조방법 및 그 구조 - Google Patents

게이트와 드레인이 중첩된 모오스 트랜지스터의 제조방법 및 그 구조 Download PDF

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KR920022372A
KR920022372A KR1019910008363A KR910008363A KR920022372A KR 920022372 A KR920022372 A KR 920022372A KR 1019910008363 A KR1019910008363 A KR 1019910008363A KR 910008363 A KR910008363 A KR 910008363A KR 920022372 A KR920022372 A KR 920022372A
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layer
gate
insulating film
conductive layer
mos transistor
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KR940005293B1 (ko
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최영석
유광동
원태영
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김광호
삼성전자 주식회사
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Priority to US07/726,189 priority patent/US5256586A/en
Priority to FR9109790A priority patent/FR2676864B1/fr
Priority to JP3216481A priority patent/JP2662325B2/ja
Priority to GB9117932A priority patent/GB2256088B/en
Priority to DE4127967A priority patent/DE4127967C2/de
Publication of KR920022372A publication Critical patent/KR920022372A/ko
Priority to US08/119,671 priority patent/US5621236A/en
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Publication of KR940005293B1 publication Critical patent/KR940005293B1/ko

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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode
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    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L29/42312—Gate electrodes for field effect devices
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    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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Abstract

내용 없음.

Description

게이트와 드레인이 중첩된 모오스 트랜지스터의 제조방법 및 그 구조
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 단면 구조도,
제3도는 본 발명에 따른 제조공정도.

Claims (15)

  1. 게이트와 드레인이 중첩된 모오스 트랜지스터에 있어서 제1도전형의 반도체 기판과, 상기 기판내의 채널영역에 의해 서로 소정거리 이격되어 그 각각이 제1및 제2농도를 가지는 제2도전형의 확산영역과, 상기 채널 영역 상면의 제1게이트 절연막을 중간층르로 하는 제1패턴의 제1도전층과, 상기 제1도전층의 측면의 상부에 접촉되면서 상기 채널 영역에 인접하는 확산영역 상면의 제2게이트 절연막을 중간층으로 하는 제2패턴의 제2도전층으로 이루어지는 게이트를 구비함을 특징으로 하는 게이트와 드레인이 중첩된 모오스 트랜지스터.
  2. 제1항에 있어서, 상기 제2게이트 절연막이 상기 제1게이트 절연막보다 더 두꺼움을 특징으로 하는 게이트와 드레인이 중첩된 모오스 트랜지스터.
  3. 제2항에 있어서, 상기 제2도전층이 상기 제1도전층의 측면의 하부와 소정 두께의 절연막에 의해 이격됨을 특징으로 하는 게이트와 드레인이 중첩된 모오스 트랜지스터.
  4. 제1항에 있어서, 상기 제1도전층이 다결정 실리콘층으로 된 단일층이거나 다결정 실리콘층과 내화성 금속의 실리사이드층이 적층된 복합층임을 특징으로 하는 게이트와 드레인이 중첩된 모오스 트랜지스터.
  5. 제1항에 있어서, 상기 제2도전층이 다결정 실리콘층임을 특징으로 하는 게이트와 드레인이 중첩된 모오스 트랜지스터.
  6. 제1항에 있어서, 상기 제1및 제2게이트 절연막이 산화막임을 특징으로 하는 게이트와 드레인이 중첩된 모오스 트랜지스터.
  7. 제1도전형의 반도체 기판과, 상기 기판내의 채널영역에 의해 소정거리 이격되는 제2도전형의 제1확산영역과, 상기 채널영역 상면에 형성된 제1게이트 절연막을 중간층으로 하는 제1패턴의 도전층을 구비하는, 게이트와 드레인이 중첩된 모오스 트랜지스터의 제조방법에 있어서, 상기 기판 상면에 제1절연막을 형성한 후 상기 제1절 연막 상면에 포토레지스트를 도포하는 제1공정과 에치백 공정을 실시하여 상기 제1패턴의 도전층 상면 및 그 측면 상부의 상기 제1절연막을 제거하는 제2공정과, 상기 기판상면에 도전층과 제2절연막을 순차적으로 형성하는 제3공정과, 상기 제1패턴의 도전층 상면이 노출될때까지 에치백 공정을 실시하여 상기 도전층의 측면에 제2절연막 스페이서를 형성함과 동시에 상기 제2절연막 스페이서 하면을 제외한 영역의 상기 도전층을 제거하여 제2게이트 절연막을 중간층으로 하는 제2패턴의 도전층을 형성함에 의해 게이트를 완성하는 제4공정을 구비함을 특징으로 하는 게이트와 드레인이 중첩된 모오스 트랜지스터의 제조방법.
  8. 제7항에 있어서, 상기 제2게이트 절연막이 상기 제1게이트 절연막과 제1절연막의 적층에 의해 형성됨을 특징으로 하는 게이트와 드레인이 중첩된 모오스 트랜지스터의 제조방법.
  9. 제8항에 있어서, 상기 제2게이트 절연막이 220Å∼300Å의 두께를 가짐을 특징으로 하는 게이트와 드레인이 중첩된 모오스 트랜지스터의 제조방법.
  10. 제7항에 있어서, 상기 제1절연막이 산화막임을 특징으로 하는 게이트와 드레인이 중첩된 모오스 트랜지스터의 제조방법.
  11. 제7항에 있어서, 상기 제2공정이 상기 포토레지스터를 소정 두께 에치백하는 1단계와, 상기 제1단계에 의해 노출된 패드 산화막을 제거하는 제2단계와, 잔류된 상기 포토레지스터를 제거하는 제3단계로 이루어짐을 특징으로 하는 게이트와 드레인이 중첩된 모오스 트랜지스터의 제조방법.
  12. 제7항에 있어서, 상기 제2공정의 에치백 공정이 상기 포토레지스트의 식각륙보다 상기 제1절연막의 식각률이 더 빠른 공정조건에서 실시됨을 특징으로 하는 게이트와 드레인이 중첩된 모오스 트랜지스터의 제조방법.
  13. 제7항에 있어서, 상기 제3공정에서 형성된 도전층이 다결정 실리콘층임을 특징으로 하는 게이트와 드레인이 중첩된 모오스 트랜지스터의 제조방법.
  14. 제7항에 있어서, 상기 제2절연막이 산화막임을 특징으로 하는 게이트와 드레인이 중첩된 모오스 트랜지스터의 제조방법.
  15. 제7항에 있어서, 상기 제1패턴의 도전층이 다결정 실리콘층만으로 된 단일층이거나 다결정 실리콘 층과 내화성 금속의 실리사이드층이 적층된 복합층임을 특징으로 하는 게이트와 드레인이 중첩된 모오스 트랜지스터의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910008363A 1991-05-23 1991-05-23 게이트와 드레인이 중첩된 모오스 트랜지스터의 제조방법 및 그 구조 KR940005293B1 (ko)

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Application Number Priority Date Filing Date Title
KR1019910008363A KR940005293B1 (ko) 1991-05-23 1991-05-23 게이트와 드레인이 중첩된 모오스 트랜지스터의 제조방법 및 그 구조
US07/726,189 US5256586A (en) 1991-05-23 1991-07-05 Gate-to-drain overlapped MOS transistor fabrication process
FR9109790A FR2676864B1 (fr) 1991-05-23 1991-08-01 Procede de fabrication de transistor mos a recouvrement grille-drain et structure correspondante.
JP3216481A JP2662325B2 (ja) 1991-05-23 1991-08-02 電界効果型半導体素子の構造およびその製造方法
GB9117932A GB2256088B (en) 1991-05-23 1991-08-20 A gate-to-drain overlapped mos transistor fabrication process and structure thereof
DE4127967A DE4127967C2 (de) 1991-05-23 1991-08-23 MOS-Transistor mit Gate-Drain-Elektrodenüberlapp und Verfahren zu seiner Herstellung
US08/119,671 US5621236A (en) 1991-05-23 1993-09-03 Gate-to-drain overlapped MOS transistor fabrication process and structure thereby

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KR1019910008363A KR940005293B1 (ko) 1991-05-23 1991-05-23 게이트와 드레인이 중첩된 모오스 트랜지스터의 제조방법 및 그 구조

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KR940005293B1 KR940005293B1 (ko) 1994-06-15

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TW203148B (ko) * 1991-03-27 1993-04-01 American Telephone & Telegraph
US5401994A (en) * 1991-05-21 1995-03-28 Sharp Kabushiki Kaisha Semiconductor device with a non-uniformly doped channel
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DE4127967A1 (de) 1992-11-26
GB2256088B (en) 1995-10-18
DE4127967C2 (de) 1998-07-02
US5621236A (en) 1997-04-15
GB2256088A (en) 1992-11-25
FR2676864A1 (fr) 1992-11-27
KR940005293B1 (ko) 1994-06-15
US5256586A (en) 1993-10-26
JP2662325B2 (ja) 1997-10-08
FR2676864B1 (fr) 1998-08-14
JPH04346440A (ja) 1992-12-02
GB9117932D0 (en) 1991-10-09

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