KR920017268A - 반도체 트랜지스터의 제조방법 및 그 구조 - Google Patents

반도체 트랜지스터의 제조방법 및 그 구조 Download PDF

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KR920017268A
KR920017268A KR1019910003186A KR910003186A KR920017268A KR 920017268 A KR920017268 A KR 920017268A KR 1019910003186 A KR1019910003186 A KR 1019910003186A KR 910003186 A KR910003186 A KR 910003186A KR 920017268 A KR920017268 A KR 920017268A
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transistor
concentration
diffusion region
insulating film
conductivity type
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KR930010124B1 (ko
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장영태
강래구
노병혁
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김광호
삼성전자 주식회사
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Priority to US07/684,795 priority patent/US5278441A/en
Priority to JP3099917A priority patent/JP2961937B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90—MOSFET type gate sidewall insulating spacer

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

내용 없음

Description

반도체 트랜지스터의 제조방법 및 그 구조
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명에 따른 단면도, 제5도는 본 발명에 따른 제조 공정도, 제6도는 본 발명의 다른 실시예에 따른 단면도.

Claims (14)

  1. 제1 또는 제2도전형의 반도체 기판내에 제1 및 제2도전형의 제1 및 제2트랜지스터 영역을 구비하는 반도체 트랜지스터의 제조방법에 있어서, 상기 제1 및 제2트랜지스터 영역(64,66)상면에 게이트 절연막(72)을 중간층으로 하는 제1 및 제2게이트(74,76)를 형성한 후 서로 다른 사진 식각 공정에 의해 상기 각각의 트랜지스터 영역내에 제2 및 제1도전형의 불순물을 이온주입하여 제1 및 제2농도의 확산영역(80,81)(83,84)을 형성하는 제1공정과, 상기 게이트(74,76)의 양 측벽에 제1절연막 스페이서(86)를 형성하는 제2공정과, 상기 제1트랜지스터 영역(64)만 노출되도록 한후 제2도전형의 불순물을 이온 주입하여 제3농도의 확산영역(89,90)을 형성하는 제3공정과, 상기 제1절연막 스페이서(86)의 양 측면에 제2절연막 스페이서(94)를 형성하는 제4공정과, 상기 제2트랜지스터 영역(66)만 노출되도록 한 후 제1도전형의 불순물을 이온 주입하여 제4농도의 확산영역(98,99)을 형성하는 제5공정을 구비하여 상기 공정들이 순차적으로 이루어짐을 특징으로 하는 반도체 트랜지스터의 제조방법.
  2. 제1항에 있어서, 상기 제1 및 제2도전형이 각각 p형 및 n형임을 특징으로 하는 반도체 트랜지스터의 제조방법.
  3. 제2항에 있어서, 상기 제3 및 제4농도가 제1 및 제2농도보다 고농도임을 특징으로 하는 반도체 트랜지스터의 제조방법.
  4. 제3항에 있어서, 상기 제1트랜시스터의 제1 및 제2농도의 확산 영역 사이의 측면 간격이 상기 제1절연막 스페이서(86)의 폭에 의해 한정되고, 상기 제2트랜지스터의 제1 및 제2농도의 확산 영역 사이의 측면 간격이 상기 제1 및 제2절연막 스페이서(86,94)의 전체폭에 의해 한정됨을 특징으로 하는 반도체 트랜지스터의 제조방법.
  5. 제2항에 있어서, 상기 제3공정 후 상기 제2트랜지스터 영역(66)을 한정하여 제1도전형의 불순물을 상기 제1공정에서 보다 고농도이면서 제5공정에서 보다는 저농도로 이온 주입하는 공정을 더 구비하여 상기 제2트랜지스터가 트리플 구조의 확산영역을 가지도록 함을 특징으로 하는 반도체 트랜지스터의 제조방법.
  6. 제2항에 있어서, 상기 제2트랜지스터의 제3농도 확산영역을 형성하기 위한 이온 주입 공정이 상기 제1절연막 스페이서(86)를 형성한 후에 실시될 수도 있음을 특징으로 하는 반도체 트랜지스터의 제조방법.
  7. 제1항에 있어서, 상기 게이트 절연막(72)이 산화막임을 특징으로 하는 반도체 트랜지스터의 제조방법.
  8. 제1항에 있어서, 상기 제1 및 제2절연막 스페이서(86,94)가 소정 두께의 절연막을 상기 기판(62) 상면에 형성한 후 반응성 이온 식각을 실시함에 의해 형성됨을 특징으로 하는 반도체 트랜지스터의 제조방법.
  9. 제1항에 있어서, 상기 제1 및 제2절연막 스페이서(86,94)가 산화막 또는 질화막으로 형성됨을 특징으로 하는 반도체 트랜지스터의 제조방법.
  10. 제1항에 있어서, 상기 게이트(74,76)가 제1또는 제2도전형의 다결정 실리콘 또는 금속으로 형성될 수 있음을 특징으로 하는 반도체 트랜지스터의 제조방법.
  11. 제1도전형의 반도체 기판 또는 웰 내에 소정거리 이격되어 형성된 제2도전형의 확산영역과, 상기 확산 영역사이에 해당하는 영역상부에 형성된 게이트를 구비하는 제1트랜지스터와, 제2도전형의 웰 또는 반도체 기판내에서 소정거리 이격되어 형성된 제1도전형의 확산영역과, 상기 확산영역 사이에 해당하는 영역 상부에 형성된 게이트를 구비하는 제2트랜지스터를 구비하는 반도체 트랜지스터에 있어서, 상기 제1 및 제2트랜지스터가 각각의 게이트 측벽에 형성된 제1 및 제2절연막 스페이서를 구비하여 상기 제1트랜지스터의 확산영역이 상기 제1절연막 스페이서의 폭에 의해 측면 경계 사이의 거리가 한정되는 제1농도 및 제2농도의 확산 영역으로 이루어지고, 상기 제2트랜지스터의 확산 영역이 상기 제1 및 제2절연막 스페이서의 전체 폭에 의해 측면 경계 사이의 거리가 한정되는 제3농도 및 제4농도의 확산 영역으로 이루어짐을 특징으로 하는 반도체 트랜지스터의 제조방법.
  12. 제10항에 있어서, 상기 제1도전형이 p형이고 제2도전형이 n형임을 특징으로 하는 반도체 트랜지스터의 제조방법.
  13. 제11항에 있어서, 상기 제1 및 제3농도가 상기 제2 및 제4농도보다 각각 저농도임을 특징으로 하는 반도체 트랜지스터의 제조방법.
  14. 제12항에 있어서, 상기 제2트랜지스터가 제3농도 및 제4농도의 확산 영역사이에 상기 제1절연막 스페이서의 두께에 의해 상기 제3농도의 확산 영역의 측면 경계와의 거리가 한정되고 상기 제3농도와 제4농도 사이의 농도를 가지는 확산 영역을 더 구비할 수 있음을 특징으로 하는 반도체 트랜지스터.
    ※참고사항:최초출원 내용에 의하여 공개되는 것임.
KR1019910003186A 1991-02-27 1991-02-27 반도체 트랜지스터의 제조방법 및 그 구조 KR930010124B1 (ko)

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Application Number Priority Date Filing Date Title
KR1019910003186A KR930010124B1 (ko) 1991-02-27 1991-02-27 반도체 트랜지스터의 제조방법 및 그 구조
US07/684,795 US5278441A (en) 1991-02-27 1991-04-15 Method for fabricating a semiconductor transistor and structure thereof
JP3099917A JP2961937B2 (ja) 1991-02-27 1991-05-01 半導体トランジスタの製造方法およびその構造

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KR1019910003186A KR930010124B1 (ko) 1991-02-27 1991-02-27 반도체 트랜지스터의 제조방법 및 그 구조

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KR930010124B1 KR930010124B1 (ko) 1993-10-14

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