KR101120122B1 - 제 2 기판을 포함하며 상부면 및 하부면에서 노출된 기판표면들을 갖는 반도체 패키지 - Google Patents

제 2 기판을 포함하며 상부면 및 하부면에서 노출된 기판표면들을 갖는 반도체 패키지 Download PDF

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KR101120122B1
KR101120122B1 KR1020077027669A KR20077027669A KR101120122B1 KR 101120122 B1 KR101120122 B1 KR 101120122B1 KR 1020077027669 A KR1020077027669 A KR 1020077027669A KR 20077027669 A KR20077027669 A KR 20077027669A KR 101120122 B1 KR101120122 B1 KR 101120122B1
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substrate
package
die
assembly
land
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KR20080073637A (ko
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마르코스 카르네조스
플린 카슨
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스태츠 칩팩, 엘티디.
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Combinations Of Printed Boards (AREA)
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US69284205P 2005-06-20 2005-06-20
US60/692,842 2005-06-20
US11/394,635 US7429786B2 (en) 2005-04-29 2006-03-31 Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides
US11/394,635 2006-03-31
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US20060244117A1 (en) 2006-11-02
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JP2008539599A (ja) 2008-11-13
WO2006118982A2 (en) 2006-11-09
TWI322489B (en) 2010-03-21
US7429786B2 (en) 2008-09-30
JP4503677B2 (ja) 2010-07-14

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