WO2006118982A2 - Semiconductor substrate with exposed upper and lower sides - Google Patents

Semiconductor substrate with exposed upper and lower sides Download PDF

Info

Publication number
WO2006118982A2
WO2006118982A2 PCT/US2006/016143 US2006016143W WO2006118982A2 WO 2006118982 A2 WO2006118982 A2 WO 2006118982A2 US 2006016143 W US2006016143 W US 2006016143W WO 2006118982 A2 WO2006118982 A2 WO 2006118982A2
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
package
assembly
die
interconnection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2006/016143
Other languages
English (en)
French (fr)
Other versions
WO2006118982A3 (en
Inventor
Marcos Karnezos
Flynn Carson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Stats Chippac Pte Ltd
Original Assignee
Stats Chippac Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Pte Ltd filed Critical Stats Chippac Pte Ltd
Priority to KR1020077027669A priority Critical patent/KR101120122B1/ko
Priority to JP2008509150A priority patent/JP4503677B2/ja
Publication of WO2006118982A2 publication Critical patent/WO2006118982A2/en
Publication of WO2006118982A3 publication Critical patent/WO2006118982A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0652—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0652—Bump or bump-like direct electrical connections from substrate to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06551—Conductive connections on the side of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06596—Structural arrangements for testing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • the type of z-interconnect employed in the PoP module requires that the top and bottom package substrates be designed with matching pads for the z-interconnect balls. If one of the packages is exchanged for one in which the substrate has a different pad arrangement (different size or different design), then the substrate for the other package must be reconfigured accordingly. This leads to increased cost for manufacture of the multi-package module.
  • the distance between the top and bottom packages must be at least as great as the encapsulation height of the bottom package, which may be 0.25 mm or more, and typically is in a range between 0.5 mm and 1.5 mm, depending upon the number of die and depending upon whether the die-to-substrate electrical connection is by flip chip or by wire bonds.
  • the method further includes affixing and electrically connecting an additional component at the exposed land side of the second substrate.
  • An additional component or components can be mounted upon the assembly as a further step in the manufacture of the stacked package assembly; or, an additional component or components
  • the invention provides for excellent manufacturability, high design flexibility, and low cost to produce a stacked package module having a low profile and a small footprint.
  • FIG. 12 is a diagrammatic sketch in a sectional view thru a semiconductor assembly 5 according to an embodiment of the invention, including a flip chip die stacked over the assembly.
  • FIG. 1 there is shown in a diagrammatic sectional view generally at 1 an embodiment of a semiconductor package assembly, including a first ("bottom” in FIG. 1) package subassembly and a second ("top” in FIG. 1) substrate stacked over the first package subassembly, in which the package and the second substrate are interconnected by wire
  • the z-interconnection of the second ("top") substrate 10 and first ("bottom") package subassembly 100 is made by way of wire bonds 118 connecting traces on the downward facing metal layer (the metal layer 21) of the top substrate with traces on the lower metal layer 123 of the bottom package substrate. At one end each wire bond 118 is electrically connected to downward facing surfaces of pads on the metal layer 21 of the top substrate 12, and at the other end each wire bond is connected to lower surfaces of pads on the lower metal layer 123 of the bottom package substrate 112.
  • the wire bonds may be formed by any wire bonding technique, well known in the art, such as is described, for example, in U.S. 5,226,582, which is hereby incorporated by reference herein.
  • the substrate-to-package z-interconnect wire bonds are shown by way of example in FIG. 1 as having been made by forming a bead or bump on the surface of a pad on the lower metal layer of the top substrate, and then drawing the wire toward, and fusing it onto, a pad on the lower metal layer of the bottom substrate.
  • the wire bonds can be made in the inverse direction, that is, by forming a bead or bump on the lower surface of a pad on the lower metal layer of the bottom substrate, and then drawing the wire toward, and fusing it onto, a pad on the metal layer of the top substrate.
  • the top substrate is larger than the footprint of the first package subassembly over which it is mounted, leaving an area at the periphery of the first side of the top substrate on which the bond pads are exposed for the wire bonds 118.
  • the top substrate is punch- or saw-singulated.
  • the first package subassembly may have flip chip, rather than wire bonding, interconnection of the die to the first package substrate.
  • the support for the second substrate can be a spacer mounted upon the first package subassembly die.
  • the ball pads 53 are additionally available as test probe sites for testing the package prior to assembly, or for testing the package assembly, if desired, prior to mounting the second level interconnect solder balls.
  • the encapsulated marginal area has a width (MW in FIG. 5A) determined by the sum of the lengths of the bond fingers, the length of the trace to the bond finger, and the width of the saw street. Additionally, some mold flash may appear on the substrate surface at the inner edge of the margin (at the broken line 58 in FIG. 5A). Where the substrate is provided as one in a strip or array, some substrate material at the edge is lost to the saw width during saw singulation of the first package.
  • the bond finger length is about 250 um
  • the finger trace length is about 50 um
  • an allowance for mold resin bleed can be about 500 um.
  • the first die 1_14 is affixed, active side upward, onto the die attach side of the substrate.
  • the die has four edges defining a square.
  • Wire bond pads 51 are arranged in rows near the four edges of the die.
  • As on the land side of the substrate, most of the surface of the die attach side is covered by a solder mask, except where sites on the metal layer are revealed by openings in the solder mask, including particularly rows (one row along each edge of the die, in this example) of bond fingers (e.g., 54).
  • Wires 116 connect the die pads 51 with the bond fingers 54.
  • the I5 land side of the first package substrate, and the package die are interconnected as appropriate by way of the traces, wires, and vias to the pads on the land sides of the first package substrate, where interconnection of the package assembly is made to an underlying substrate (second level interconnection) or to additional devices stacked over the assembly.
  • the die in the first package subassembly are interconnected as desired to exposed pads on the land sides of the first package substrate and the second substrate at the top and bottom of the completed assembly.
  • the second substrate necessarily has a larger footprint than the first package substrate, to accommodate the z-interconnection between the substrates.
  • z-interconnects are arranged along all four edges of the packages and, accordingly, the second package is both wider and longer than the first package.
  • a ball grid array (BGA) package can be mounted over a package assembly constructed as described above with reference to FIG. 3.
  • BGA ball grid array
  • FIG. 7A 1 a BGA package 710 having interconnect solder balls 718 is aligned with and mounted upon the land side of a second substrate 10, and the solder balls are reflowed onto ball pads in the metal layer 23 to form a module 70.
  • the BGA footprint is smaller than that of the package assembly; in the module 72 shown in FIG.
  • the first package subassembly substrate (that is, the substrate in the assembly upon which the enclosed die is/are mounted, has a larger footprint than the second substrate (compare FIG. 24 with FIGs. 3 and 4).
  • a first package subassembly 242 includes die mounted upon (die 243) and stacked over (die 243'. 243") a first package subassembly substrate 241.
  • die 243 die mounted upon (die 243) and stacked over (die 243'. 243") a first package subassembly substrate 241.
  • FIG. 28 illustrates a package assembly in which the first subassembly constitutes a flip
  • FIG. 30 illustrates a package assembly generally similar to that shown in FIG. 29, in which the first package die is a flip chip die rather than a wire bonded die.
  • the first package subassembly 302 substrate 241 is constructed as in FIG. 24.
  • a first die 303 is mounted onto the die attach side of the substrate 241. Solder balls or bumps attached to pads on the die are electrically connected with pads on the metal layer at the die attach side of the substrate.
  • An underfill between the die and the substrate serves to protect the electrical interconnections and to provide structural and mechanical integrity and robustness to the interconnection.
  • Procedures in processes for making the various packages and for routing package substrates for use in the invention are well established in the industry.
  • the assembly process is similar for the configurations according to the various aspects of the invention. Generally, the process includes steps of: providing a ball grid array or land

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Combinations Of Printed Boards (AREA)
PCT/US2006/016143 2005-04-29 2006-04-27 Semiconductor substrate with exposed upper and lower sides Ceased WO2006118982A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020077027669A KR101120122B1 (ko) 2005-04-29 2006-04-27 제 2 기판을 포함하며 상부면 및 하부면에서 노출된 기판표면들을 갖는 반도체 패키지
JP2008509150A JP4503677B2 (ja) 2005-04-29 2006-04-27 上側および下側の基板表面を露出させた半導体パッケージ

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US59471105P 2005-04-29 2005-04-29
US60/594,711 2005-04-29
US69284205P 2005-06-20 2005-06-20
US60/692,842 2005-06-20
US11/394,635 US7429786B2 (en) 2005-04-29 2006-03-31 Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides
US11/394,635 2006-03-31

Publications (2)

Publication Number Publication Date
WO2006118982A2 true WO2006118982A2 (en) 2006-11-09
WO2006118982A3 WO2006118982A3 (en) 2007-07-12

Family

ID=37233660

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/016143 Ceased WO2006118982A2 (en) 2005-04-29 2006-04-27 Semiconductor substrate with exposed upper and lower sides

Country Status (5)

Country Link
US (1) US7429786B2 (enExample)
JP (1) JP4503677B2 (enExample)
KR (1) KR101120122B1 (enExample)
TW (1) TWI322489B (enExample)
WO (1) WO2006118982A2 (enExample)

Families Citing this family (114)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6930256B1 (en) 2002-05-01 2005-08-16 Amkor Technology, Inc. Integrated circuit substrate having laser-embedded conductive patterns and method therefor
US7548430B1 (en) 2002-05-01 2009-06-16 Amkor Technology, Inc. Buildup dielectric and metallization process and semiconductor package
US7633765B1 (en) 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
US9691635B1 (en) 2002-05-01 2017-06-27 Amkor Technology, Inc. Buildup dielectric layer having metallization pattern semiconductor package fabrication method
KR20050074961A (ko) * 2002-10-08 2005-07-19 치팩, 인코포레이티드 역전된 제 2 패키지를 구비한 반도체 적층형 멀티-패키지모듈
US11081370B2 (en) 2004-03-23 2021-08-03 Amkor Technology Singapore Holding Pte. Ltd. Methods of manufacturing an encapsulated semiconductor device
US10811277B2 (en) 2004-03-23 2020-10-20 Amkor Technology, Inc. Encapsulated semiconductor package
SG130055A1 (en) 2005-08-19 2007-03-20 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
SG130066A1 (en) 2005-08-26 2007-03-20 Micron Technology Inc Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
US8012867B2 (en) * 2006-01-31 2011-09-06 Stats Chippac Ltd Wafer level chip scale package system
US20070187818A1 (en) * 2006-02-15 2007-08-16 Texas Instruments Incorporated Package on package design a combination of laminate and tape substrate
US7986043B2 (en) * 2006-03-08 2011-07-26 Stats Chippac Ltd. Integrated circuit package on package system
US7981702B2 (en) 2006-03-08 2011-07-19 Stats Chippac Ltd. Integrated circuit package in package system
DE102006016345A1 (de) * 2006-04-05 2007-10-18 Infineon Technologies Ag Halbleitermodul mit diskreten Bauelementen und Verfahren zur Herstellung desselben
KR100885419B1 (ko) * 2006-04-26 2009-02-24 삼성전자주식회사 적층형 패키지 구조체
KR100792352B1 (ko) * 2006-07-06 2008-01-08 삼성전기주식회사 패키지 온 패키지의 바텀기판 및 그 제조방법
US20080029884A1 (en) * 2006-08-03 2008-02-07 Juergen Grafe Multichip device and method for producing a multichip device
US20080054496A1 (en) * 2006-08-30 2008-03-06 Neill Thornton High temperature operating package and circuit design
TWM308495U (en) * 2006-09-08 2007-03-21 Lingsen Precision Ind Ltd Microelectromechanical module package structure
US8154881B2 (en) * 2006-11-13 2012-04-10 Telecommunication Systems, Inc. Radiation-shielded semiconductor assembly
US7550857B1 (en) 2006-11-16 2009-06-23 Amkor Technology, Inc. Stacked redistribution layer (RDL) die assembly package
US7608921B2 (en) * 2006-12-07 2009-10-27 Stats Chippac, Inc. Multi-layer semiconductor package
US7566962B2 (en) * 2006-12-26 2009-07-28 Advanced Semiconductor Engineering Inc. Semiconductor package structure and method for manufacturing the same
TWI341576B (en) * 2007-01-24 2011-05-01 Chipmos Technologies Inc Chip package reducing wiring layers on substrate and its carrier
US8063481B2 (en) * 2007-02-21 2011-11-22 Rambus Inc. High-speed memory package
TWI335070B (en) * 2007-03-23 2010-12-21 Advanced Semiconductor Eng Semiconductor package and the method of making the same
US7777354B2 (en) * 2007-06-05 2010-08-17 Stats Chippac Ltd. Integrated circuit package system with leaded package
US9330945B2 (en) * 2007-09-18 2016-05-03 Stats Chippac Ltd. Integrated circuit package system with multi-chip module
US7888184B2 (en) * 2008-06-20 2011-02-15 Stats Chippac Ltd. Integrated circuit packaging system with embedded circuitry and post, and method of manufacture thereof
JP2010010437A (ja) * 2008-06-27 2010-01-14 Stanley Electric Co Ltd 光半導体装置
TWI473553B (zh) * 2008-07-03 2015-02-11 日月光半導體製造股份有限公司 晶片封裝結構
KR101297192B1 (ko) 2008-11-10 2013-08-19 삼성전자주식회사 화상형성장치, 칩, 및, 칩 패키지
US20100171206A1 (en) * 2009-01-07 2010-07-08 Chi-Chih Chu Package-on-Package Device, Semiconductor Package, and Method for Manufacturing The Same
US8012797B2 (en) * 2009-01-07 2011-09-06 Advanced Semiconductor Engineering, Inc. Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
TWI499024B (zh) * 2009-01-07 2015-09-01 日月光半導體製造股份有限公司 堆疊式多封裝構造裝置、半導體封裝構造及其製造方法
US20100244223A1 (en) * 2009-03-25 2010-09-30 Cho Namju Integrated circuit packaging system with an integral-interposer-structure and method of manufacture thereof
US8710634B2 (en) * 2009-03-25 2014-04-29 Stats Chippac Ltd. Integrated circuit packaging system with an integral-interposer-structure and method of manufacture thereof
US8003445B2 (en) * 2009-03-26 2011-08-23 Stats Chippac Ltd. Integrated circuit packaging system with z-interconnects having traces and method of manufacture thereof
US7960827B1 (en) 2009-04-09 2011-06-14 Amkor Technology, Inc. Thermal via heat spreader package and method
US8623753B1 (en) * 2009-05-28 2014-01-07 Amkor Technology, Inc. Stackable protruding via package and method
US8533853B2 (en) 2009-06-12 2013-09-10 Telecommunication Systems, Inc. Location sensitive solid state drive
US8222538B1 (en) 2009-06-12 2012-07-17 Amkor Technology, Inc. Stackable via package and method
US8106499B2 (en) * 2009-06-20 2012-01-31 Stats Chippac Ltd. Integrated circuit packaging system with a dual substrate package and method of manufacture thereof
US20100327419A1 (en) 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
US8471154B1 (en) 2009-08-06 2013-06-25 Amkor Technology, Inc. Stackable variable height via package and method
US8743561B2 (en) 2009-08-26 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level molded structure for package assembly
TWI469283B (zh) * 2009-08-31 2015-01-11 日月光半導體製造股份有限公司 封裝結構以及封裝製程
US8796561B1 (en) 2009-10-05 2014-08-05 Amkor Technology, Inc. Fan out build up substrate stackable package and method
EP2309535A1 (en) 2009-10-09 2011-04-13 Telefonaktiebolaget L M Ericsson (Publ) Chip package with a chip embedded in a wiring body
US8304921B2 (en) * 2009-11-13 2012-11-06 Stats Chippac Ltd. Integrated circuit packaging system with interconnect and method of manufacture thereof
US8198131B2 (en) * 2009-11-18 2012-06-12 Advanced Semiconductor Engineering, Inc. Stackable semiconductor device packages
JP2011128140A (ja) * 2009-11-19 2011-06-30 Dainippon Printing Co Ltd センサデバイス及びその製造方法
TWI411051B (zh) * 2009-12-02 2013-10-01 晨星半導體股份有限公司 封裝層疊方法與結構及其電路板系統
US8937381B1 (en) 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US9691734B1 (en) 2009-12-07 2017-06-27 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
TWI408785B (zh) 2009-12-31 2013-09-11 日月光半導體製造股份有限公司 半導體封裝結構
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8536462B1 (en) 2010-01-22 2013-09-17 Amkor Technology, Inc. Flex circuit package and method
TWI419283B (zh) * 2010-02-10 2013-12-11 日月光半導體製造股份有限公司 封裝結構
TWI411075B (zh) 2010-03-22 2013-10-01 日月光半導體製造股份有限公司 半導體封裝件及其製造方法
US8981577B2 (en) * 2010-03-24 2015-03-17 Stats Chippac Ltd. Integrated circuit packaging system with interconnect and method of manufacture thereof
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8300423B1 (en) 2010-05-25 2012-10-30 Amkor Technology, Inc. Stackable treated via package and method
US8294276B1 (en) 2010-05-27 2012-10-23 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US8338229B1 (en) 2010-07-30 2012-12-25 Amkor Technology, Inc. Stackable plasma cleaned via package and method
US8717775B1 (en) 2010-08-02 2014-05-06 Amkor Technology, Inc. Fingerprint sensor package and method
US9059187B2 (en) * 2010-09-30 2015-06-16 Ibiden Co., Ltd. Electronic component having encapsulated wiring board and method for manufacturing the same
US8337657B1 (en) 2010-10-27 2012-12-25 Amkor Technology, Inc. Mechanical tape separation package and method
TWI451546B (zh) * 2010-10-29 2014-09-01 日月光半導體製造股份有限公司 堆疊式封裝結構、其封裝結構及封裝結構之製造方法
TWI455265B (zh) * 2010-11-01 2014-10-01 矽品精密工業股份有限公司 具微機電元件之封裝結構及其製法
US8482134B1 (en) 2010-11-01 2013-07-09 Amkor Technology, Inc. Stackable package and method
US9748154B1 (en) 2010-11-04 2017-08-29 Amkor Technology, Inc. Wafer level fan out semiconductor device and manufacturing method thereof
US8525318B1 (en) 2010-11-10 2013-09-03 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US8557629B1 (en) 2010-12-03 2013-10-15 Amkor Technology, Inc. Semiconductor device having overlapped via apertures
US8535961B1 (en) 2010-12-09 2013-09-17 Amkor Technology, Inc. Light emitting diode (LED) package and method
TWI445155B (zh) 2011-01-06 2014-07-11 日月光半導體製造股份有限公司 堆疊式封裝結構及其製造方法
US8171800B1 (en) * 2011-01-25 2012-05-08 Continental Automotive Systems, Inc. Differential pressure sensor using dual backside absolute pressure sensing
KR101828386B1 (ko) * 2011-02-15 2018-02-13 삼성전자주식회사 스택 패키지 및 그의 제조 방법
US9721872B1 (en) 2011-02-18 2017-08-01 Amkor Technology, Inc. Methods and structures for increasing the allowable die size in TMV packages
US9171792B2 (en) 2011-02-28 2015-10-27 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having a side-by-side device arrangement and stacking functionality
US9013011B1 (en) 2011-03-11 2015-04-21 Amkor Technology, Inc. Stacked and staggered die MEMS package and method
KR101140113B1 (ko) 2011-04-26 2012-04-30 앰코 테크놀로지 코리아 주식회사 반도체 디바이스
US8765497B2 (en) * 2011-09-02 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging and function tests for package-on-package and system-in-package structures
US8653674B1 (en) 2011-09-15 2014-02-18 Amkor Technology, Inc. Electronic component package fabrication method and structure
US8633598B1 (en) 2011-09-20 2014-01-21 Amkor Technology, Inc. Underfill contacting stacking balls package fabrication method and structure
US9029962B1 (en) 2011-10-12 2015-05-12 Amkor Technology, Inc. Molded cavity substrate MEMS package fabrication method and structure
TWI449152B (zh) 2011-12-21 2014-08-11 財團法人工業技術研究院 半導體元件堆疊結構
KR20130105175A (ko) * 2012-03-16 2013-09-25 삼성전자주식회사 보호 층을 갖는 반도체 패키지 및 그 형성 방법
US9385006B2 (en) * 2012-06-21 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming an embedded SOP fan-out package
US9799592B2 (en) 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
KR101366461B1 (ko) 2012-11-20 2014-02-26 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US10115661B2 (en) * 2013-02-08 2018-10-30 Qualcomm Incorporated Substrate-less discrete coupled inductor structure
AT513747B1 (de) 2013-02-28 2014-07-15 Mikroelektronik Ges Mit Beschränkter Haftung Ab Bestückungsverfahren für Schaltungsträger und Schaltungsträger
CN104051411B (zh) 2013-03-15 2018-08-28 台湾积体电路制造股份有限公司 叠层封装结构
US9768048B2 (en) 2013-03-15 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package on-package structure
KR101488590B1 (ko) 2013-03-29 2015-01-30 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US20150014852A1 (en) * 2013-07-12 2015-01-15 Yueli Liu Package assembly configurations for multiple dies and associated techniques
US9478498B2 (en) * 2013-08-05 2016-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Through package via (TPV)
US9524948B2 (en) * 2013-09-30 2016-12-20 Mediatek Inc. Package structure
KR101607981B1 (ko) 2013-11-04 2016-03-31 앰코 테크놀로지 코리아 주식회사 반도체 패키지용 인터포저 및 이의 제조 방법, 제조된 인터포저를 이용한 반도체 패키지
KR102190390B1 (ko) 2013-11-07 2020-12-11 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
CN104760920B (zh) 2014-01-02 2017-01-04 意法半导体研发(深圳)有限公司 具有mems ic的紧凑电子封装体和相关方法
CN105097680B (zh) * 2014-05-16 2019-06-07 恩智浦美国有限公司 用于集成电路器件的保护性封装
JP6235423B2 (ja) * 2014-06-30 2017-11-22 東芝メモリ株式会社 半導体装置
US20170053858A1 (en) * 2015-08-20 2017-02-23 Intel Corporation Substrate on substrate package
US10229859B2 (en) 2016-08-17 2019-03-12 Advanced Semiconductor Engineering, Inc. Semiconductor device package and a method of manufacturing the same
US9960328B2 (en) 2016-09-06 2018-05-01 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US9859255B1 (en) * 2016-10-01 2018-01-02 Intel Corporation Electronic device package
KR102359904B1 (ko) 2019-09-16 2022-02-08 삼성전자주식회사 반도체 패키지
US20230065615A1 (en) * 2021-08-27 2023-03-02 Advanced Semiconductor Engineering, Inc. Electronic device
TWI808835B (zh) * 2022-07-20 2023-07-11 強茂股份有限公司 晶圓級晶片尺寸封裝件及方法
KR102855264B1 (ko) * 2022-11-22 2025-09-03 앱솔릭스 인코포레이티드 패키징 기판 및 이를 포함하는 반도체 패키지
TWI843347B (zh) * 2022-12-20 2024-05-21 矽品精密工業股份有限公司 電子封裝件及其製法

Family Cites Families (123)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8927164D0 (en) 1989-12-01 1990-01-31 Inmos Ltd Semiconductor chip packages
US5446620A (en) 1990-08-01 1995-08-29 Staktek Corporation Ultra high density integrated circuit packages
FR2670322B1 (fr) 1990-12-05 1997-07-04 Matra Espace Modules de memoire a l'etat solide et dispositifs de memoire comportant de tels modules
JPH05152505A (ja) 1991-11-25 1993-06-18 Fujitsu Ltd 電子回路実装基板
US5222014A (en) 1992-03-02 1993-06-22 Motorola, Inc. Three-dimensional multi-chip pad array carrier
US5422435A (en) 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
FR2694840B1 (fr) 1992-08-13 1994-09-09 Commissariat Energie Atomique Module multi-puces à trois dimensions.
US5340771A (en) 1993-03-18 1994-08-23 Lsi Logic Corporation Techniques for providing high I/O count connections to semiconductor dies
JP2531928B2 (ja) 1993-11-05 1996-09-04 株式会社東芝 半導体スタック
US5444296A (en) 1993-11-22 1995-08-22 Sun Microsystems, Inc. Ball grid array packages for high speed applications
US5436203A (en) 1994-07-05 1995-07-25 Motorola, Inc. Shielded liquid encapsulated semiconductor device and method for making the same
MY112145A (en) 1994-07-11 2001-04-30 Ibm Direct attachment of heat sink attached directly to flip chip using flexible epoxy
US5652185A (en) 1995-04-07 1997-07-29 National Semiconductor Corporation Maximized substrate design for grid array based assemblies
US5998864A (en) 1995-05-26 1999-12-07 Formfactor, Inc. Stacking semiconductor devices, particularly memory chips
US5719440A (en) 1995-12-19 1998-02-17 Micron Technology, Inc. Flip chip adaptor package for bare die
US7166495B2 (en) 1996-02-20 2007-01-23 Micron Technology, Inc. Method of fabricating a multi-die semiconductor package assembly
US5952725A (en) * 1996-02-20 1999-09-14 Micron Technology, Inc. Stacked semiconductor devices
US6075289A (en) 1996-10-24 2000-06-13 Tessera, Inc. Thermally enhanced packaged semiconductor assemblies
US5994166A (en) 1997-03-10 1999-11-30 Micron Technology, Inc. Method of constructing stacked packages
US5898219A (en) 1997-04-02 1999-04-27 Intel Corporation Custom corner attach heat sink design for a plastic ball grid array integrated circuit package
JPH10294423A (ja) 1997-04-17 1998-11-04 Nec Corp 半導体装置
US5982633A (en) 1997-08-20 1999-11-09 Compaq Computer Corporation Opposed ball grid array mounting
JP3834426B2 (ja) 1997-09-02 2006-10-18 沖電気工業株式会社 半導体装置
CA2218307C (en) 1997-10-10 2006-01-03 Gennum Corporation Three dimensional packaging configuration for multi-chip module assembly
JP3644662B2 (ja) 1997-10-29 2005-05-11 株式会社ルネサステクノロジ 半導体モジュール
JPH11219984A (ja) 1997-11-06 1999-08-10 Sharp Corp 半導体装置パッケージおよびその製造方法ならびにそのための回路基板
US5899705A (en) 1997-11-20 1999-05-04 Akram; Salman Stacked leads-over chip multi-chip module
JP2000208698A (ja) 1999-01-18 2000-07-28 Toshiba Corp 半導体装置
TW432550B (en) * 1998-02-07 2001-05-01 Siliconware Precision Industries Co Ltd Method of encapsulating a chip
TW434756B (en) 1998-06-01 2001-05-16 Hitachi Ltd Semiconductor device and its manufacturing method
US6451624B1 (en) 1998-06-05 2002-09-17 Micron Technology, Inc. Stackable semiconductor package having conductive layer and insulating layers and method of fabrication
US6034875A (en) 1998-06-17 2000-03-07 International Business Machines Corporation Cooling structure for electronic components
US5977640A (en) 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
JP2000058691A (ja) 1998-08-07 2000-02-25 Sharp Corp ミリ波半導体装置
US6201302B1 (en) 1998-12-31 2001-03-13 Sampo Semiconductor Corporation Semiconductor package having multi-dies
JP2000228468A (ja) * 1999-02-05 2000-08-15 Mitsubishi Electric Corp 半導体チップ及び半導体装置
JP3685947B2 (ja) 1999-03-15 2005-08-24 新光電気工業株式会社 半導体装置及びその製造方法
US6118176A (en) 1999-04-26 2000-09-12 Advanced Semiconductor Engineering, Inc. Stacked chip assembly utilizing a lead frame
US6890798B2 (en) 1999-06-08 2005-05-10 Intel Corporation Stacked chip packaging
US6238949B1 (en) 1999-06-18 2001-05-29 National Semiconductor Corporation Method and apparatus for forming a plastic chip on chip package module
JP3526788B2 (ja) 1999-07-01 2004-05-17 沖電気工業株式会社 半導体装置の製造方法
SG87046A1 (en) 1999-08-17 2002-03-19 Micron Technology Inc Multi-chip module with stacked dice
US6424033B1 (en) 1999-08-31 2002-07-23 Micron Technology, Inc. Chip package with grease heat sink and method of making
WO2001018864A1 (en) 1999-09-03 2001-03-15 Seiko Epson Corporation Semiconductor device, method of manufacture thereof, circuit board, and electronic device
JP2001156212A (ja) 1999-09-16 2001-06-08 Nec Corp 樹脂封止型半導体装置及びその製造方法
JP2001094045A (ja) 1999-09-22 2001-04-06 Seiko Epson Corp 半導体装置
JP3485507B2 (ja) 1999-10-25 2004-01-13 沖電気工業株式会社 半導体装置
JP2001127246A (ja) 1999-10-29 2001-05-11 Fujitsu Ltd 半導体装置
US6376904B1 (en) 1999-12-23 2002-04-23 Rambus Inc. Redistributed bond pads in stacked integrated circuit die package
JP2001223326A (ja) 2000-02-09 2001-08-17 Hitachi Ltd 半導体装置
KR100335717B1 (ko) 2000-02-18 2002-05-08 윤종용 고용량 메모리 카드
US6462421B1 (en) 2000-04-10 2002-10-08 Advanced Semicondcutor Engineering, Inc. Multichip module
JP2001308262A (ja) 2000-04-26 2001-11-02 Mitsubishi Electric Corp 樹脂封止ｂｇａ型半導体装置
TW445610B (en) 2000-06-16 2001-07-11 Siliconware Precision Industries Co Ltd Stacked-die packaging structure
TW459361B (en) 2000-07-17 2001-10-11 Siliconware Precision Industries Co Ltd Three-dimensional multiple stacked-die packaging structure
US6472758B1 (en) 2000-07-20 2002-10-29 Amkor Technology, Inc. Semiconductor package including stacked semiconductor dies and bond wires
JP2002040095A (ja) 2000-07-26 2002-02-06 Nec Corp 半導体装置及びその実装方法
US6607937B1 (en) 2000-08-23 2003-08-19 Micron Technology, Inc. Stacked microelectronic dies and methods for stacking microelectronic dies
JP3377001B2 (ja) 2000-08-31 2003-02-17 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
JP4570809B2 (ja) 2000-09-04 2010-10-27 富士通セミコンダクター株式会社 積層型半導体装置及びその製造方法
US6492726B1 (en) 2000-09-22 2002-12-10 Chartered Semiconductor Manufacturing Ltd. Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection
JP2002118201A (ja) 2000-10-05 2002-04-19 Hitachi Ltd 半導体装置およびその製造方法
JP3913481B2 (ja) 2001-01-24 2007-05-09 シャープ株式会社 半導体装置および半導体装置の製造方法
TW459363B (en) 2000-11-22 2001-10-11 Kingpak Tech Inc Integrated circuit stacking structure and the manufacturing method thereof
JP3798620B2 (ja) 2000-12-04 2006-07-19 富士通株式会社 半導体装置の製造方法
US6340846B1 (en) 2000-12-06 2002-01-22 Amkor Technology, Inc. Making semiconductor packages with stacked dies and reinforced wire bonds
US6777819B2 (en) 2000-12-20 2004-08-17 Siliconware Precision Industries Co., Ltd. Semiconductor package with flash-proof device
US6734539B2 (en) 2000-12-27 2004-05-11 Lucent Technologies Inc. Stacked module package
JP2002208656A (ja) 2001-01-11 2002-07-26 Mitsubishi Electric Corp 半導体装置
US6388313B1 (en) 2001-01-30 2002-05-14 Siliconware Precision Industries Co., Ltd. Multi-chip module
JP2002231885A (ja) 2001-02-06 2002-08-16 Mitsubishi Electric Corp 半導体装置
JP4780844B2 (ja) 2001-03-05 2011-09-28 Ｏｋｉセミコンダクタ株式会社 半導体装置
TW502408B (en) 2001-03-09 2002-09-11 Advanced Semiconductor Eng Chip with chamfer
JP2002280516A (ja) 2001-03-19 2002-09-27 Toshiba Corp 半導体モジュール
SG108245A1 (en) 2001-03-30 2005-01-28 Micron Technology Inc Ball grid array interposer, packages and methods
US6627980B2 (en) 2001-04-12 2003-09-30 Formfactor, Inc. Stacked semiconductor device assembly with microelectronic spring contacts
US6400007B1 (en) 2001-04-16 2002-06-04 Kingpak Technology Inc. Stacked structure of semiconductor means and method for manufacturing the same
JP2002373969A (ja) 2001-06-15 2002-12-26 Oki Electric Ind Co Ltd 半導体装置及び半導体装置の製造方法
US6900528B2 (en) 2001-06-21 2005-05-31 Micron Technology, Inc. Stacked mass storage flash memory package
US6734552B2 (en) 2001-07-11 2004-05-11 Asat Limited Enhanced thermal dissipation integrated circuit package
US6451626B1 (en) 2001-07-27 2002-09-17 Charles W.C. Lin Three-dimensional stacked semiconductor package
KR100445073B1 (ko) 2001-08-21 2004-08-21 삼성전자주식회사 듀얼 다이 패키지
JP2003086733A (ja) 2001-09-11 2003-03-20 Matsushita Electric Ind Co Ltd 半導体装置とその製造方法およびそれを用いた電子機器
US6787916B2 (en) 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
US6847105B2 (en) 2001-09-21 2005-01-25 Micron Technology, Inc. Bumping technology in stacked die configurations
US6599779B2 (en) 2001-09-24 2003-07-29 St Assembly Test Service Ltd. PBGA substrate for anchoring heat sink
US6897565B2 (en) 2001-10-09 2005-05-24 Tessera, Inc. Stacked packages
US6555917B1 (en) 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
TW523887B (en) 2001-11-15 2003-03-11 Siliconware Precision Industries Co Ltd Semiconductor packaged device and its manufacturing method
US6737750B1 (en) 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US20030113952A1 (en) 2001-12-19 2003-06-19 Mahesh Sambasivam Underfill materials dispensed in a flip chip package by way of a through hole
TW523894B (en) 2001-12-24 2003-03-11 Siliconware Precision Industries Co Ltd Semiconductor device and its manufacturing method
US6891276B1 (en) 2002-01-09 2005-05-10 Bridge Semiconductor Corporation Semiconductor package device
US7034388B2 (en) 2002-01-25 2006-04-25 Advanced Semiconductor Engineering, Inc. Stack type flip-chip package
JP2003273317A (ja) 2002-03-19 2003-09-26 Nec Electronics Corp 半導体装置及びその製造方法
JP3688249B2 (ja) 2002-04-05 2005-08-24 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
JP3550391B2 (ja) 2002-05-15 2004-08-04 沖電気工業株式会社 半導体装置及びその製造方法
US7081578B2 (en) * 2002-05-17 2006-07-25 Crimson Technology, Inc. Musical performance information compression apparatus, and musical performance information decoding apparatus
US6906415B2 (en) 2002-06-27 2005-06-14 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor devices and methods
KR100442880B1 (ko) 2002-07-24 2004-08-02 삼성전자주식회사 적층형 반도체 모듈 및 그 제조방법
US7132311B2 (en) 2002-07-26 2006-11-07 Intel Corporation Encapsulation of a stack of semiconductor dice
US7064426B2 (en) 2002-09-17 2006-06-20 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages
US20040061213A1 (en) 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages
US6838761B2 (en) 2002-09-17 2005-01-04 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield
US6972481B2 (en) 2002-09-17 2005-12-06 Chippac, Inc. Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages
US7053476B2 (en) 2002-09-17 2006-05-30 Chippac, Inc. Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages
KR20050074961A (ko) 2002-10-08 2005-07-19 치팩, 인코포레이티드 역전된 제 2 패키지를 구비한 반도체 적층형 멀티-패키지모듈
US7034387B2 (en) 2003-04-04 2006-04-25 Chippac, Inc. Semiconductor multipackage module including processor and memory package assemblies
TW567601B (en) 2002-10-18 2003-12-21 Siliconware Precision Industries Co Ltd Module device of stacked semiconductor package and method for fabricating the same
SG114585A1 (en) 2002-11-22 2005-09-28 Micron Technology Inc Packaged microelectronic component assemblies
KR100621991B1 (ko) 2003-01-03 2006-09-13 삼성전자주식회사 칩 스케일 적층 패키지
US6861288B2 (en) 2003-01-23 2005-03-01 St Assembly Test Services, Ltd. Stacked semiconductor packages and method for the fabrication thereof
TW576549U (en) 2003-04-04 2004-02-11 Advanced Semiconductor Eng Multi-chip package combining wire-bonding and flip-chip configuration
TWI225292B (en) 2003-04-23 2004-12-11 Advanced Semiconductor Eng Multi-chips stacked package
US6818980B1 (en) 2003-05-07 2004-11-16 Asat Ltd. Stacked semiconductor package and method of manufacturing the same
TWI299551B (en) 2003-06-25 2008-08-01 Via Tech Inc Quad flat no-lead type chip carrier
US6930378B1 (en) 2003-11-10 2005-08-16 Amkor Technology, Inc. Stacked semiconductor die assembly having at least one support
KR100564585B1 (ko) * 2003-11-13 2006-03-28 삼성전자주식회사 이중 스택된 ｂｇａ 패키지 및 다중 스택된 ｂｇａ 패키지
US20060138631A1 (en) 2003-12-31 2006-06-29 Advanced Semiconductor Engineering, Inc. Multi-chip package structure
US20060043556A1 (en) 2004-08-25 2006-03-02 Chao-Yuan Su Stacked packaging methods and structures
US7271496B2 (en) 2005-02-04 2007-09-18 Stats Chippac Ltd. Integrated circuit package-in-package system
US7445962B2 (en) 2005-02-10 2008-11-04 Stats Chippac Ltd. Stacked integrated circuits package system with dense routability and high thermal conductivity
US7354800B2 (en) * 2005-04-29 2008-04-08 Stats Chippac Ltd. Method of fabricating a stacked integrated circuit package system

Also Published As

Publication number Publication date
US7429786B2 (en) 2008-09-30
TWI322489B (en) 2010-03-21
US20060244117A1 (en) 2006-11-02
KR20080073637A (ko) 2008-08-11
JP4503677B2 (ja) 2010-07-14
TW200711072A (en) 2007-03-16
WO2006118982A3 (en) 2007-07-12
JP2008539599A (ja) 2008-11-13
KR101120122B1 (ko) 2012-03-23

Similar Documents

Publication Publication Date Title
US7429786B2 (en) Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides
US7429787B2 (en) Semiconductor assembly including chip scale package and second substrate with exposed surfaces on upper and lower sides
US7394148B2 (en) Module having stacked chip scale semiconductor packages
US7372141B2 (en) Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides
US8970049B2 (en) Multiple chip package module having inverted package stacked over die
JP5005534B2 (ja) ダイと、ボールグリッドアレイパッケージを覆うように積層された反転ランドグリッドアレイパッケージとを含む半導体マルチパッケージモジュール
CN102569214B (zh) 三维系统级封装堆栈式封装结构
TWI469301B (zh) 堆疊封裝間具有線接點互連之半導體多重封裝模組
US20060043556A1 (en) Stacked packaging methods and structures
US20040145039A1 (en) Stacked semiconductor packages and method for the fabrication thereof
KR20050074961A (ko) 역전된 제 2 패키지를 구비한 반도체 적층형 멀티-패키지모듈
US20110180891A1 (en) Conductor package structure and method of the same
KR100632476B1 (ko) 멀티칩 패키지 및 이에 사용되는 반도체칩
KR20060112303A (ko) 칩 크기 축소에 대응할 수 있는 반도체 패키지 조립방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
ENP Entry into the national phase

Ref document number: 2008509150

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 1020077027669

Country of ref document: KR

NENP Non-entry into the national phase

Ref country code: RU

122 Ep: pct application non-entry in european phase

Ref document number: 06751711

Country of ref document: EP

Kind code of ref document: A2