TWI808835B - 晶圓級晶片尺寸封裝件及方法 - Google Patents

晶圓級晶片尺寸封裝件及方法 Download PDF

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TWI808835B
TWI808835B TW111127104A TW111127104A TWI808835B TW I808835 B TWI808835 B TW I808835B TW 111127104 A TW111127104 A TW 111127104A TW 111127104 A TW111127104 A TW 111127104A TW I808835 B TWI808835 B TW I808835B
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layer
metal layer
substrate
wafer
crystal grain
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TW202406083A (zh
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何中雄
李季學
許裕銘
王永輝
陳嘉韋
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強茂股份有限公司
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Abstract

本發明是一種晶圓級晶片尺寸封裝件及方法，該封裝件包含有：一晶粒、一介電層及一底部金屬層；其中，該晶粒具有一基底及一主動面，在該主動面上設置複數個焊墊，於各焊墊的表面具有一焊接層；該介電層覆蓋於該晶粒的四個側周面的上部，但未覆蓋各個側周面的下部；該底部金屬層形成在該基底的底面。該底部金屬層可對晶粒的底面提供保護作用，且晶粒產生的熱能也可透過該底部金屬層對外散熱，而該底部金屬層具有較佳的抗電磁干擾(EMI)效果，能降低外界雜訊對晶粒的干擾。

Description

晶圓級晶片尺寸封裝件及方法
本發明關於一種晶圓級封裝元件，尤指一種具有較佳散熱效果及抗電磁干擾的晶圓級晶片尺寸封裝件。
請參考圖6A~6F所示的現有晶圓級晶片尺寸封裝(WLCSP)元件的製造方法，在圖6A中，在一晶圓500的正面上係製作出複數個晶粒502(如虛線所示)，每一個晶粒502上設置有複數有導電凸塊504。沿著各晶粒502的周圍對晶圓500進行第一次切割以形成切割道506，該切割道506未完全貫穿晶圓500。
在圖6B中，將模塑料(molding compound)508填充在各個切割道506中，且該模塑料508圍繞各個晶粒502的導電凸塊504，且包覆各導電凸塊504的下半部。在模塑料508填充完成後，在晶圓500的正面貼附一支撐膜510。
在圖6C中，將已經貼附該支撐膜510的晶圓500翻轉，對晶圓500的背面進行研磨以降低晶圓500的厚度，並且直到露出填充在各切割道506中的模塑料50為止，如圖所示，研磨晶圓500所去除的研磨厚度為L。
在圖6D中，於研磨後的晶圓500背面貼附一背面保護層512，以保護各個晶粒502的背面。於貼附該背面保護層512後，將該支撐膜510移除。
在圖6E中，將該支撐膜510移除之後，沿著各晶粒502的周圍進行第二次切割，將模塑料508完全切穿而得到多個晶圓級晶片尺寸封裝元件600。請參考圖6F所示，根據上述製法得到的晶圓級晶片尺寸封裝元件600具有 六面式保護層，即晶粒502四個周面的模塑料508、晶粒502頂面的模塑料508、以及在晶粒502底面的背面保護層512。
雖然在晶粒502的六面均具有保護層，但因為該模塑料508或該背面保護層512是以絕緣材環氧樹脂(epoxy resin)形成，因此散熱效果不佳，晶粒502產生的熱能不容易向外散熱。
本發明主要提供一種晶圓級晶片尺寸封裝件，可具有較佳散熱效果及抗電磁干擾功效。
為達成前述目的，本發明之晶圓級晶片尺寸封裝件，包含有：一晶粒，具有一基底及一主動面，在該主動面上設置複數個焊墊，於各焊墊的表面具有一焊接層；一介電層，該介電層覆蓋於該晶粒的四個側周面的上部，而未覆蓋各個側周面的下部；該介電層另覆蓋於晶粒的該主動面，且該介電層的表面係與該焊墊的表面齊平；一底部金屬層，係形成在該基底的底面。
本發明之晶圓級晶片尺寸封裝方法，包含有：提供一基底，於該基底上形成有複數個晶粒，其中各該晶粒的一主動面上形成有複數個焊墊；於該基底的底面形成一底部金屬層；沿著各晶粒的周圍對該基底進行第一次切割以形成切割道，該切割道未完全貫穿該基底；填充介電材料層於各個切割道內部，並且使該介電材料層覆蓋各該晶粒的主動面而與該複數個銲墊的表面齊平； 沿著各晶粒周圍的切割道進行第二次切割，並且切穿該基底、該底部金屬層以得到分離的複數個晶圓級晶片尺寸封裝件，其中第二次切割時的切割寬度係小於該切割道的寬度，令各個晶圓級晶片尺寸封裝件的四側周面保留有該介電材料層，且各個晶圓級晶片尺寸封裝件的底面具有該底部金屬層。
本發明之晶圓級晶片尺寸封裝件具有一底部金屬層，可對晶粒的底面提供保護作用，且晶粒產生的熱能透過該底部金屬層向外散熱。再者，相較於樹脂等介電材料，底部金屬層可提供較佳的抗電磁干擾(EMI)效果，降低外界雜訊對晶粒的干擾。
10:基底
11:磊晶層
12:晶粒
13:焊墊
14:切割道
20:第一金屬層
21:鈦層
22:銅層
30:熱壓層
31:介電層
32:隔離層
33:離形膜層
40:第二金屬層
50:焊接層
60:接合層
70:底部金屬層
100:晶圓級晶片尺寸封裝件
200:支撐膜
h:厚度
d:深度
W:切割寬度
A,B:晶圓單元
500:晶圓
502:晶粒
504:導電凸塊
506:切割道
508:模塑料
510:支撐膜
512:背面保護層
600:晶圓級晶片尺寸封裝件
L:研磨厚度
圖1A~圖1J：本發明第一較佳實施例的製作流程示意圖。
圖2：本發明「晶圓級晶片尺寸封裝件」之立體剖面示意圖。
圖3：本發明「晶圓級晶片尺寸封裝件」另一實施例之剖面示意圖。
圖4A~圖4K：本發明第二較佳實施例的製作流程示意圖。
圖5A~圖5J：本發明第三較佳實施例的製作流程示意圖。
圖6A~圖6F：現有晶圓級晶片尺寸封裝(WLCSP)元件的製造方法流程圖。
關於本發明製法的第一實施例，請參考圖1A~1H所示，首先於圖1A中，係提供一基底10，該基底10的厚度為h，在該基底10上製作出有複數個晶粒12(active device die/chip，如虛線框所示)，其中，該基底10為一晶圓基底，其材質可為矽基底或其它半導體材料的基底，在其表面上形成有一磊晶層11，該晶粒12的元件區可製作在該磊晶層11中，其中，磊晶層11的表面作為晶粒12的一主動面(active surface)，在該主動面上形成有數個焊墊13。
如圖1B所示，在該基底10的背面上形成一第一金屬層20，在一實施例中，該第一金屬層20可以是單一材料的金屬層(例如銅層)或是一複合金屬層，該第一金屬層20可藉由沉積或電鍍的方式形成在該基底10背面。以複合金屬層為例，該複合金屬層包含依序形成在基底10背面上的鈦層21、形成在該鈦層21上的銅層22。
如圖1C所示，在該基底10的底面設置一支撐膜200，並且對該基底10進行第一次切割作業，切割技術可包含使用合適蝕刻劑的乾式蝕刻、濕式蝕刻、非等向性蝕刻或電漿蝕刻；或切割技術可包含雷射；或切割技術可包含機械製程，諸如利用刀具切割至所要深度。切割時係沿著各晶粒12的周圍進行切割但不完全切穿該基底10，所形成之切割道14的縱向深度d可小於該基底10的厚度h(d<h)。在其中一實施例中，第一次切割時產生的切割道14其寬度為W，例如40μm。
如圖1D、1E所示，在基底10的正面貼合一熱壓層30，該熱壓層30為複層結構，包含一介電層31及一隔離層32。在貼合時，將該介電層31朝向該基底10的正面，而該隔離層32係附著在該介電層31的另一表面，該介電層31的材質可採用聚丙烯(PP)、味之素累積膜(Ajinomoto build-up film，ABF)等，該隔離層32可為銅箔。
在該基底10的背面貼合一第二金屬層40，例如銅。根據產品的製作需求，該第二金屬層40的厚度大於前述該銅層22的厚度，例如該第二金屬層40的厚度為20~200μm。在圖1E之後所示的各圖，因為該第二金屬層40及該銅層22均為銅材料，故圖面上以單一第二金屬層40簡化表示。
如圖1F所示，在該基底10的正面及背面分別貼合該熱壓層30及該第二金屬層40之後，將該基底10置於具有合適壓力及溫度的壓合設備中，對基底10雙面進行加熱壓合，使該介電層31熱融後流動填充於各個切割道14內部 並且覆蓋在各個晶粒12的主動面上。在熱壓過程中，最上方的隔離層32可隔絕該介電層31避免該介電層31沾黏到壓合設備，並可限制該介電層31的溢流方向使其能夠流入各切割道14內部。
如圖1G所示，於熱壓完成後，移除在該基底10表面的隔離層32，例如透過濕式蝕刻製程將該隔離層32移除而露出每個晶粒12的焊墊13。去除該隔離層32之後，在晶粒12主動面上的該介電層31表面大致與焊墊13的表面齊平；且相鄰焊墊13之間以該介電層31絕緣隔離。
如圖1H所示，在每個焊墊13的表面再形成一焊接層50，在本實施例中，該焊接層50為一金屬保護膜，例如透過無電電鍍(E’less)、無電鍍鎳浸金(ENIG)等製法將該金屬保護膜製作於各個焊墊13的表面。在另一實施例中，該焊接層50為電連接在該焊墊13上的導電錫球，如圖3所示。
如圖1I、1J所示，在基底10的背面貼合另一支撐膜200並對基底10進行第二次切割作業，以得到多個單體的晶圓級晶片尺寸封裝件100。該第二次切割作業沿著該切割道14進行切割且完全切穿該基底10。第二次切割時的切割寬度係小於該切割道14的寬度W，例如使用寬度為20μm的刀具沿著該40μm的切割道14的中心切割，令每個晶圓級晶片尺寸封裝件100的四周均保留有將近10μm厚度的該介電層31，且該介電層31可完整保護晶粒中的磊晶層11。
如圖2所示，每個晶圓級尺寸封裝件100的結構包含有：一晶粒12，具有一基底10及一主動面，在該主動面上設置複數個焊墊13，於各焊墊13的表面上形成一焊接層50；一介電層31，係部分覆蓋該基底10的四個側周面及該主動面，其中，位在各個側周面的該介電層31覆蓋側周面的上部，該介電層31未覆蓋各個側周面的下部，且該介電層31的側面與未被覆蓋的基底10的側周面平齊；位在該主動面的介電層31的表面係與該焊墊13的表面齊平； 一底部金屬層70，係形成在該晶粒12的底面，且面積大小與該晶粒12的底面面積相等。
其中，該底部金屬層70可以是單一材料的金屬層；或在另一實施例中，該底部金屬層70為複合金屬層，例如依序形成在該基底10底面的鈦層21、銅層40。該底部金屬層70不僅作為承載晶粒12的底材，也對晶粒12的底面提供保護作用，且晶粒12工作時產生的熱能也更容易傳導至該底部金屬層70，透過該底部金屬層70對外散熱。再者，該底部金屬層70相較於樹脂等介電材料，可提供較佳的抗電磁干擾效果，降低外界雜訊對晶粒12的干擾。
關於本發明製法的第二實施例以圖4A~4K表示其製程，其中圖4A至4E所示的步驟與第一實施例中圖1A至1E的步驟相同，故不再贅述。當完成圖4E的步驟，將已經貼合該熱壓層30及該第二金屬層40的基底10稱為一晶圓單元A。
在圖4F中，本發明將兩片的該晶圓單元A以背對背的方式互相貼合，透過具有黏性的一接合層60雙面黏合各晶圓單元A的第二金屬層40，其中，該接合層60可為一熱解膠膜(thermal release film)。相對貼合兩片的該晶圓單元A後，進行如圖4G所示的熱壓合作業，使各片晶圓單元A的介電層31在熱融後流動填充於各個切割道14的內部且覆蓋在各個晶粒12的主動面上。在此實施例中，因為將兩片晶圓單元A先貼合後可提高整體厚度，因此在進行圖4G的壓合作業時，能減少晶圓單元A發生破裂的機會，提高產品的製作良率。
在圖4H中，於熱壓完成後，將原本貼合的兩片晶圓單元A分離並清除該接合層60。在圖4I中，針對各片晶圓單元A再移除其隔離層32，例如透過濕式蝕刻製程將該隔離層32移除並露出每個晶粒12的焊墊13，同樣的，於晶粒12主動面上的介電層31表面大致會與焊墊13的表面齊平。
在圖4J中，於每個晶片12的焊墊13表面形成一焊接層50，在本實施例中，該焊接層50為一金屬保護膜，例如透過無電電鍍(E’less)、無電鍍鎳浸金(ENIG)等製法將該焊接層50製作於各個焊墊13的表面；在其它實施例中，該焊接層50可以是如圖3所示的導電錫球。如圖4K所示，在基底10的背面貼合另一支撐膜並對基底10進行第二次切割作業，以得到多個晶圓級晶片尺寸封裝件100，該第二次切割作業沿著該切割道14的位置進行切割且完全切穿該基底10，第二次切割時所用的刀具寬度係小於該切割道14的寬度W，令每個晶圓級晶片尺寸封裝件100的四周均保留有該介電層31，該晶圓級晶片尺寸封裝件100的結構亦如同圖2或圖3所示。
關於本發明製法的第三實施例以圖5A~5J表示。於圖5A中，製備一基底10，該基底10的厚度為h，在該基底10上製作出有複數個晶粒(active device die/chip)12(如虛線框所示)，其中，於該基底10的表面上可先形成有一磊晶層11，該晶粒12製作在該磊晶層11上，在各個晶粒12的主動面上形成有數個焊墊13。
如圖5B所示，在該基底10的背面上形成一第一金屬層20，在一實施例中，該第一金屬層20是複合金屬層，包含依序重疊形成在基底10背面上的一鈦層21及一銅層22，其中，該第一金屬層20可藉由沉積或電鍍的方式形成在該基底10背面，且該第一金屬層20的厚度可根據需求製作出20~200μm的銅層22。
如圖5C所示，在該基底10的底面設置一支撐膜，並且對該基底10進行第一次切割作業，切割時係沿著各晶粒12的周圍進行切割但不完全切穿該基底10，所形成之切割道14的深度d可小於該基底10的厚度h(d<h)。
如圖5D所示，在基底10的正面貼合一熱壓層30，其中，該熱壓層30包含一介電層31及一離形膜層33，在貼合時將該介電層31面向該基底10的 正面，而該離形膜層33係附著在該介電層31的表面，該介電層31的材質為味之素累積膜(Ajinomoto build-up film，ABF)。相較於前述的第一、第二實施例，本實施例在該基底10的背面不需貼合第二金屬層。
如圖5E所示，將已經貼合該熱壓層30的基底10定義為一晶圓單元B。
在圖5F中，將兩片的該晶圓單元B以背對背的方式互相貼合，透過具有黏性的一接合層(thermal release film)60雙面黏合各晶圓單元B的銅層22。於相對貼合兩片的該晶圓單元B後，進行如圖5G所示的熱壓合作業，使各片晶圓單元B的介電層31在熱融後流動填充於各個切割道14的內部且覆蓋在各個晶粒12的主動面上。因為兩片晶圓單元B先貼合後可提高整體厚度，因此在進行壓合作業時，能減少各晶圓單元B發生破裂的機會。
在圖5H中，於熱壓完成後，將原本貼合的兩片晶圓單元B分離並清除該接合層60，對各晶圓單元B撕除其離形膜層33，並露出每個晶粒12的焊墊13，同樣的，於晶粒12主動面上的介電層31表面大致會與焊墊13的表面齊平。
在圖5I中，於每個晶片12的焊墊13表面形成一焊接層50，在本實施例中，該焊接層50為一金屬保護膜，例如透過無電電鍍(E’less)、無電鍍鎳浸金(ENIG)等製法將該焊接層50製作於各個焊墊13的表面；在其它實施例中，該焊接層50可以是如圖3所示的導電錫球。如圖5JK所示，在基底10的背面貼合另一支撐膜並對基底10進行第二次切割作業，以得到多個晶圓級晶片尺寸封裝件100，該第二次切割作業沿著該切割道14的位置進行切割且完全切穿該基底10，第二次切割時所用的刀具寬度係小於該切割道14的寬度W，令每個晶圓級晶片尺寸封裝件100的四周均保留有該介電層31，該晶圓級晶片尺寸封裝件100的結構亦如同圖2或圖3所示。
綜上所述，本發明以上述不同製法實施例均可製作出如圖2、圖3所示的「晶圓級晶片尺寸封裝件100」，其底部金屬層70無論是以貼合、電鍍、沉積等方式製成，均可對晶粒12的底面提供保護作用，且晶粒12產生的熱能能透過該底部金屬層70向外散熱。再者，該底部金屬層70相較於樹脂等介電材料，可提供較佳的抗電磁干擾(EMI)效果，降低外界雜訊對晶粒12的干擾；而晶粒12四周側面及主動面可獲得該介電層31包覆保護。
雖然本發明已利用上述較佳實施例揭示，然其並非用以限定本發明，任何熟習此技藝者在不脫離本發明之精神和範圍之內，相對上述實施例進行各種更動與修改仍屬本發明所保護之技術範疇，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100:晶圓級晶片尺寸封裝件
10:基底
13:焊墊
21:鈦層
31:介電層
40:第二金屬層
50:焊接層
70:底部金屬層

Claims (7)

  1. 一種晶圓級晶片尺寸封裝件，包含有：一晶粒，具有一基底及一主動面，在該主動面上設置複數個焊墊，於各焊墊的表面具有一焊接層；一介電層，該介電層覆蓋該晶粒的四個側周面的上部，而未覆蓋各個側周面的下部；該介電層另覆蓋於晶粒的該主動面，且該介電層的表面係與該焊墊的表面齊平；一底部金屬層，形成在該基底的底面，且該底部金屬層的面積與該晶粒的底面面積形狀相等。
  2. 如請求項1所述晶圓級晶片尺寸封裝件，其中，該底部金屬層是單一材料的金屬層。
  3. 如請求項1所述晶圓級晶片尺寸封裝件，其中，該底部金屬層是由不同材料疊合而成的複合金屬層。
  4. 如請求項3所述晶圓級晶片尺寸封裝件，其中，該底部金屬層包含有：依序形成在該基底的底面的一鈦層及一銅層。
  5. 如請求項3所述晶圓級晶片尺寸封裝件，其中，位在該晶粒的四個側周面上的介電層，係與未被覆蓋的基底的側周面平齊。
  6. 一種晶圓級晶片尺寸封裝方法，包含有：提供一基底，於該基底上形成有複數個晶粒，其中各該晶粒的一主動面上形成有複數個焊墊；於該基底的底面形成一底部金屬層；沿著各晶粒的周圍對該基底進行第一次切割以形成切割道，該切割道未完全貫穿該基底； 填充介電材料層於各個切割道內部，並且使該介電材料層覆蓋各該晶粒的主動面而與該複數個銲墊的表面齊平；沿著各晶粒周圍的切割道進行第二次切割，並且切穿該基底、該底部金屬層以得到分離的複數個晶圓級晶片尺寸封裝件，其中第二次切割時的切割寬度係小於該切割道的寬度，令各個晶圓級晶片尺寸封裝件的四側周面保留有該介電材料層，且各個晶圓級晶片尺寸封裝件的底面具有該底部金屬層。
  7. 一種晶圓級晶片尺寸封裝方法，包含有：提供一基底，於該基底上形成有複數個晶粒，其中各該晶粒的一主動面上形成有複數個焊墊；於該基底的底面形成一第一金屬層；沿著各晶粒的周圍對該基底進行第一次切割以形成切割道，該切割道未完全貫穿該基底；於該基底的兩面分別貼合一熱壓層及一第二金屬層，其中該熱壓層係面向該切割道且包含有一介電材料層，該第二金屬層係貼合該第一金屬層；熱壓合該熱壓層及該第二金屬層，令該介電材料層熱融後填充於各切割道且覆蓋各該晶粒的主動面而與該複數個銲墊的表面齊平；沿著各晶粒周圍的切割道進行第二次切割，並且切穿該基底、該第一金屬層、該第二金屬層以得到分離的複數個晶圓級晶片尺寸封裝件，其中第二次切割時的切割寬度係小於該切割道的寬度，令各個晶圓級晶片尺寸封裝件的四側周面保留有該介電材料層，且各個晶圓級晶片尺寸封裝件的底面具有該第一金屬層與該第二金屬層。
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