KR101034279B1 - 도체 패턴층에 전기적으로 연결된 부품을 포함하는 전자모듈 제조방법 - Google Patents

도체 패턴층에 전기적으로 연결된 부품을 포함하는 전자모듈 제조방법 Download PDF

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KR101034279B1
KR101034279B1 KR1020067026627A KR20067026627A KR101034279B1 KR 101034279 B1 KR101034279 B1 KR 101034279B1 KR 1020067026627 A KR1020067026627 A KR 1020067026627A KR 20067026627 A KR20067026627 A KR 20067026627A KR 101034279 B1 KR101034279 B1 KR 101034279B1
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layer
component
conductor layer
conductor
contact
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KR1020067026627A
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KR20070030838A (ko
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안티 이홀라
티모 조켈라
페테리 팜
리스토 투오미넨
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임베라 일렉트로닉스 오와이
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Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100736635B1 (ko) 2006-02-09 2007-07-06 삼성전기주식회사 베어칩 내장형 인쇄회로기판 및 그 제조 방법
FI20060256L (sv) 2006-03-17 2006-03-20 Imbera Electronics Oy Tillverkning av ett kretskort och ett kretskort innehållande en komponent
DE102007010731A1 (de) * 2007-02-26 2008-08-28 Würth Elektronik GmbH & Co. KG Verfahren zum Einbetten von Chips und Leiterplatte
DE102008009220A1 (de) * 2008-02-06 2009-08-13 Robert Bosch Gmbh Verfahren zum Herstellen einer Leiterplatte
US8225503B2 (en) * 2008-02-11 2012-07-24 Ibiden Co., Ltd. Method for manufacturing board with built-in electronic elements
US8264085B2 (en) 2008-05-05 2012-09-11 Infineon Technologies Ag Semiconductor device package interconnections
KR101013994B1 (ko) * 2008-10-15 2011-02-14 삼성전기주식회사 전자 소자 내장 인쇄회로기판 및 그 제조 방법
AT12316U1 (de) * 2008-10-30 2012-03-15 Austria Tech & System Tech Verfahren zur integration eines elektronischen bauteils in eine leiterplatte
KR101047484B1 (ko) * 2008-11-07 2011-07-08 삼성전기주식회사 전자 소자 내장 인쇄회로기판 및 그 제조 방법
US8124449B2 (en) 2008-12-02 2012-02-28 Infineon Technologies Ag Device including a semiconductor chip and metal foils
FI122216B (sv) 2009-01-05 2011-10-14 Imbera Electronics Oy Rigid-flex modul
FI20095110A0 (sv) * 2009-02-06 2009-02-06 Imbera Electronics Oy Elektronisk modul med EMI-skydd
DE102009058764A1 (de) 2009-12-15 2011-06-16 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur Herstellung einer elektronischen Baugruppe und elektronische Baugruppe
US8735735B2 (en) 2010-07-23 2014-05-27 Ge Embedded Electronics Oy Electronic module with embedded jumper conductor
TWI446495B (zh) * 2011-01-19 2014-07-21 Subtron Technology Co Ltd 封裝載板及其製作方法
AT13055U1 (de) * 2011-01-26 2013-05-15 Austria Tech & System Tech Verfahren zur integration eines elektronischen bauteils in eine leiterplatte oder ein leiterplatten-zwischenprodukt sowie leiterplatte oder leiterplatten-zwischenprodukt
DE102011089927A1 (de) * 2011-12-27 2013-06-27 Robert Bosch Gmbh Kontaktsystem mit einem Verbindungsmittel und Verfahren
JP2013211519A (ja) * 2012-02-29 2013-10-10 Ngk Spark Plug Co Ltd 多層配線基板の製造方法
JP6033872B2 (ja) * 2012-09-11 2016-11-30 株式会社メイコー 部品内蔵基板の製造方法
WO2014041627A1 (ja) * 2012-09-12 2014-03-20 株式会社メイコー 部品内蔵基板の製造方法
KR101420526B1 (ko) * 2012-11-29 2014-07-17 삼성전기주식회사 전자부품 내장기판 및 그 제조방법
US9425122B2 (en) 2012-12-21 2016-08-23 Panasonic Intellectual Property Management Co., Ltd. Electronic component package and method for manufacturing the same
CN104584210B (zh) 2012-12-21 2017-09-26 松下知识产权经营株式会社 电子部件封装件及其制造方法
US9825209B2 (en) 2012-12-21 2017-11-21 Panasonic Intellectual Property Management Co., Ltd. Electronic component package and method for manufacturing the same
CN104584207A (zh) 2012-12-21 2015-04-29 松下知识产权经营株式会社 电子部件封装以及其制造方法
US20150041993A1 (en) * 2013-08-06 2015-02-12 Infineon Technologies Ag Method for manufacturing a chip arrangement, and a chip arrangement
DE102013022388B3 (de) 2013-08-19 2024-01-04 Oechsler Aktiengesellschaft Chipmontage-Verfahren
JP2015050309A (ja) * 2013-08-31 2015-03-16 京セラサーキットソリューションズ株式会社 配線基板の製造方法
US9941229B2 (en) 2013-10-31 2018-04-10 Infineon Technologies Ag Device including semiconductor chips and method for producing such device
DE102014101366B3 (de) 2014-02-04 2015-05-13 Infineon Technologies Ag Chip-Montage an über Chip hinausstehender Adhäsions- bzw. Dielektrikumsschicht auf Substrat
US9806051B2 (en) 2014-03-04 2017-10-31 General Electric Company Ultra-thin embedded semiconductor device package and method of manufacturing thereof
US10649497B2 (en) * 2014-07-23 2020-05-12 Apple Inc. Adaptive processes for improving integrity of surfaces
US9613843B2 (en) * 2014-10-13 2017-04-04 General Electric Company Power overlay structure having wirebonds and method of manufacturing same
US9999136B2 (en) * 2014-12-15 2018-06-12 Ge Embedded Electronics Oy Method for fabrication of an electronic module and electronic module
US10615053B2 (en) * 2018-06-07 2020-04-07 Texas Instruments Incorporated Pre-cut plating lines on lead frames and laminate substrates for saw singulation

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1111662A2 (en) * 1999-12-22 2001-06-27 General Electric Company Apparatus and method for aligning semiconductor die to interconnect metal on flex substrate and product therefrom
JP2002290051A (ja) 2001-01-19 2002-10-04 Matsushita Electric Ind Co Ltd 部品内蔵モジュールとその製造方法

Family Cites Families (102)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB342995A (en) 1929-08-03 1931-02-12 Carba Ab Improvements in or relating to gas analysis
US4246595A (en) 1977-03-08 1981-01-20 Matsushita Electric Industrial Co., Ltd. Electronics circuit device and method of making the same
FR2527036A1 (fr) 1982-05-14 1983-11-18 Radiotechnique Compelec Procede pour connecter un semiconducteur a des elements d'un support, notamment d'une carte portative
FR2599893B1 (fr) * 1986-05-23 1996-08-02 Ricoh Kk Procede de montage d'un module electronique sur un substrat et carte a circuit integre
US4993148A (en) 1987-05-19 1991-02-19 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a circuit board
US5354695A (en) 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
BE1002529A6 (nl) 1988-09-27 1991-03-12 Bell Telephone Mfg Methode om een elektronische component te monteren en geheugen kaart waarin deze wordt toegepast.
JPH0744320B2 (ja) 1989-10-20 1995-05-15 松下電器産業株式会社 樹脂回路基板及びその製造方法
US5355102A (en) 1990-04-05 1994-10-11 General Electric Company HDI impedance matched microwave circuit assembly
US5227338A (en) 1990-04-30 1993-07-13 International Business Machines Corporation Three-dimensional memory card structure with internal direct chip attachment
JP3094481B2 (ja) 1991-03-13 2000-10-03 松下電器産業株式会社 電子回路装置とその製造方法
US5985693A (en) 1994-09-30 1999-11-16 Elm Technology Corporation High density three-dimensional IC interconnection
KR950012658B1 (ko) 1992-07-24 1995-10-19 삼성전자주식회사 반도체 칩 실장방법 및 기판 구조체
US5216806A (en) 1992-09-01 1993-06-08 Atmel Corporation Method of forming a chip package and package interconnects
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5306670A (en) 1993-02-09 1994-04-26 Texas Instruments Incorporated Multi-chip integrated circuit module and method for fabrication thereof
US5353195A (en) 1993-07-09 1994-10-04 General Electric Company Integral power and ground structure for multi-chip modules
DE69405832T2 (de) 1993-07-28 1998-02-05 Whitaker Corp Von der Peripherie-unabhängiges präzises Positionsglied für einen Halbleiterchip und Herstellungsverfahren dafür
JP2757748B2 (ja) 1993-07-30 1998-05-25 日立エーアイシー株式会社 プリント配線板
US5508561A (en) * 1993-11-15 1996-04-16 Nec Corporation Apparatus for forming a double-bump structure used for flip-chip mounting
US5510580A (en) 1993-12-07 1996-04-23 International Business Machines Corporation Printed circuit board with landless blind hole for connecting an upper wiring pattern to a lower wiring pattern
JPH08167630A (ja) * 1994-12-15 1996-06-25 Hitachi Ltd チップ接続構造
US5552633A (en) 1995-06-06 1996-09-03 Martin Marietta Corporation Three-dimensional multimodule HDI arrays with heat spreading
JPH0913567A (ja) 1995-06-30 1997-01-14 Mikio Yoshimatsu 床版及びその成形方法並びに床版の施工方法
JPH09199824A (ja) * 1995-11-16 1997-07-31 Matsushita Electric Ind Co Ltd プリント配線板とその実装体
DE69626747T2 (de) * 1995-11-16 2003-09-04 Matsushita Electric Ind Co Ltd Gedruckte Leiterplatte und ihre Anordnung
US5729049A (en) 1996-03-19 1998-03-17 Micron Technology, Inc. Tape under frame for conventional-type IC package assembly
US5936847A (en) 1996-05-02 1999-08-10 Hei, Inc. Low profile electronic circuit modules
US5838545A (en) 1996-10-17 1998-11-17 International Business Machines Corporation High performance, low cost multi-chip modle package
US5796590A (en) * 1996-11-05 1998-08-18 Micron Electronics, Inc. Assembly aid for mounting packaged integrated circuit devices to printed circuit boards
JP3176307B2 (ja) * 1997-03-03 2001-06-18 日本電気株式会社 集積回路装置の実装構造およびその製造方法
US6710614B1 (en) 1997-03-04 2004-03-23 Micron Technology, Inc. Methods for using an interposer/converter to allow single-sided contact to circuit modules
US5882957A (en) 1997-06-09 1999-03-16 Compeq Manufacturing Company Limited Ball grid array packaging method for an integrated circuit and structure realized by the method
JP3623639B2 (ja) 1997-09-29 2005-02-23 京セラ株式会社 多層配線基板の製造方法
US6038133A (en) 1997-11-25 2000-03-14 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module and method for producing the same
US6172419B1 (en) 1998-02-24 2001-01-09 Micron Technology, Inc. Low profile ball grid array package
US6430569B1 (en) * 1998-08-14 2002-08-06 Sun Microsystems, Inc. Methods and apparatus for type safe, lazy, user-defined class loading
US6232666B1 (en) 1998-12-04 2001-05-15 Mciron Technology, Inc. Interconnect for packaging semiconductor dice and fabricating BGA packages
JP3619421B2 (ja) 1999-03-30 2005-02-09 京セラ株式会社 多層配線基板の製造方法
EP1098368B1 (en) * 1999-04-16 2011-12-21 Panasonic Corporation Module component and method of manufacturing the same
JP2000311229A (ja) * 1999-04-27 2000-11-07 Hitachi Ltd Icカード及びその製造方法
JP3575001B2 (ja) 1999-05-07 2004-10-06 アムコー テクノロジー コリア インコーポレーティド 半導体パッケージ及びその製造方法
US6393148B1 (en) * 1999-05-13 2002-05-21 Hewlett-Packard Company Contrast enhancement of an image using luminance and RGB statistical metrics
KR100298828B1 (ko) 1999-07-12 2001-11-01 윤종용 재배선 필름과 솔더 접합을 이용한 웨이퍼 레벨 칩 스케일 패키지 제조방법
JP2001053447A (ja) 1999-08-05 2001-02-23 Iwaki Denshi Kk 部品内蔵型多層配線基板およびその製造方法
DE19940480C2 (de) 1999-08-26 2001-06-13 Orga Kartensysteme Gmbh Leiterbahnträgerschicht zur Einlaminierung in eine Chipkarte, Chipkarte mit einer Leiterbahnträgerschicht und Verfahren zur Herstellung einer Chipkarte
US6284564B1 (en) 1999-09-20 2001-09-04 Lockheed Martin Corp. HDI chip attachment method for reduced processing
US6242282B1 (en) 1999-10-04 2001-06-05 General Electric Company Circuit chip package and fabrication method
US6271469B1 (en) * 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
US6154366A (en) 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
TW512653B (en) 1999-11-26 2002-12-01 Ibiden Co Ltd Multilayer circuit board and semiconductor device
US6538210B2 (en) 1999-12-20 2003-03-25 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module, radio device having the same, and method for producing the same
JP3809053B2 (ja) 2000-01-20 2006-08-16 新光電気工業株式会社 電子部品パッケージ
JP4685251B2 (ja) 2000-02-09 2011-05-18 日本特殊陶業株式会社 配線基板の製造方法
US6396148B1 (en) 2000-02-10 2002-05-28 Epic Technologies, Inc. Electroless metal connection structures and methods
US6562660B1 (en) 2000-03-08 2003-05-13 Sanyo Electric Co., Ltd. Method of manufacturing the circuit device and circuit device
JP2002016327A (ja) 2000-04-24 2002-01-18 Ngk Spark Plug Co Ltd 配線基板およびその製造方法
US6292366B1 (en) 2000-06-26 2001-09-18 Intel Corporation Printed circuit board with embedded integrated circuit
US6551861B1 (en) 2000-08-22 2003-04-22 Charles W. C. Lin Method of making a semiconductor chip assembly by joining the chip to a support circuit with an adhesive
US6402970B1 (en) * 2000-08-22 2002-06-11 Charles W. C. Lin Method of making a support circuit for a semiconductor chip assembly
US6713859B1 (en) 2000-09-13 2004-03-30 Intel Corporation Direct build-up layer on an encapsulated die package having a moisture barrier structure
US6489185B1 (en) * 2000-09-13 2002-12-03 Intel Corporation Protective film for the fabrication of direct build-up layers on an encapsulated die package
JP2002094200A (ja) 2000-09-18 2002-03-29 Matsushita Electric Ind Co Ltd 回路基板用電気絶縁材と回路基板およびその製造方法
US6876072B1 (en) 2000-10-13 2005-04-05 Bridge Semiconductor Corporation Semiconductor chip assembly with chip in substrate cavity
US6576493B1 (en) 2000-10-13 2003-06-10 Bridge Semiconductor Corporation Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps
JP3554533B2 (ja) 2000-10-13 2004-08-18 シャープ株式会社 チップオンフィルム用テープおよび半導体装置
JP2002158307A (ja) 2000-11-22 2002-05-31 Toshiba Corp 半導体装置及びその製造方法
JP3407737B2 (ja) 2000-12-14 2003-05-19 株式会社デンソー 多層基板の製造方法およびその製造方法によって形成される多層基板
TW511405B (en) 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
TW511415B (en) 2001-01-19 2002-11-21 Matsushita Electric Ind Co Ltd Component built-in module and its manufacturing method
US6512182B2 (en) 2001-03-12 2003-01-28 Ngk Spark Plug Co., Ltd. Wiring circuit board and method for producing same
JP4863563B2 (ja) * 2001-03-13 2012-01-25 イビデン株式会社 プリント配線板及びプリント配線板の製造方法
TW579581B (en) 2001-03-21 2004-03-11 Ultratera Corp Semiconductor device with chip separated from substrate and its manufacturing method
JP3609737B2 (ja) 2001-03-22 2005-01-12 三洋電機株式会社 回路装置の製造方法
US6537848B2 (en) 2001-05-30 2003-03-25 St. Assembly Test Services Ltd. Super thin/super thermal ball grid array package
JP2003037205A (ja) 2001-07-23 2003-02-07 Sony Corp Icチップ内蔵多層基板及びその製造方法
US7183658B2 (en) * 2001-09-05 2007-02-27 Intel Corporation Low cost microelectronic circuit package
US6774486B2 (en) 2001-10-10 2004-08-10 Micron Technology, Inc. Circuit boards containing vias and methods for producing same
JP3870778B2 (ja) * 2001-12-20 2007-01-24 ソニー株式会社 素子内蔵基板の製造方法および素子内蔵基板
TW200302685A (en) 2002-01-23 2003-08-01 Matsushita Electric Ind Co Ltd Circuit component built-in module and method of manufacturing the same
FI115285B (sv) 2002-01-31 2005-03-31 Imbera Electronics Oy Förfarande för insänkning av en komponent i ett basmaterial och för bildning av en kontakt
FI119215B (sv) 2002-01-31 2008-08-29 Imbera Electronics Oy Förfarande för insättning av en komponent i ett basmaterial och elektronikmodul
JP2003249763A (ja) * 2002-02-25 2003-09-05 Fujitsu Ltd 多層配線基板及びその製造方法
JP2004031651A (ja) 2002-06-26 2004-01-29 Sony Corp 素子実装基板及びその製造方法
EP1542519A4 (en) 2002-07-31 2010-01-06 Sony Corp METHOD FOR PCB CONSTRUCTION WITH AN INTEGRATED EQUIPMENT AND PCB WITH INTEGRATED EQUIPMENT AND METHOD FOR PRODUCING A PRINTED PCB AND PRINTED PCB
JP4052915B2 (ja) 2002-09-26 2008-02-27 三洋電機株式会社 回路装置の製造方法
JP2004146634A (ja) 2002-10-25 2004-05-20 Murata Mfg Co Ltd 樹脂基板の製造方法、および樹脂多層基板の製造方法
FI20030293A (sv) 2003-02-26 2004-08-27 Imbera Electronics Oy Förfarande för tillverkning av en elektronikmodul och en elektronikmodul
FI119583B (sv) 2003-02-26 2008-12-31 Imbera Electronics Oy Förfarande för tillverkning av en elektronikmodul
FI115601B (sv) 2003-04-01 2005-05-31 Imbera Electronics Oy Förfarande för tillverkning av en elektronikmodul och en elektronikmodul
TW200507131A (en) 2003-07-02 2005-02-16 North Corp Multi-layer circuit board for electronic device
US7141884B2 (en) 2003-07-03 2006-11-28 Matsushita Electric Industrial Co., Ltd. Module with a built-in semiconductor and method for producing the same
FI20031201A (sv) 2003-08-26 2005-02-27 Imbera Electronics Oy Förfarande för tillverkning av en elektronikmodul och en elektronikmodul
FI20031341A (sv) 2003-09-18 2005-03-19 Imbera Electronics Oy Förfarande för tillverkning av en elektronikmodul
JPWO2005081312A1 (ja) * 2004-02-24 2008-01-17 イビデン株式会社 半導体搭載用基板
TWI237883B (en) 2004-05-11 2005-08-11 Via Tech Inc Chip embedded package structure and process thereof
TWI251910B (en) 2004-06-29 2006-03-21 Phoenix Prec Technology Corp Semiconductor device buried in a carrier and a method for fabricating the same
US7150090B2 (en) * 2004-07-16 2006-12-19 General Electric Company Method for matching a collector to replace a brushless exciter in a turbine generator drive train
FI117812B (sv) * 2004-08-05 2007-02-28 Imbera Electronics Oy Tillverkning av ett skikt innehållande en komponent
US8487194B2 (en) * 2004-08-05 2013-07-16 Imbera Electronics Oy Circuit board including an embedded component
FI117369B (sv) 2004-11-26 2006-09-15 Imbera Electronics Oy Förfarande för tillverkning av en elektronikmodul
FI119714B (sv) * 2005-06-16 2009-02-13 Imbera Electronics Oy Kretskortskonstruktion och förfarande för tillverkning av kretskortskonstruktion

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1111662A2 (en) * 1999-12-22 2001-06-27 General Electric Company Apparatus and method for aligning semiconductor die to interconnect metal on flex substrate and product therefrom
JP2001250888A (ja) 1999-12-22 2001-09-14 General Electric Co <Ge> フレキシブル基板上の相互接続用金属にダイを位置合せするための装置及び方法並びにそれによって得られた製品
JP2002290051A (ja) 2001-01-19 2002-10-04 Matsushita Electric Ind Co Ltd 部品内蔵モジュールとその製造方法

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CN101010994A (zh) 2007-08-01
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WO2005125298A3 (en) 2006-10-26
JP4796057B2 (ja) 2011-10-19
DE112005001414T5 (de) 2007-05-03
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