FI119215B - Förfarande för insättning av en komponent i ett basmaterial och elektronikmodul - Google Patents

Förfarande för insättning av en komponent i ett basmaterial och elektronikmodul Download PDF

Info

Publication number
FI119215B
FI119215B FI20020191A FI20020191A FI119215B FI 119215 B FI119215 B FI 119215B FI 20020191 A FI20020191 A FI 20020191A FI 20020191 A FI20020191 A FI 20020191A FI 119215 B FI119215 B FI 119215B
Authority
FI
Finland
Prior art keywords
component
base plate
base material
heel
polymer layer
Prior art date
Application number
FI20020191A
Other languages
English (en)
Finnish (fi)
Other versions
FI20020191A0 (sv
FI20020191A (sv
Inventor
Risto Tuominen
Original Assignee
Imbera Electronics Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=8563008&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=FI119215(B) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Imbera Electronics Oy filed Critical Imbera Electronics Oy
Priority to FI20020191A priority Critical patent/FI119215B/sv
Publication of FI20020191A0 publication Critical patent/FI20020191A0/sv
Priority to US10/502,336 priority patent/US7294529B2/en
Priority to RU2004126136/09A priority patent/RU2327311C2/ru
Priority to CN038030985A priority patent/CN1625926B/zh
Priority to AT03700816T priority patent/ATE513453T1/de
Priority to PCT/FI2003/000065 priority patent/WO2003065779A1/en
Priority to EP03700816A priority patent/EP1477048B1/en
Publication of FI20020191A publication Critical patent/FI20020191A/sv
Priority to US11/797,609 priority patent/US7732909B2/en
Priority to US11/878,557 priority patent/US7989944B2/en
Publication of FI119215B publication Critical patent/FI119215B/sv
Application granted granted Critical
Priority to US12/842,056 priority patent/US8455994B2/en
Priority to US13/185,165 priority patent/US8368201B2/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01061—Promethium [Pm]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09981—Metallised walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/061—Lamination of previously made multilayered subassemblies
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/063—Lamination of preperforated insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H05K2203/1469—Circuit made after mounting or encapsulation of the components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Claims (21)

1. Förfarande for insänkning av ätminstone en komponent (18) i ett basmaterial, varvid en första yta hos komponenten uppvisar kontaktomräden, vid vilket förfarande - en basplatta (1) väljs som basmaterial, vilken basplatta uppvisar en första yta 5 (la) och en andra yta (Ib), - ätminstone ett häl (6) utformas i basplattan för den ätminstone ena komponenten (18) pä sä sätt, att vaqe häl (6) sträcker sig genom basplattan (1) mellan den första ytan (la) och den andra ytan (Ib), - pä basplattans (1) andra yta (Ib) utbreds ett isoleringspolymerskikt (7) pä sä 10 sätt, att isoleringspolymerskiktet (7) täcker det ätminstone ena för kom ponenten (18) utformade hälet (6). - i det ätminstone ena hälet (6) anordnas den ätminstone ena komponenten (18) pä sä sätt, att komponentens (18) första yta pressas mot isoleringspolymerskiktet (7), och 15. isoleringspolymerskiktet (7) härdas, ·:··· kännetecknat av att • · · • · · *·* * - innan komponenten (18) anordnas i hälet (6) tillverkas ledarmönster (4) pä bas- ] * plattan (1), och • · • · ·· - komponenten (18) anordnas i hälet (6) pä sä sätt, att komponenten (18) in- • · • *"; 20 passas i förhällande tili de pä basplattan (1) tillverkade ledarmönstren (4). • · · • · • · · • · · • · . * * *. 2. Förfarande i enlighet med patentkrav 1,kännetecknat av att komponentens • · • · · * . (18) första yta pressas in i det ohärdade isoleringspolymerskiktet (7). • · • * * • * • · * · · • · :,*·· 25 3. Förfarande i enlighet med patentkrav 1, kännetecknat av att komponentens • · · •.,,: (18) första yta pressas in i det delvis härdade isoleringspolymerskiktet (7). 119215 21
4. Förfarandeienlighetmednägotavpatentkraven 1-3, kännetecknat av att isoleringspolymerskiktet (7) tillverkas genom att pä basplattans (1) andra yta (Ib) anordna en RCC-film (7, 8).
5. Förfarande i enlighet med nägot av patentkraven 1 -3,kännetecknat av att 5 isoleringspolymerskiktet (7) tillverkas genom att pä basplattans (1) andra yta (Ib) breda ut en pre-preg-epoxifilm (7).
6. Förfarande i enlighet med nägot av patentkraven 1 -5, kännetecknatav att pä sidoväggama av hälet (6) utformat för komponenten (18) odlas ledarmaterial 10 för att utbilda ett stömingsskydd runt komponenten (18).
7. Förfarande i enlighet med nägot av patentkraven 1 - 6, kännetecknat av att tili komponentens (18) kontaktomräden är kontaktutsprang (9) anslutna, och komponenten (18) anordnas i hälet (6) pä sä sätt, att kontaktutsprängen (9) pressas in i 15 isoleringspolymerskiktet (7). • · » • 1 · • · · *:·2: 8. Förfarande i enlighet med nägot av patentkraven 1 -6, kännetecknat av att tili komponentens (18) kontaktomräden är kontaktutspräng (9) anslutna, vilkas höjd är ätminstone lika stor som isoleringspolymerskiktets (7) tjocklek, och komponenten • · · 20 (18) anordnas i hälet (6) pä sä sätt, att kontaktutsprängen (9) penetrerar isolerings polymerskiktet (7). * · • · · • · · • · » · • « 2 • · 22 119215 - i kontaktöppningama (13) och pä isoleringspolymerskiktet (7) tillverkas ledare (14) för att bilda elektriska kontakter med komponenten (18).
10. Förfarande i enlighet med nägot av patentkraven 1-9, kännetecknat av att 5 komponenten (18) fästs pä plats i hälet (6) utformat i basplattan (1) genom att fylla hälet (6) med fyllnadsmaterial (9).
11. Förfarande i enlighet med nägot av patentkraven 1-10, kännetecknat av att komponenten utgörs av en mikrokrets och med mikrokretsen (18) bildas en 10 elektrisk kontakt i riktningen frän basplattans (1) andra yta (Ib) efter att mikrokretsen är anordnad i hälet (6) utformat i basplattan (1).
12. Förfarande i enlighet med nägot av patentkraven 1-11,kännetecknat av att med komponenten (18) bildas en elektrisk kontakt genom att pä komponentens 15 (18) kontaktomräden eller kontaktutspräng odla ett ledande material (14). e • · a · * ·* 13. Förfarande i enlighet med nägot av patentkraven 1-12, kännetecknat av att den elektriska kontakten med mikrokretsen (18) bildas utan lod medelst en krets- * · · kortstillverkningsteknik. * · t » t • · * 20 • · ·· ·
14. Förfarande i enlighet med nägot av patentkraven 1 -13, kännetecknat av att • · i basmaterialet insänks flera än en komponent (18) och i basplattan (1) utformas ett • · **··* eget häl (6) för vaije komponent (18) som skall insänkas i basmaterialet, och vaxje * komponent (18) som skall insänkas i basmaterialet anordnas i ett eget häl (6). • * · • · • • · a • · « · · • · · » * 1 • · • · ··* 119215 23
15. Förfarande i enlighet med nägot av patentkraven 1-14, kännetecknatav att en multiskiktsstruktur med ätminstone fyra pä varandra liggande ledarskikt (4,14) tillverkas.
16. Förfarande i enlighet med nägot av patentkraven 1 - 15, kännetecknatav 5 att ett första basmaterial, väri ätminstone tvä mikrokretsar (18) är insänkta, och ätminstone ett andra basmaterial, väri ätminstone tvä mikrokretsar (18) är insänkta, tillverkas, och basmaterialen staplas och fästs ovanpä varandra pä sä sätt, att basmaterialen inpassas i förhällande tili varandra. 10 17. Förfarande i enlighet med nägot av patentkraven 1-15, kännetecknat av att - ett första och andra basmaterial samt ett mellanskikt (21) tillverkas, - det andra basmaterialet anordnas ovanpä det första, och det andra basmaterialet inpassas i förhällande tili det första basmaterialet, ·:··· 15 - mellanskiktet (21) bringas mellan det första och andra basmaterialet, och • · · • · · *·* | - det första och andra basmaterialet lamineras tili varandra med hjälp av mellan- ]<#* skiktet (21). • · • · ··· • e t t i e ·· • · • * * • · *·..* 18. Förfarande i enlighet med patentkrav 17, kännetecknat av att 20 - ätminstone ett tredj e basmaterial samt ett mellanskikt för vart tredj e basmaterial • · • · tillverkas, • · 7 • · · ·;··: - vart tredje basmaterial anordnas i sin tur ovanför det första och andra bas- :’ j materialet, och vart tredje basmaterial inpassas i förhällande tili ett undre bas- .*· : material, • · · • · • * · 1 - ett mellanskikt (21) bringas under vart tredje basmaterial, och 119215 24 det första, andra och vart tredje basmaterial lamineras tili varandra med hjälp av mellanskikten (21).
19. Förfarande i enlighet med nägot av patentkraven 16-18, kännetecknat 5 av att genom de pä varandra fästa basmaterialen borras häl (23) för genomföringar, och i de borrade hälen (23) utbildas ledare för att koppia elektronikkretsama pä vaije basmaterial tili varandra för att bilda en funktionell helhet.
20. Förfarande i enlighet med nägot av patentkraven 1 - 19, kännetecknat av 10 att temperaturen av basplattan (1), komponenten (18) och ledarskiktet (14) i direkt anslutning tili komponenten (18) uppgär under processen till under 200 °C, och företrädesvis tili mellan 20 och 85 °C.
21. Elektronikmodul, som omfattar 15. en basplatta (1) som basmaterial, vilken basplatta uppvisar en första yta (la) ·:··· och en andra yta (Ib), • · · • · · *·’ | - ätminstone ett häl (6) i basplattan (1) för ätminstone en komponent (18) pä sä sätt, att vaije häl (6) sträcker sig genom basplattan (1) mellan den första • i **\ ytan (la) och den andra ytan (Ib), e « · • ·· • · ·*"; 20 - ett isoleringspolymerskikt (7) pä basplattans (1) andra yta (Ib) pä sä sätt, att *·· isoleringspolymerskiktet (7) täcker det ätminstone ena för komponenten :V: (18)utformadehälet(6). ·♦· • * - den ätminstone ena komponenten (18), vars första yta uppvisar kontakt-omräden, anordnad i det ätminstone ena för komponenten utformade hälet ··♦ 25 (6) pä sä sätt, att komponentens (18) första yta är pressad mot det härdade isoleringspolymerskiktet (7), ··» • · • e • · * 119215 25 - kontaktöppningar (13) för komponenten (18) i det härdade isolerings-polymerskiktet (7), och - ledare (14) som sträcker sig tili kontaktöppningama (13) för att bilda elektriska kontakter med komponenten (18), 5 kännetecknad av att - de ledare (14) som sträcker sig tili kontaktöppningama (13) är tillverkade pa ytan av isoleringspolymerskiktet (7), och - elektronikmodulen omfattar ledarmönster (4) pä ytan av basplattan (1). • · ··· * * · a a a • ·*··· a • · · • · • · a « * · · • I· • a a « · • a • a aa* a a • a a a a a a a a a a a a a a a a a a • a • a a a a • a aa a a a a • a a • aa a a a a a • a • a a a a
FI20020191A 2002-01-31 2002-01-31 Förfarande för insättning av en komponent i ett basmaterial och elektronikmodul FI119215B (sv)

Priority Applications (11)

Application Number Priority Date Filing Date Title
FI20020191A FI119215B (sv) 2002-01-31 2002-01-31 Förfarande för insättning av en komponent i ett basmaterial och elektronikmodul
EP03700816A EP1477048B1 (en) 2002-01-31 2003-01-28 Method for embedding a component in a base
PCT/FI2003/000065 WO2003065779A1 (en) 2002-01-31 2003-01-28 Method for embedding a component in a base
RU2004126136/09A RU2327311C2 (ru) 2002-01-31 2003-01-28 Способ встраивания компонента в основание
CN038030985A CN1625926B (zh) 2002-01-31 2003-01-28 用于将元件置入于基座中的方法
AT03700816T ATE513453T1 (de) 2002-01-31 2003-01-28 Verfahren zur einbettung einer komponente in eine basis
US10/502,336 US7294529B2 (en) 2002-01-31 2003-01-28 Method for embedding a component in a base
US11/797,609 US7732909B2 (en) 2002-01-31 2007-05-04 Method for embedding a component in a base
US11/878,557 US7989944B2 (en) 2002-01-31 2007-07-25 Method for embedding a component in a base
US12/842,056 US8455994B2 (en) 2002-01-31 2010-07-23 Electronic module with feed through conductor between wiring patterns
US13/185,165 US8368201B2 (en) 2002-01-31 2011-07-18 Method for embedding a component in a base

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI20020191 2002-01-31
FI20020191A FI119215B (sv) 2002-01-31 2002-01-31 Förfarande för insättning av en komponent i ett basmaterial och elektronikmodul

Publications (3)

Publication Number Publication Date
FI20020191A0 FI20020191A0 (sv) 2002-01-31
FI20020191A FI20020191A (sv) 2003-08-01
FI119215B true FI119215B (sv) 2008-08-29

Family

ID=8563008

Family Applications (1)

Application Number Title Priority Date Filing Date
FI20020191A FI119215B (sv) 2002-01-31 2002-01-31 Förfarande för insättning av en komponent i ett basmaterial och elektronikmodul

Country Status (7)

Country Link
US (4) US7294529B2 (sv)
EP (1) EP1477048B1 (sv)
CN (1) CN1625926B (sv)
AT (1) ATE513453T1 (sv)
FI (1) FI119215B (sv)
RU (1) RU2327311C2 (sv)
WO (1) WO2003065779A1 (sv)

Families Citing this family (107)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3617647B2 (ja) * 2002-11-08 2005-02-09 沖電気工業株式会社 半導体装置及びその製造方法
US8222723B2 (en) * 2003-04-01 2012-07-17 Imbera Electronics Oy Electric module having a conductive pattern layer
US6940705B2 (en) * 2003-07-25 2005-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor with enhanced performance and method of manufacture
US6936881B2 (en) 2003-07-25 2005-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor that includes high permittivity capacitor dielectric
US7078742B2 (en) 2003-07-25 2006-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel semiconductor structure and method of fabricating the same
US7112495B2 (en) 2003-08-15 2006-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit
FI20031341A (sv) 2003-09-18 2005-03-19 Imbera Electronics Oy Förfarande för tillverkning av en elektronikmodul
US7888201B2 (en) 2003-11-04 2011-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
FI117814B (sv) * 2004-06-15 2007-02-28 Imbera Electronics Oy Förfarande för tillverkning av en elektronikmodul
US8487194B2 (en) * 2004-08-05 2013-07-16 Imbera Electronics Oy Circuit board including an embedded component
FI117812B (sv) * 2004-08-05 2007-02-28 Imbera Electronics Oy Tillverkning av ett skikt innehållande en komponent
KR100594299B1 (ko) * 2004-10-29 2006-06-30 삼성전자주식회사 유연성 인쇄 회로 및 이것이 구비된 하드 디스크 드라이브
TWI256694B (en) * 2004-11-19 2006-06-11 Ind Tech Res Inst Structure with embedded active components and manufacturing method thereof
US20090008792A1 (en) * 2004-11-19 2009-01-08 Industrial Technology Research Institute Three-dimensional chip-stack package and active component on a substrate
FI117369B (sv) * 2004-11-26 2006-09-15 Imbera Electronics Oy Förfarande för tillverkning av en elektronikmodul
FI119714B (sv) 2005-06-16 2009-02-13 Imbera Electronics Oy Kretskortskonstruktion och förfarande för tillverkning av kretskortskonstruktion
FI122128B (sv) * 2005-06-16 2011-08-31 Imbera Electronics Oy Förfarande för tillverkning av kretskortskonstruktion
GB2441265B (en) 2005-06-16 2012-01-11 Imbera Electronics Oy Method for manufacturing a circuit board structure, and a circuit board structure
US8072059B2 (en) * 2006-04-19 2011-12-06 Stats Chippac, Ltd. Semiconductor device and method of forming UBM fixed relative to interconnect structure for alignment of semiconductor die
US7859098B2 (en) * 2006-04-19 2010-12-28 Stats Chippac Ltd. Embedded integrated circuit package system
US8546929B2 (en) * 2006-04-19 2013-10-01 Stats Chippac Ltd. Embedded integrated circuit package-on-package system
JP3942190B1 (ja) * 2006-04-25 2007-07-11 国立大学法人九州工業大学 両面電極構造の半導体装置及びその製造方法
US8558278B2 (en) 2007-01-16 2013-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Strained transistor with optimized drive current and method of forming
DE102007024189A1 (de) * 2007-05-24 2008-11-27 Robert Bosch Gmbh Verfahren zur Herstellung einer elektronischen Baugruppe
JP5012896B2 (ja) * 2007-06-26 2012-08-29 株式会社村田製作所 部品内蔵基板の製造方法
TWI360207B (en) 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
US7943961B2 (en) 2008-03-13 2011-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Strain bars in stressed layers of MOS devices
DE102008000842A1 (de) * 2008-03-27 2009-10-01 Robert Bosch Gmbh Verfahren zur Herstellung einer elektronischen Baugruppe
US8259454B2 (en) * 2008-04-14 2012-09-04 General Electric Company Interconnect structure including hybrid frame panel
US8264085B2 (en) 2008-05-05 2012-09-11 Infineon Technologies Ag Semiconductor device package interconnections
AT10247U8 (de) * 2008-05-30 2008-12-15 Austria Tech & System Tech Verfahren zur integration wenigstens eines elektronischen bauteils in eine leiterplatte sowie leiterplatte
KR101055471B1 (ko) * 2008-09-29 2011-08-08 삼성전기주식회사 전자소자 내장형 인쇄회로기판 및 그 제조방법
US7808051B2 (en) 2008-09-29 2010-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell without OD space effect in Y-direction
US8114708B2 (en) * 2008-09-30 2012-02-14 General Electric Company System and method for pre-patterned embedded chip build-up
DE102008043122A1 (de) * 2008-10-23 2010-04-29 Robert Bosch Gmbh Elektrische Schaltungsanordnung sowie Verfahren zum Herstellen einer elektrischen Schaltungsanordnung
JP5833926B2 (ja) 2008-10-30 2015-12-16 アーテー・ウント・エス・オーストリア・テヒノロギー・ウント・ジュステームテッヒニク・アクチェンゲゼルシャフトＡｔ ＆ Ｓ Ａｕｓｔｒｉａ Ｔｅｃｈｎｏｌｏｇｉｅ ＆ Ｓｙｓｔｅｍｔｅｃｈｎｉｋ Ａｋｔｉｅｎｇｅｓｅｌｌｓｃｈａｆｔ 電子構成部品をプリント回路基板に組み込むための方法
US8124449B2 (en) 2008-12-02 2012-02-28 Infineon Technologies Ag Device including a semiconductor chip and metal foils
US7935570B2 (en) * 2008-12-10 2011-05-03 Stats Chippac, Ltd. Semiconductor device and method of embedding integrated passive devices into the package electrically interconnected using conductive pillars
TWI417993B (zh) * 2009-02-04 2013-12-01 Unimicron Technology Corp 具凹穴結構的封裝基板、半導體封裝體及其製作方法
US7977785B2 (en) * 2009-03-05 2011-07-12 Freescale Semiconductor, Inc. Electronic device including dies, a dielectric layer, and a encapsulating layer
US8049114B2 (en) * 2009-03-22 2011-11-01 Unimicron Technology Corp. Package substrate with a cavity, semiconductor package and fabrication method thereof
JP5372579B2 (ja) * 2009-04-10 2013-12-18 新光電気工業株式会社 半導体装置及びその製造方法、並びに電子装置
TWI456715B (zh) 2009-06-19 2014-10-11 Advanced Semiconductor Eng 晶片封裝結構及其製造方法
KR101170878B1 (ko) * 2009-06-29 2012-08-02 삼성전기주식회사 반도체 칩 패키지 및 그의 제조방법
DE102009032219A1 (de) * 2009-07-06 2011-02-24 Institut Für Mikroelektronik Stuttgart Verfahren zum Herstellen einer integrierten Schaltung und resultierender Folienchip
JP5296636B2 (ja) * 2009-08-21 2013-09-25 新光電気工業株式会社 半導体パッケージの製造方法
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8320134B2 (en) 2010-02-05 2012-11-27 Advanced Semiconductor Engineering, Inc. Embedded component substrate and manufacturing methods thereof
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
WO2012005394A1 (en) * 2010-07-09 2012-01-12 Lg Innotek Co., Ltd. Printed circuit board and method of manufacturing the same
US8735735B2 (en) 2010-07-23 2014-05-27 Ge Embedded Electronics Oy Electronic module with embedded jumper conductor
US8941222B2 (en) 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
US8680683B1 (en) 2010-11-30 2014-03-25 Triquint Semiconductor, Inc. Wafer level package with embedded passive components and method of manufacturing
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
AT13055U1 (de) 2011-01-26 2013-05-15 Austria Tech & System Tech Verfahren zur integration eines elektronischen bauteils in eine leiterplatte oder ein leiterplatten-zwischenprodukt sowie leiterplatte oder leiterplatten-zwischenprodukt
US8923008B2 (en) * 2011-03-08 2014-12-30 Ibiden Co., Ltd. Circuit board and method for manufacturing circuit board
US8487426B2 (en) 2011-03-15 2013-07-16 Advanced Semiconductor Engineering, Inc. Semiconductor package with embedded die and manufacturing methods thereof
US8603858B2 (en) 2011-07-12 2013-12-10 Infineon Technologies Ag Method for manufacturing a semiconductor package
AT13436U1 (de) 2011-08-31 2013-12-15 Austria Tech & System Tech Verfahren zur integration eines bauteils in eine leiterplatte oder ein leiterplatten-zwischenprodukt sowie leiterplatte oder leiterplatten-zwischenprodukt
AT13432U1 (de) 2011-08-31 2013-12-15 Austria Tech & System Tech Verfahren zur integration eines bauteils in eine leiterplatte oder ein leiterplatten-zwischenprodukt sowie leiterplatte oder leiterplatten-zwischenprodukt
US11445617B2 (en) * 2011-10-31 2022-09-13 Unimicron Technology Corp. Package structure and manufacturing method thereof
KR101233640B1 (ko) 2011-11-28 2013-02-15 대덕전자 주식회사 내장형 인쇄회로기판의 수율 향상방법
DE102011089415A1 (de) * 2011-12-21 2013-06-27 Siemens Aktiengesellschaft Schaltungsträger mit einem Leitpfad und einer elektrischen Schirmung und Verfahren zu dessen Herstellung
DE102011089927A1 (de) * 2011-12-27 2013-06-27 Robert Bosch Gmbh Kontaktsystem mit einem Verbindungsmittel und Verfahren
CN104145334B (zh) * 2012-03-01 2018-05-22 皇家飞利浦有限公司 电子电路的线布置及其制造方法
US9281260B2 (en) * 2012-03-08 2016-03-08 Infineon Technologies Ag Semiconductor packages and methods of forming the same
US8901730B2 (en) 2012-05-03 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for package on package devices
TWI540768B (zh) * 2012-12-21 2016-07-01 鴻海精密工業股份有限公司 發光晶片組合及其製造方法
AT514074B1 (de) 2013-04-02 2014-10-15 Austria Tech & System Tech Verfahren zum Herstellen eines Leiterplattenelements
US9793218B2 (en) * 2013-05-14 2017-10-17 Meiko Electronics Co., Ltd. Method for manufacturing device embedded substrate, and device embedded substrate
US8912663B1 (en) 2013-06-28 2014-12-16 Delta Electronics, Inc. Embedded package structure and method for manufacturing thereof
US8828807B1 (en) * 2013-07-17 2014-09-09 Infineon Technologies Ag Method of packaging integrated circuits and a molded substrate with non-functional placeholders embedded in a molding compound
US20150041993A1 (en) * 2013-08-06 2015-02-12 Infineon Technologies Ag Method for manufacturing a chip arrangement, and a chip arrangement
US9275878B2 (en) 2013-10-01 2016-03-01 Infineon Technologies Ag Metal redistribution layer for molded substrates
US9171795B2 (en) * 2013-12-16 2015-10-27 Stats Chippac Ltd. Integrated circuit packaging system with embedded component and method of manufacture thereof
DE102014101366B3 (de) * 2014-02-04 2015-05-13 Infineon Technologies Ag Chip-Montage an über Chip hinausstehender Adhäsions- bzw. Dielektrikumsschicht auf Substrat
US10542917B2 (en) 2014-02-10 2020-01-28 Battelle Memorial Institute Printed circuit board with embedded sensor
SG10201400396WA (en) 2014-03-05 2015-10-29 Delta Electronics Int’L Singapore Pte Ltd Package structure and stacked package module with the same
SG10201400390YA (en) 2014-03-05 2015-10-29 Delta Electronics Int L Singapore Pte Ltd Package structure
RU2572588C1 (ru) * 2014-08-19 2016-01-20 Федеральное государственное автономное образовательное учреждение высшего образования "Национальный исследовательский университет "Московский институт электронной техники" Способ изготовления электронных узлов на гибком носителе без процессов пайки и сварки
CN104241219B (zh) 2014-08-26 2019-06-21 日月光半导体制造股份有限公司 元件嵌入式封装结构和其制造方法
RU2576666C1 (ru) * 2014-08-28 2016-03-10 Публичное акционерное общество "Радиофизика" Способ монтажа мощного полупроводникового элемента
TWI778938B (zh) 2015-03-16 2022-10-01 美商艾馬克科技公司 半導體裝置和製造其之方法
KR101678418B1 (ko) * 2015-03-16 2016-11-23 한국생산기술연구원 3차원 레이저 스캐닝 시스템
RU2597210C1 (ru) * 2015-05-28 2016-09-10 Федеральное государственное автономное образовательное учреждение высшего образования "Национальный исследовательский университет "Московский институт электронной техники" Способ изготовления микроэлектронного узла на пластичном основании
WO2017095419A1 (en) * 2015-12-03 2017-06-08 Intel Corporation A hybrid microelectronic substrate and methods for fabricating the same
US10763215B2 (en) 2015-12-09 2020-09-01 Intel Corporation Hybrid microelectronic substrate and methods for fabricating the same
CN107295747B (zh) 2016-03-31 2021-03-12 奥特斯(中国)有限公司 器件载体及制造器件载体的方法
CN107295746B (zh) 2016-03-31 2021-06-15 奥特斯(中国)有限公司 器件载体及其制造方法
KR20170112363A (ko) * 2016-03-31 2017-10-12 삼성전기주식회사 전자부품 패키지 및 그 제조방법
RU2639720C2 (ru) * 2016-06-14 2017-12-22 Федеральное государственное унитарное предприятие "Научно-производственный центр автоматики и приборостроения имени академика Н.А. Пилюгина" (ФГУП "НПЦАП") Печатная плата с внутренним монтажом элементов и способ ее изготовления
JP6625491B2 (ja) * 2016-06-29 2019-12-25 新光電気工業株式会社 配線基板、半導体装置、配線基板の製造方法
US9887167B1 (en) 2016-09-19 2018-02-06 Advanced Semiconductor Engineering, Inc. Embedded component package structure and method of manufacturing the same
JP6711229B2 (ja) 2016-09-30 2020-06-17 日亜化学工業株式会社 プリント基板の製造方法及び発光装置の製造方法
US10312194B2 (en) 2016-11-04 2019-06-04 General Electric Company Stacked electronics package and method of manufacturing thereof
US10700035B2 (en) 2016-11-04 2020-06-30 General Electric Company Stacked electronics package and method of manufacturing thereof
US9966371B1 (en) 2016-11-04 2018-05-08 General Electric Company Electronics package having a multi-thickness conductor layer and method of manufacturing thereof
US9966361B1 (en) 2016-11-04 2018-05-08 General Electric Company Electronics package having a multi-thickness conductor layer and method of manufacturing thereof
US10206286B2 (en) 2017-06-26 2019-02-12 Infineon Technologies Austria Ag Embedding into printed circuit board with drilling
US10446521B2 (en) * 2017-11-07 2019-10-15 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating an integrated fan-out package
SG10201802515PA (en) 2018-03-27 2019-10-30 Delta Electronics Int’L Singapore Pte Ltd Packaging process
US10497648B2 (en) 2018-04-03 2019-12-03 General Electric Company Embedded electronics package with multi-thickness interconnect structure and method of making same
TWI770419B (zh) * 2018-10-31 2022-07-11 南韓商三星電子股份有限公司 半導體封裝及包括其的天線模組
RU196513U1 (ru) * 2019-12-19 2020-03-03 Федеральное государственное бюджетное образовательное учреждение высшего образования "МИРЭА - Российский технологический университет" Высокоплотный электронный модуль
CN111128977A (zh) * 2019-12-25 2020-05-08 华进半导体封装先导技术研发中心有限公司 一种多层芯片的封装结构和封装方法
KR20220027537A (ko) * 2020-08-27 2022-03-08 삼성전자주식회사 팬-아웃 타입 반도체 패키지
US11978699B2 (en) * 2021-08-19 2024-05-07 Texas Instruments Incorporated Electronic device multilevel package substrate for improved electromigration preformance

Family Cites Families (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4246595A (en) 1977-03-08 1981-01-20 Matsushita Electric Industrial Co., Ltd. Electronics circuit device and method of making the same
US4783695A (en) 1986-09-26 1988-11-08 General Electric Company Multichip integrated circuit packaging configuration and method
US4894115A (en) 1989-02-14 1990-01-16 General Electric Company Laser beam scanning method for forming via holes in polymer materials
US5208188A (en) * 1989-10-02 1993-05-04 Advanced Micro Devices, Inc. Process for making a multilayer lead frame assembly for an integrated circuit structure and multilayer integrated circuit die package formed by such process
JPH0744320B2 (ja) 1989-10-20 1995-05-15 松下電器産業株式会社 樹脂回路基板及びその製造方法
US5227338A (en) * 1990-04-30 1993-07-13 International Business Machines Corporation Three-dimensional memory card structure with internal direct chip attachment
JP3094481B2 (ja) 1991-03-13 2000-10-03 松下電器産業株式会社 電子回路装置とその製造方法
US5250843A (en) 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
US5162613A (en) * 1991-07-01 1992-11-10 At&T Bell Laboratories Integrated circuit interconnection technique
US5102829A (en) * 1991-07-22 1992-04-07 At&T Bell Laboratories Plastic pin grid array package
US5216806A (en) * 1992-09-01 1993-06-08 Atmel Corporation Method of forming a chip package and package interconnects
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5306670A (en) * 1993-02-09 1994-04-26 Texas Instruments Incorporated Multi-chip integrated circuit module and method for fabrication thereof
US5353195A (en) 1993-07-09 1994-10-04 General Electric Company Integral power and ground structure for multi-chip modules
DE69405832T2 (de) * 1993-07-28 1998-02-05 Whitaker Corp Von der Peripherie-unabhängiges präzises Positionsglied für einen Halbleiterchip und Herstellungsverfahren dafür
JPH08167630A (ja) 1994-12-15 1996-06-25 Hitachi Ltd チップ接続構造
CN1094717C (zh) 1995-11-16 2002-11-20 松下电器产业株式会社 印刷电路板的安装体
US5869869A (en) * 1996-01-31 1999-02-09 Lsi Logic Corporation Microelectronic device with thin film electrostatic discharge protection structure
US5729049A (en) * 1996-03-19 1998-03-17 Micron Technology, Inc. Tape under frame for conventional-type IC package assembly
JP3345878B2 (ja) * 1997-02-17 2002-11-18 株式会社デンソー 電子回路装置の製造方法
US5943216A (en) 1997-06-03 1999-08-24 Photo Opto Electronic Technologies Apparatus for providing a two-sided, cavity, inverted-mounted component circuit board
US5919329A (en) * 1997-10-14 1999-07-06 Gore Enterprise Holdings, Inc. Method for assembling an integrated circuit chip package having at least one semiconductor device
US6038133A (en) 1997-11-25 2000-03-14 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module and method for producing the same
US6495394B1 (en) * 1999-02-16 2002-12-17 Sumitomo Metal (Smi) Electronics Devices Inc. Chip package and method for manufacturing the same
US6172419B1 (en) * 1998-02-24 2001-01-09 Micron Technology, Inc. Low profile ball grid array package
US6131269A (en) * 1998-05-18 2000-10-17 Trw Inc. Circuit isolation technique for RF and millimeter-wave modules
US6239485B1 (en) * 1998-11-13 2001-05-29 Fujitsu Limited Reduced cross-talk noise high density signal interposer with power and ground wrap
JP2000311229A (ja) 1999-04-27 2000-11-07 Hitachi Ltd Ｉｃカード及びその製造方法
JP3575001B2 (ja) * 1999-05-07 2004-10-06 アムコー テクノロジー コリア インコーポレーティド 半導体パッケージ及びその製造方法
JP2001053447A (ja) 1999-08-05 2001-02-23 Iwaki Denshi Kk 部品内蔵型多層配線基板およびその製造方法
US6312972B1 (en) * 1999-08-09 2001-11-06 International Business Machines Corporation Pre-bond encapsulation of area array terminated chip and wafer scale packages
US6284564B1 (en) 1999-09-20 2001-09-04 Lockheed Martin Corp. HDI chip attachment method for reduced processing
US6271469B1 (en) 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
US6154366A (en) 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
US6538210B2 (en) 1999-12-20 2003-03-25 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module, radio device having the same, and method for producing the same
US6475877B1 (en) 1999-12-22 2002-11-05 General Electric Company Method for aligning die to interconnect metal on flex substrate
JP3809053B2 (ja) 2000-01-20 2006-08-16 新光電気工業株式会社 電子部品パッケージ
JP4685251B2 (ja) 2000-02-09 2011-05-18 日本特殊陶業株式会社 配線基板の製造方法
US6396148B1 (en) 2000-02-10 2002-05-28 Epic Technologies, Inc. Electroless metal connection structures and methods
JP2002016327A (ja) * 2000-04-24 2002-01-18 Ngk Spark Plug Co Ltd 配線基板およびその製造方法
US6404043B1 (en) * 2000-06-21 2002-06-11 Dense-Pac Microsystems, Inc. Panel stacking of BGA devices to form three-dimensional modules
US6292366B1 (en) 2000-06-26 2001-09-18 Intel Corporation Printed circuit board with embedded integrated circuit
US20020020898A1 (en) * 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6350633B1 (en) 2000-08-22 2002-02-26 Charles W. C. Lin Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint
US6562657B1 (en) 2000-08-22 2003-05-13 Charles W. C. Lin Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint
US6489185B1 (en) 2000-09-13 2002-12-03 Intel Corporation Protective film for the fabrication of direct build-up layers on an encapsulated die package
JP3554533B2 (ja) * 2000-10-13 2004-08-18 シャープ株式会社 チップオンフィルム用テープおよび半導体装置
JP2002202025A (ja) * 2000-11-06 2002-07-19 Auto Network Gijutsu Kenkyusho:Kk インジェクタ一体型モジュール
JP2002158307A (ja) 2000-11-22 2002-05-31 Toshiba Corp 半導体装置及びその製造方法
JP2003152317A (ja) * 2000-12-25 2003-05-23 Ngk Spark Plug Co Ltd 配線基板
TW511405B (en) 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
TW511415B (en) 2001-01-19 2002-11-21 Matsushita Electric Ind Co Ltd Component built-in module and its manufacturing method
SG100635A1 (en) * 2001-03-09 2003-12-26 Micron Technology Inc Die support structure
US6512182B2 (en) 2001-03-12 2003-01-28 Ngk Spark Plug Co., Ltd. Wiring circuit board and method for producing same
TW579581B (en) * 2001-03-21 2004-03-11 Ultratera Corp Semiconductor device with chip separated from substrate and its manufacturing method
US6537848B2 (en) * 2001-05-30 2003-03-25 St. Assembly Test Services Ltd. Super thin/super thermal ball grid array package
JP2003037205A (ja) 2001-07-23 2003-02-07 Sony Corp Ｉｃチップ内蔵多層基板及びその製造方法
TW550997B (en) * 2001-10-18 2003-09-01 Matsushita Electric Ind Co Ltd Module with built-in components and the manufacturing method thereof
TW200302685A (en) 2002-01-23 2003-08-01 Matsushita Electric Ind Co Ltd Circuit component built-in module and method of manufacturing the same
TWI237883B (en) * 2004-05-11 2005-08-11 Via Tech Inc Chip embedded package structure and process thereof
TWI251910B (en) * 2004-06-29 2006-03-21 Phoenix Prec Technology Corp Semiconductor device buried in a carrier and a method for fabricating the same

Also Published As

Publication number Publication date
EP1477048A1 (en) 2004-11-17
US7989944B2 (en) 2011-08-02
RU2327311C2 (ru) 2008-06-20
US7732909B2 (en) 2010-06-08
RU2004126136A (ru) 2005-05-27
US20070206366A1 (en) 2007-09-06
FI20020191A0 (sv) 2002-01-31
US8368201B2 (en) 2013-02-05
US7294529B2 (en) 2007-11-13
WO2003065779A1 (en) 2003-08-07
ATE513453T1 (de) 2011-07-15
US20080036093A1 (en) 2008-02-14
EP1477048B1 (en) 2011-06-15
CN1625926A (zh) 2005-06-08
CN1625926B (zh) 2010-05-26
FI20020191A (sv) 2003-08-01
US20050224988A1 (en) 2005-10-13
US20110266041A1 (en) 2011-11-03

Similar Documents

Publication Publication Date Title
FI119215B (sv) Förfarande för insättning av en komponent i ett basmaterial och elektronikmodul
FI115285B (sv) Förfarande för insänkning av en komponent i ett basmaterial och för bildning av en kontakt
US20200187358A1 (en) Method for manufacturing an electronic module and electronic module
FI119583B (sv) Förfarande för tillverkning av en elektronikmodul
FI115601B (sv) Förfarande för tillverkning av en elektronikmodul och en elektronikmodul
FI117814B (sv) Förfarande för tillverkning av en elektronikmodul
US20070131349A1 (en) Method for manufacturing an electronic module, and an electronic module
US20080211083A1 (en) Electronic package and manufacturing method thereof
EP3833163A1 (en) Method of manufacturing component carrier and component carrier
JP5150720B2 (ja) 電子アッセンブリーの製造方法並びに電子アッセンブリー
CN112992776A (zh) 封装方法、封装结构及封装模块

Legal Events

Date Code Title Description
FG Patent granted

Ref document number: 119215

Country of ref document: FI

PC Transfer of assignment of patent

Owner name: GE EMBEDDED ELECTRONICS OY

PC Transfer of assignment of patent

Owner name: IMBERA TEK, LLC

MA Patent expired