FI117369B - Förfarande för tillverkning av en elektronikmodul - Google Patents

Förfarande för tillverkning av en elektronikmodul Download PDF

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Publication number
FI117369B
FI117369B FI20041524A FI20041524A FI117369B FI 117369 B FI117369 B FI 117369B FI 20041524 A FI20041524 A FI 20041524A FI 20041524 A FI20041524 A FI 20041524A FI 117369 B FI117369 B FI 117369B
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Finland
Prior art keywords
layer
conductor
component
film
contact
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FI20041524A
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English (en)
Finnish (fi)
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FI20041524A (sv
FI20041524A0 (sv
Inventor
Antti Iihola
Risto Tuominen
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Imbera Electronics Oy
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Application filed by Imbera Electronics Oy filed Critical Imbera Electronics Oy
Priority to FI20041524A priority Critical patent/FI117369B/sv
Publication of FI20041524A0 publication Critical patent/FI20041524A0/sv
Priority to JP2007542017A priority patent/JP5160895B2/ja
Priority to PCT/FI2005/000499 priority patent/WO2006056643A2/en
Priority to CN2005800402916A priority patent/CN101065843B/zh
Priority to US11/667,429 priority patent/US8062537B2/en
Priority to KR1020077014479A priority patent/KR101101603B1/ko
Publication of FI20041524A publication Critical patent/FI20041524A/sv
Application granted granted Critical
Publication of FI117369B publication Critical patent/FI117369B/sv

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/82009—Pre-treatment of the connector or the bonding area
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    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
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    • H01L2224/8312—Aligning
    • H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/83132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Claims (12)

1. Förfarande för tillverkning av en elektronikmodul, vilken innehäller ätminstone en komponent (6) med ätminstone ett kontaktomräde (7), vilket är elektriskt anslutet tili ett 5 ledarmönsterskikt (14), k ä n n e t e c k n a t av att vid förfarandet: - väljs en skiktfilm, vilken omfattar ätminstone ett ledarskikt (4) samt ett isoleringsskikt (10) pä en första yta av ledarskiktet (4), - utformas kontaktöppningar (17), vilkas inbördes position motsvarar den inbördes positionen for vaije for fästning avsedd komponents (6) kontaktomräden (7) och 10 vilka penetrerar bäde ledarskiktet (4) och isoleringsskiktet (10), - fasts efter utformningen av kontaktöppningama (17) varje komponent (6) pä ytan (6) av skiktfilmens isoleringsskikt (10) pä sä sätt anordnat, att komponentens (6) kontaktomräden (7) kommer att ligga mot motsvarande kontaktöppningar (17), - framställs ätminstone i kontaktöppningama (17) och komponentens (6) kontakt- 15 omraden (7) ledarraaterial, vilket ansluter komponenten (6) tili ledarskiktet (4), och - ledarskiktet (4) konfigureras tili ett ledarmönsterskikt (14). M· * • «M • « • i i « ♦· • ·
2. Förfarande i enlighet med patentkrav 1, kännetecknat av att före *:**: utformningen av kontaktöppningama (17): bestär skiktfilmen av ett ledarskikt (4) samt 20 ett isoleringsskikt (10) pä den första ytan av ledarskiktet (4). • v · i * • * «ta I
: 3. Förfarande i enlighet med patentkrav 1, kännetecknat av att före I utformningen av kontaktöppningama (17): omfattar skiktfilmen ett stödskikt (12) pä I den andra ytan av ledarskiktet (4). I M * 117369
4. Förfarande i enlighet med nägot av patentkraven 1-3, kännetecknat av att före utformningen av kontaktöppningama (17): innehäller skiktfilmens ledarskikt (4) väsentligen alli det ledarmaterial varav ledarmonsterskiktet (14) senare bildas.
5 5. Förfarande i enlighet med nägot av patentkraven 1-4, kännetecknat av att skiktfilmens isoleringsskikt (10) utgörs av epoxi.
6. Förfarande i enlighet med nägot av patentkraven 1-5, kännetecknat av att tjockleken av skiktfilmens isoleringsskikt (10) ligger under 10 mikrometer, lämpligen i 10 intervallet 4-7 mikrometer.
7. Förfarande i enlighet med nägot av patentkraven 1-6, kännetecknat av att komponenten fasts vid isoleringsskiktet (10) medelst isolerande lim (5). 15
8. Förfarande i enlighet med nägot av patentkraven 1-7, kännetecknat av att ·;· ledarmaterialet, som ansluter komponenten (6) tili ledarskiktet (4), framställs medelst *··« ett kemiskt och/eller elektrokemiskt metalliseringsförfarande. • e * « · • · · ··· · * » ββ·ϊ·
9. Förfarande i enlighet med nägot av patentkraven 1-8, kännetecknat av att 20 ledarmaterialet, som ansluter komponenten (6) tili ledarskiktet (4), utformas genom att fylla kontaktöppningama (17) med ledarmaterial, t.ex. ledande pasta. • i « e t · » ·#· ··# • ψ *99 9 : V.
10. Förfarande i enlighet med nägot av patentkraven 1-9, kännetecknat av att i • * . * * ·; elektronikmodulen tillverkas ätminstone ett andra ledarmönsterskikt (19). at* ·:··: 25 99 9 9 9 9 9 9 * t 117369
11. Förfarande i enlighet med nigot av patentkraven 1-10, kännetecknat av att i elektronikmodulen anordnas flera än en komponent (6) och de insänkta komponentema (6) ansluts elektriskt med varandra för att bilda en fimktionell helhet. 5
12. Förfarande i enlighet med nägot av patentkraven 1-11, där ätminstone en komponent (6) avsedd att fästas vid ledarskiktet (4) utgörs av en icke-packad mikrokretschip. • f · « «««« • · • « 1 • ·· • 9 • 1 • · » * · « ««I « ft ft ft ··· ft • ••ft ft ·· ft ft ft ft ft ft ft • • ft ft ft ft ft • •ft • ft· ft ft ft ft ··· ft • ft ft ft ft ft • ft ft ft ftft ft ft ft ft ft·· ft • ft ft «· ft ft · ft • ft ft ft
FI20041524A 2004-11-26 2004-11-26 Förfarande för tillverkning av en elektronikmodul FI117369B (sv)

Priority Applications (6)

Application Number Priority Date Filing Date Title
FI20041524A FI117369B (sv) 2004-11-26 2004-11-26 Förfarande för tillverkning av en elektronikmodul
JP2007542017A JP5160895B2 (ja) 2004-11-26 2005-11-23 電子モジュールの製造方法
PCT/FI2005/000499 WO2006056643A2 (en) 2004-11-26 2005-11-23 Method for manufacturing an electronics module
CN2005800402916A CN101065843B (zh) 2004-11-26 2005-11-23 制造电子模块的方法
US11/667,429 US8062537B2 (en) 2004-11-26 2005-11-23 Method for manufacturing an electronics module
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KR20070086645A (ko) 2007-08-27
KR101101603B1 (ko) 2012-01-02
US8062537B2 (en) 2011-11-22
US20070267136A1 (en) 2007-11-22
FI20041524A (sv) 2006-03-17
WO2006056643A2 (en) 2006-06-01
FI20041524A0 (sv) 2004-11-26
CN101065843B (zh) 2010-08-18
WO2006056643A3 (en) 2006-11-09
JP5160895B2 (ja) 2013-03-13
CN101065843A (zh) 2007-10-31
JP2008522396A (ja) 2008-06-26

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