FI117812B - Tillverkning av ett skikt innehållande en komponent - Google Patents
Tillverkning av ett skikt innehållande en komponent Download PDFInfo
- Publication number
- FI117812B FI117812B FI20041059A FI20041059A FI117812B FI 117812 B FI117812 B FI 117812B FI 20041059 A FI20041059 A FI 20041059A FI 20041059 A FI20041059 A FI 20041059A FI 117812 B FI117812 B FI 117812B
- Authority
- FI
- Finland
- Prior art keywords
- layer
- conductor
- component
- insulating material
- conductor layer
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000004020 conductor Substances 0.000 claims description 92
- 238000000034 method Methods 0.000 claims description 52
- 239000011810 insulating material Substances 0.000 claims description 43
- 239000000853 adhesive Substances 0.000 claims description 28
- 230000001070 adhesive effect Effects 0.000 claims description 28
- 239000000463 material Substances 0.000 claims description 21
- 239000000126 substance Substances 0.000 claims description 6
- 239000012774 insulation material Substances 0.000 claims description 4
- 238000001465 metallisation Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 143
- 239000010949 copper Substances 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000012790 adhesive layer Substances 0.000 description 5
- 238000004026 adhesive bonding Methods 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 4
- 239000003292 glue Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 229920000106 Liquid crystal polymer Polymers 0.000 description 2
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 238000002848 electrochemical method Methods 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 241000531908 Aramides Species 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229920003235 aromatic polyamide Polymers 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011152 fibreglass Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- -1 polytetrafluoroethylene Polymers 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000000746 purification Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
Classifications
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/82009—Pre-treatment of the connector or the bonding area
- H01L2224/8203—Reshaping, e.g. forming vias
- H01L2224/82035—Reshaping, e.g. forming vias by heating means
- H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
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- H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
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- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Claims (17)
1. Förfarande för tillverkning av ett kretskortsskikt pä en bottenyta (2), vilken bottenyta (2) omfattar ledarmönster (19) och kretskortsskiktet omfattar ett ledar-mönsterskikt (14), ett isoleringsmaterialskikt (1) samt atminstone en komponent (6) 5 inne i isoleringsmaterialskiktet (1), k ä n n e t e c k n a t av att: - ett ledarskikt (4) väljs och den nämnda atminstone ena komponenten (6) fästs vid ledarskiktet (4) pä sidan av en forsta yta pä ledarskiktet, - ledarskiktet (4) inpassas i förhällande tili bottenytan (2) och ledarskiktet fästs med hjälp av isoleringsmaterialet (1) vid bottenytan (2) med ledarskiktets (4) forsta yta 10 mot bottenytan (2), varvid isoleringsmaterialskiktet (1) bildas mellan ledarskiktet (4) och bottenytan (2), i vilket isoleringsmaterialskikt den nämnda atminstone ena komponenten (6) placerar sig, - elektriska kontakter bildas mellan komponentens (6) kontaktomräden (7) och ledar- ... skiktct (4) pä sä sätt, att vid komponentens (6) kontaktomräden (7) öppnas kontakt- • · · j 15 öppningar (17) och i kontaktöppningarna(17) utformas ledarmaterial, • · · ··· · ··· • * • · m”]· - ledarskiktet (4) konfigureras tili ett ledarmönsterskikt (14), och • · ··* 1·''ψ - atminstone en genomföring (20) utformas mellan ledarmönsterskiktet (14) och * · bottenytans (2) ledarmönster (19).
• · * · · • · · "···[ 2. Förfarande i enlighet med patentkrav 1, k ä n n e t e c k n a t av att bottenytan (2) • · ·' 20 utgörs av kretskortets yta.
• · * · · • · · • · **”’ 3. Förfarande i enlighet med patentkrav 1 eller 2, kännetecknat av att en komponent (6), t.ex. en mikrokrets, fasts vid ledarskiktet (4) med hjälp av ett isolerande • · · Hm (5), och efter fästningen bildas en elektriskt kontakt mellan ledarskiktet och 117812 15 kontaktomrädena eller kontaktknottror genom att genomföringar utformas genom det isolerande limmet.
4. Förfarande i enlighet med patentkrav 3, k ä n n e t e c k n a t av att de elektriska kontakteina mellan komponentens (6) kontaktomräden (7) och ledarmönsterskiktet (14) 5 bildas efiter att ledarskiktet (4) fästs med hjälp av isoleringsmaterialet (1) vid bottenytan (2).
5. Förfarande i enlighet med nägot av patentkraven 1 - 4, k ä n n e t e c k n a t av att ledarmaterialet utformas i kontaktöppningama medelst ett kemiskt ocli/eller elektro-kemiskt metalliseringsförfarande. 10
6. Förfarande i enlighet med nägot av patentkraven 1-5, kännetecknat avatt dä komponenten (6) fästs omfattar ledarskiktet (4) för inpassning utformade öppningar (-’)·
7. Förfarande i enlighet med nägot av patentkraven 1-5, kännetecknat av att ... dä komponenten (6) fästs omfattar ledarskiktet (4) kontaktöppningar (17) vid « » · • · · / . 15 komponentens kontaktomräden (7).
• · · * · · *·· · • · · * · ***, 8. Förfarande i enlighet med nägot av patentkraven 1 - 7, k ä n n e t e c k n a t av att • * . dä komponenten (6) fasts omfattar ledarskiktet (4) öppningar för utformning av ·*· *1" genomföringama.
• · • * • · · . . 9. Förfarande i enlighet med nägot av patentkraven 1-8, kännetecknat av att • · · • · · 20 bottenytan (2) omfattar inpassningsmärken (39) för inpassning av det kretskortsskikt • · ]·’ som skall tillverkas i förhällande tili bottenytan (2).
« · • · · * · ^ ’···' 10. Förfarande i enlighet med nägot av patentkraven 1-9, kännetecknat av att ί,·,: dä isoleringsmaterialskiktet (1) bildas tillförs mellan bottenytan (2) och ledarskiktets (4) • · · :...· första yta ätminstone en isoleringsmaterialskiva (1, 11), som ätminstone delvis är 25 ohärdad. 117812 16
11. Förfarande i enlighet med patentkrav 10, k ä n n e t e c k n a t av att dä isoleringsmaterialskiktet (1) bildas omfattar isoleringsmaterialskivan (1, 11) för inpassning utformade öppningar (13, 33).
12. Förfarande i enlighet med nägot av patentkraven 1-11, kännetecknat av att 5 ledarskiktet (4) fasts vid bottenytan (2) med hjälp av ett isoleringsmaterial (1) pä sä sätt, att ett enhetligt isoleringsmaterialskikt (1), som bestär av ett isoleringsmaterial, bildas mellan ledarskiktet och bottenytan (2).
13. Förfarande i enlighet med nägot av patentkraven 1-12, kännetecknat av att isoleringsmaterialskiktet (1) mellan ledarskiktet (4) och bottenytan (2) bildas efter att 10 komponenten (6) lasts, och av ledarskiktet (4) bildas ledarmönster (14) efter att isoleringsmaterialskiktet (1) bildats.
14. Förfarande i enlighet med nägot av patentkraven 1-13, kännetecknat av att isoleringsmaterialskiktet (1) bildas pä sä sätt, att isoleringsmaterialet omger komponenten (6) och bringas i kontakt med komponentens (6) yta. »i* * * 4 » · · , 15
15. Förfarande i enlighet med nägot av patentkraven 1-14, kännetecknat av att • · · * * · i kretskortsskiktet anordnas ett flertal komponenter (6) och komponentema ansluts * 4 elektriskt tili en funktionell enhet med hjälp av ledarmönster (14) i ett eller flera 4 · . kretskortsskikt. • Φ · ···* *44 • * * *
16. Förfarande i enlighet med nägot av patentkraven 1-15, kännetecknat av att • S 20 bottenytan (2) utgörs av bägformig yta. 4 * 4 * · · ♦ • > * * 4 * 4 T
17. Förfarande i enlighet med nägot av patentkraven 1-16, kännetecknat av att * · • · • medelst förfarandet tillverkas ätminstone tvä pä varandra belägna kretskortsskikt pä sä 4 * *···* sätt, att pä bottenytan (2) tillverkas ett första kretskortsskikt och pä dettas yta i tur och * :„V ordning vaije päföljande kretskortsskikt under det att föregäende kretskortsskikt *44' 25 fungerar som bottenskikt.
Priority Applications (9)
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FI20041059A FI117812B (sv) | 2004-08-05 | 2004-08-05 | Tillverkning av ett skikt innehållande en komponent |
US11/659,190 US7673387B2 (en) | 2004-08-05 | 2005-08-04 | Manufacture of a layer including a component |
PCT/FI2005/000352 WO2006013230A2 (en) | 2004-08-05 | 2005-08-04 | Manufacture of a layer including a component |
AT0932705A AT503718B1 (de) | 2004-08-05 | 2005-08-04 | Herstellung einer eine komponente umfassenden schicht |
KR1020077005242A KR20070041774A (ko) | 2004-08-05 | 2005-08-04 | 부품을 포함한 층의 제조 |
JP2007524358A JP4630333B2 (ja) | 2004-08-05 | 2005-08-04 | 基板表面上に回路基板層を形成する方法 |
CNB2005800263538A CN100543983C (zh) | 2004-08-05 | 2005-08-04 | 在基底表面上制造电路板层的方法 |
CN200910164685A CN101686612A (zh) | 2004-08-05 | 2005-08-04 | 制造包括部件的层 |
US12/702,653 US8487194B2 (en) | 2004-08-05 | 2010-02-09 | Circuit board including an embedded component |
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FI20041059 | 2004-08-05 | ||
FI20041059A FI117812B (sv) | 2004-08-05 | 2004-08-05 | Tillverkning av ett skikt innehållande en komponent |
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FI20041059A0 FI20041059A0 (sv) | 2004-08-05 |
FI20041059A FI20041059A (sv) | 2006-02-06 |
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FI20041059A FI117812B (sv) | 2004-08-05 | 2004-08-05 | Tillverkning av ett skikt innehållande en komponent |
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JP (1) | JP4630333B2 (sv) |
KR (1) | KR20070041774A (sv) |
CN (2) | CN100543983C (sv) |
AT (1) | AT503718B1 (sv) |
FI (1) | FI117812B (sv) |
WO (1) | WO2006013230A2 (sv) |
Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FI20031341A (sv) | 2003-09-18 | 2005-03-19 | Imbera Electronics Oy | Förfarande för tillverkning av en elektronikmodul |
FI117814B (sv) * | 2004-06-15 | 2007-02-28 | Imbera Electronics Oy | Förfarande för tillverkning av en elektronikmodul |
FI117369B (sv) * | 2004-11-26 | 2006-09-15 | Imbera Electronics Oy | Förfarande för tillverkning av en elektronikmodul |
FI119714B (sv) | 2005-06-16 | 2009-02-13 | Imbera Electronics Oy | Kretskortskonstruktion och förfarande för tillverkning av kretskortskonstruktion |
FI122128B (sv) * | 2005-06-16 | 2011-08-31 | Imbera Electronics Oy | Förfarande för tillverkning av kretskortskonstruktion |
WO2006134220A1 (en) | 2005-06-16 | 2006-12-21 | Imbera Electronics Oy | Method for manufacturing a circuit board structure, and a circuit board structure |
WO2007135737A1 (ja) | 2006-05-24 | 2007-11-29 | Dai Nippon Printing Co., Ltd. | 部品内蔵配線板、部品内蔵配線板の製造方法 |
US9953910B2 (en) | 2007-06-21 | 2018-04-24 | General Electric Company | Demountable interconnect structure |
US9610758B2 (en) | 2007-06-21 | 2017-04-04 | General Electric Company | Method of making demountable interconnect structure |
WO2009001621A1 (ja) * | 2007-06-26 | 2008-12-31 | Murata Manufacturing Co., Ltd. | 部品内蔵基板の製造方法 |
CN101472399B (zh) * | 2007-12-26 | 2011-09-21 | 欣兴电子股份有限公司 | 内埋式线路板的制作方法 |
US8259454B2 (en) | 2008-04-14 | 2012-09-04 | General Electric Company | Interconnect structure including hybrid frame panel |
US8264085B2 (en) | 2008-05-05 | 2012-09-11 | Infineon Technologies Ag | Semiconductor device package interconnections |
KR101048515B1 (ko) * | 2008-10-15 | 2011-07-12 | 삼성전기주식회사 | 전자 소자 내장 인쇄회로기판 및 그 제조 방법 |
US8124449B2 (en) | 2008-12-02 | 2012-02-28 | Infineon Technologies Ag | Device including a semiconductor chip and metal foils |
FI20095110A0 (sv) | 2009-02-06 | 2009-02-06 | Imbera Electronics Oy | Elektronisk modul med EMI-skydd |
CN102332408B (zh) * | 2010-07-13 | 2015-05-13 | 矽品精密工业股份有限公司 | 芯片尺寸封装件及其制法 |
US8735735B2 (en) | 2010-07-23 | 2014-05-27 | Ge Embedded Electronics Oy | Electronic module with embedded jumper conductor |
AT12737U1 (de) * | 2010-09-17 | 2012-10-15 | Austria Tech & System Tech | Verfahren zum herstellen einer aus mehreren leiterplattenbereichen bestehenden leiterplatte sowie leiterplatte |
TWI462194B (zh) * | 2011-08-25 | 2014-11-21 | Chipmos Technologies Inc | 半導體封裝結構及其製作方法 |
JP2013211519A (ja) * | 2012-02-29 | 2013-10-10 | Ngk Spark Plug Co Ltd | 多層配線基板の製造方法 |
AT513047B1 (de) * | 2012-07-02 | 2014-01-15 | Austria Tech & System Tech | Verfahren zum Einbetten zumindest eines Bauteils in eine Leiterplatte |
TWI463634B (zh) * | 2012-08-29 | 2014-12-01 | Macronix Int Co Ltd | 晶片堆疊結構及其製造方法 |
US8860202B2 (en) * | 2012-08-29 | 2014-10-14 | Macronix International Co., Ltd. | Chip stack structure and manufacturing method thereof |
JP6103054B2 (ja) * | 2013-06-18 | 2017-03-29 | 株式会社村田製作所 | 樹脂多層基板の製造方法 |
US10219384B2 (en) | 2013-11-27 | 2019-02-26 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Circuit board structure |
AT515101B1 (de) | 2013-12-12 | 2015-06-15 | Austria Tech & System Tech | Verfahren zum Einbetten einer Komponente in eine Leiterplatte |
AT515447B1 (de) | 2014-02-27 | 2019-10-15 | At & S Austria Tech & Systemtechnik Ag | Verfahren zum Kontaktieren eines in eine Leiterplatte eingebetteten Bauelements sowie Leiterplatte |
US11523520B2 (en) | 2014-02-27 | 2022-12-06 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Method for making contact with a component embedded in a printed circuit board |
US10178755B2 (en) * | 2017-05-09 | 2019-01-08 | Unimicron Technology Corp. | Circuit board stacked structure and method for forming the same |
KR102175825B1 (ko) * | 2018-11-26 | 2020-11-06 | 엘비세미콘 주식회사 | 반도체 패키지의 제조방법 |
CN111010808B (zh) * | 2019-12-31 | 2022-05-13 | 生益电子股份有限公司 | 一种pcb的制作方法 |
CN113498633B (zh) * | 2020-01-21 | 2023-09-15 | 鹏鼎控股(深圳)股份有限公司 | 内埋电子元件的电路板及制作方法 |
WO2022209319A1 (ja) * | 2021-04-02 | 2022-10-06 | 株式会社村田製作所 | 配線基板及びモジュール |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4246595A (en) * | 1977-03-08 | 1981-01-20 | Matsushita Electric Industrial Co., Ltd. | Electronics circuit device and method of making the same |
JPH0744320B2 (ja) * | 1989-10-20 | 1995-05-15 | 松下電器産業株式会社 | 樹脂回路基板及びその製造方法 |
JP3094481B2 (ja) * | 1991-03-13 | 2000-10-03 | 松下電器産業株式会社 | 電子回路装置とその製造方法 |
US5353498A (en) * | 1993-02-08 | 1994-10-11 | General Electric Company | Method for fabricating an integrated circuit module |
JPH11135951A (ja) * | 1997-10-30 | 1999-05-21 | Kyocera Corp | 多層配線基板 |
JP4606685B2 (ja) * | 1997-11-25 | 2011-01-05 | パナソニック株式会社 | 回路部品内蔵モジュール |
US6038133A (en) * | 1997-11-25 | 2000-03-14 | Matsushita Electric Industrial Co., Ltd. | Circuit component built-in module and method for producing the same |
JP3619395B2 (ja) * | 1999-07-30 | 2005-02-09 | 京セラ株式会社 | 半導体素子内蔵配線基板およびその製造方法 |
US6284564B1 (en) * | 1999-09-20 | 2001-09-04 | Lockheed Martin Corp. | HDI chip attachment method for reduced processing |
US6271469B1 (en) * | 1999-11-12 | 2001-08-07 | Intel Corporation | Direct build-up layer on an encapsulated die package |
US6154366A (en) * | 1999-11-23 | 2000-11-28 | Intel Corporation | Structures and processes for fabricating moisture resistant chip-on-flex packages |
JP2001156457A (ja) * | 1999-11-30 | 2001-06-08 | Taiyo Yuden Co Ltd | 電子回路装置の製造方法 |
US6475877B1 (en) * | 1999-12-22 | 2002-11-05 | General Electric Company | Method for aligning die to interconnect metal on flex substrate |
US6876072B1 (en) * | 2000-10-13 | 2005-04-05 | Bridge Semiconductor Corporation | Semiconductor chip assembly with chip in substrate cavity |
TW511405B (en) * | 2000-12-27 | 2002-11-21 | Matsushita Electric Ind Co Ltd | Device built-in module and manufacturing method thereof |
TW511415B (en) * | 2001-01-19 | 2002-11-21 | Matsushita Electric Ind Co Ltd | Component built-in module and its manufacturing method |
JP2003037205A (ja) * | 2001-07-23 | 2003-02-07 | Sony Corp | Icチップ内蔵多層基板及びその製造方法 |
JP2003133693A (ja) * | 2001-10-29 | 2003-05-09 | Denso Corp | 配線形成方法、回路形成方法、配線形成装置、回路形成装置 |
JP3910045B2 (ja) * | 2001-11-05 | 2007-04-25 | シャープ株式会社 | 電子部品内装配線板の製造方法 |
FI119215B (sv) * | 2002-01-31 | 2008-08-29 | Imbera Electronics Oy | Förfarande för insättning av en komponent i ett basmaterial och elektronikmodul |
FI115285B (sv) * | 2002-01-31 | 2005-03-31 | Imbera Electronics Oy | Förfarande för insänkning av en komponent i ett basmaterial och för bildning av en kontakt |
US6701614B2 (en) * | 2002-02-15 | 2004-03-09 | Advanced Semiconductor Engineering Inc. | Method for making a build-up package of a semiconductor |
JP2003249763A (ja) * | 2002-02-25 | 2003-09-05 | Fujitsu Ltd | 多層配線基板及びその製造方法 |
JP4288912B2 (ja) * | 2002-08-08 | 2009-07-01 | 日立化成工業株式会社 | 配線板、半導体パッケージ用基板、半導体パッケージ及びそれらの製造方法 |
JP2004146634A (ja) | 2002-10-25 | 2004-05-20 | Murata Mfg Co Ltd | 樹脂基板の製造方法、および樹脂多層基板の製造方法 |
JP4489411B2 (ja) * | 2003-01-23 | 2010-06-23 | 新光電気工業株式会社 | 電子部品実装構造の製造方法 |
FI115601B (sv) * | 2003-04-01 | 2005-05-31 | Imbera Electronics Oy | Förfarande för tillverkning av en elektronikmodul och en elektronikmodul |
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- 2004-08-05 FI FI20041059A patent/FI117812B/sv active IP Right Grant
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2005
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- 2005-08-04 AT AT0932705A patent/AT503718B1/de active
- 2005-08-04 JP JP2007524358A patent/JP4630333B2/ja active Active
- 2005-08-04 CN CNB2005800263538A patent/CN100543983C/zh active Active
- 2005-08-04 CN CN200910164685A patent/CN101686612A/zh active Pending
- 2005-08-04 US US11/659,190 patent/US7673387B2/en active Active
Also Published As
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AT503718A5 (de) | 2009-04-15 |
KR20070041774A (ko) | 2007-04-19 |
FI20041059A (sv) | 2006-02-06 |
AT503718B1 (de) | 2009-06-15 |
AT503718A2 (de) | 2007-12-15 |
CN101686612A (zh) | 2010-03-31 |
WO2006013230A2 (en) | 2006-02-09 |
US7673387B2 (en) | 2010-03-09 |
CN101027775A (zh) | 2007-08-29 |
JP4630333B2 (ja) | 2011-02-09 |
WO2006013230A3 (en) | 2006-05-11 |
CN100543983C (zh) | 2009-09-23 |
JP2008509549A (ja) | 2008-03-27 |
FI20041059A0 (sv) | 2004-08-05 |
US20080295326A1 (en) | 2008-12-04 |
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