JP2008509549A - 素子を含む層の形成 - Google Patents
素子を含む層の形成 Download PDFInfo
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- JP2008509549A JP2008509549A JP2007524358A JP2007524358A JP2008509549A JP 2008509549 A JP2008509549 A JP 2008509549A JP 2007524358 A JP2007524358 A JP 2007524358A JP 2007524358 A JP2007524358 A JP 2007524358A JP 2008509549 A JP2008509549 A JP 2008509549A
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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Abstract
Description
Claims (19)
- 基板表面(2)上に回路基板層を形成する方法であって、前記基板表面(2)が導体パターン(19)を有し、前記回路基板層が、導体パターン層(14)と、絶縁材料層(1)と、前記絶縁材料層(1)内にある少なくとも一つの素子(6)とを具える方法において、
導体層(4)を取り出し、前記導体層の第1の表面の側で、前記少なくとも一つの素子(6)を前記導体層(4)に取り付け、
前記導体層(4)を前記基板表面(2)に対して位置決めし、前記基板表面(2)に対向する前記導体層(4)の第1の表面の側で、前記導体層を、絶縁材料(1)を用いて前記基板表面(2)に取り付けて、前記少なくとも一つの素子(6)が配置された前記絶縁材料層(1)を、前記導体層(4)と前記基板表面(2)との間に形成し、
前記素子(6)のコンタクトエリア(7)の位置にコンタクト開口(17)を形成するとともに前記コンタクト開口(17)に導電材料を形成することによって、前記素子(6)のコンタクトエリア(7)と前記導体層(4)との間の電気的なコンタクトを形成し、
前記導体層(4)をパターニングして導電パターン層(14)を形成し、
前記導電パターン層(14)と前記基板表面(2)の前記導体パターン(19)との間に少なくとも一つのビアを形成することを特徴とする方法。 - 請求項1記載の方法において、前記基板表面(2)を前記回路基板の表面とすることを特徴とする方法。
- 請求項1又は2記載の方法において、前記素子(6)、例えばマイクロ回路を、絶縁性の接着剤(5)を用いて前記導体層(4)に取り付け、取付後、前記絶縁性の接着剤によりビアを形成することによって、前記導体層と前記コンタクトエリア又はコンタクトバンプとの間の電気的なコンタクトを形成することを特徴とする方法。
- 請求項3記載の方法において、前記導体層(4)を前記絶縁材料(1)を用いて前記基板表面(2)に取り付けた後、前記素子(6)の前記コンタクトエリア(7)と前記導体層(14)との間に電気的なコンタクトを形成することを特徴とする方法。
- 請求項1から4のうちのいずれかに記載の方法において、化学的及び/又は電気化学的なメタライゼーション方法を用いて前記コンタクト開口に前記導電材料を形成することを特徴とする方法。
- 請求項1から5のうちのいずれかに記載の方法において、前記素子(6)を取り付けるとき、前記導体層(4)が、位置決め用の開口(3)を有することを特徴とする方法。
- 請求項1から5のうちのいずれかに記載の方法において、前記素子(6)を取り付けるとき、前記導体層(4)が、前記素子のコンタクトエリアの位置に開口(3)を有することを特徴とする方法。
- 請求項1から7のうちのいずれかに記載の方法において、前記素子(6)を取り付けるとき、前記導体層(4)が、ビア形成用の開口(3)を有することを特徴とする方法。
- 請求項1から8のうちのいずれかに記載の方法において、前記基板表面(2)が、形成される回路基板層を前記基板表面(2)に対して位置決めする位置決めマーク(39)を有することを特徴とする方法。
- 請求項1から9のうちのいずれかに記載の方法において、前記絶縁材料層(1)を形成するとき、少なくとも部分的に硬化していない少なくとも一つの絶縁材料シート(1)を、前記基板表面(2)と前記導体層(4)の第1の表面との間に配置することを特徴とする方法。
- 請求項10記載の方法において、前記絶縁材料層(1)を形成するとき、前記絶縁材料シート(1,11)が、位置決め用の開口(13,33)を有することを特徴とする方法。
- 請求項1から11のうちのいずれかに記載の方法において、単一の絶縁材料から構成される一体となった絶縁材料層(1)を、前記導体層と前記基板表面(2)との間に形成するように、前記導体層(4)を、一つの絶縁材料を用いて前記基板表面(2)に取り付けることを特徴とする方法。
- 請求項1から12のうちのいずれかに記載の方法において、前記導体層(4)と前記基板表面(2)との間の絶縁材料層(1)を、前記素子(6)の取付後に形成し、前記導体パターン(14)を、前記絶縁材料層(1)の形成後に前記導体層(4)から形成することを特徴とする方法。
- 請求項1から13のうちのいずれかに記載の方法において、前記絶縁材料が前記素子(6)を包囲するとともに前記素子(6)の表面に接触するように前記絶縁材料層(1)を形成することを特徴とする方法。
- 請求項1から14のうちのいずれかに記載の方法において、複数の素子を前記回路基板層に配置するとともに、一つ以上の回路基板層の導体パターン(14)を用いて電気的な機能を果たすためにこれらの素子を組み合わせることを特徴とする方法。
- 請求項1から15のうちのいずれかに記載の方法において、前記基板表面(2)を曲面とすることを特徴とする方法。
- 請求項1から16のうちのいずれかに記載の方法において、最初に、第1の回路基板層を前記基板表面(2)の上に形成し、次に、前記第1の回路基板層の表面に次の回路基板層を形成し、先行する回路基板層が前記基板表面としての役割を果たすように、前記方法を、重なり合う少なくとも二つの回路基板層を形成するために用いることを特徴とする方法。
- 請求項1から17のうちのいずれかに記載の方法において、同一の処理工程で前記コンタクト開口(17)及び前記ビア(20)に導電材料を充填することを特徴とする方法。
- 請求項1から18のうちのいずれかに記載の方法において、化学的及び/又は電気化学的なメタライゼーション方法を用いて前記ビア(20)に導電材料を形成することを特徴とする方法。
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CN100543983C (zh) | 2009-09-23 |
FI20041059A0 (fi) | 2004-08-05 |
US20080295326A1 (en) | 2008-12-04 |
JP4630333B2 (ja) | 2011-02-09 |
CN101027775A (zh) | 2007-08-29 |
WO2006013230A3 (en) | 2006-05-11 |
US7673387B2 (en) | 2010-03-09 |
CN101686612A (zh) | 2010-03-31 |
FI20041059A (fi) | 2006-02-06 |
WO2006013230A2 (en) | 2006-02-09 |
AT503718A2 (de) | 2007-12-15 |
AT503718A5 (de) | 2009-04-15 |
AT503718B1 (de) | 2009-06-15 |
FI117812B (fi) | 2007-02-28 |
KR20070041774A (ko) | 2007-04-19 |
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