CN101027775A - 制造包括部件的层 - Google Patents

制造包括部件的层 Download PDF

Info

Publication number
CN101027775A
CN101027775A CNA2005800263538A CN200580026353A CN101027775A CN 101027775 A CN101027775 A CN 101027775A CN A2005800263538 A CNA2005800263538 A CN A2005800263538A CN 200580026353 A CN200580026353 A CN 200580026353A CN 101027775 A CN101027775 A CN 101027775A
Authority
CN
China
Prior art keywords
layer
conductor layer
substrate surface
parts
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2005800263538A
Other languages
English (en)
Other versions
CN100543983C (zh
Inventor
R·托米南
P·帕尔姆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Imberatec Co., Ltd
Original Assignee
Imbera Electronics Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imbera Electronics Oy filed Critical Imbera Electronics Oy
Publication of CN101027775A publication Critical patent/CN101027775A/zh
Application granted granted Critical
Publication of CN100543983C publication Critical patent/CN100543983C/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/83132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

一种在基底表面(2)上制造电路板层的方法，其中基底表面(2)包括导体图案(19)。将要制造的电路板层包括导体图案层(14)、绝缘材料层(1)和至少在绝缘材料层(1)内部的一个部件(6)。根据本发明，部件(6)连接到导体层(4)，导体层(4)相对于借助于绝缘材料(1)连接到基底表面(2)的基底表面(2)对准。绝缘材料层(1)由此在导体层(4)和其上具有所述至少一个部件(6)的基底表面(2)之间形成。电接触以接触开口(17)在部件(6)的接触区域(7)处形成和导电材料形成在接触开口(17)的方式形成在部件(6)的接触区域(7)和导体层(4)之间。构图导体层(4)以形成导体图案层(14)，和在导体图案层(14)和基底表面(2)的导体图案(19)之间形成至少一个通孔(20)。

Description

制造包括部件的层
本发明涉及制造包含部件的层的方法。
例如，当制造多层电路板或其它类似的电子模块时，制造包含部件的层。特别地，本发明涉及的方法设法制造包含一个或多个通过在电子模块中制造的导体结构电连接到层外部电路、或彼此电连接的部件。在本文中，这样的层成为电路板层。
专利公开US 6,489,685公开了一种方法，其中部件在制造电路板期间放置在电路板内部。在本方法中，在支撑基底的顶部制造导体图案，部件连接到制造的导体图案上。在此之后，在其表面上可以具有用作电路板基础材料的附加导体图案层的绝缘层，形成在导体图案和部件的顶部。在产生绝缘层后，支撑基底从结构脱离。
专利公开US 6,038,133不仅仅公开了与上述类似的方法，而且公开了第二种方法，其中部件在电路板生产期间放置在电路板内部。在第二方法中，使用导电粘结剂把部件附着到铜箔上，且在这之后，在铜箔和部件的顶部形成用作电路板的基础材料的绝缘层。在形成绝缘层后，导体图案由铜箔形成。
利用导电粘结剂制造的接触的电性能不是特别好，因此专利公开US6,489,685和US 6,038,133公开的方法不适用于许多例如电性能起决定性的应用。
本发明想要建立一种在包括导体图案的基底表面上制造电路板层的新方法。具体地，该新方法能够制造对于接触块或部件的其它接触区域是可靠的且具有高质量电学性能的接触。
本发明基于把要制造的电路板的部件连接到导体层，在此阶段导体层还未被构图以形成导体图案层。通过部件面对基底表面且部件位于绝缘材料内部的方式，导体层相对于基底表面对准且利用绝缘材料连接到基底表面。通过在部件接触区域的位置处形成接触开口且在接触开口中形成导体材料的方式，在部件的接触区域和导体图案层之间形成电接触。优选使用化学和/或电化学金属化方法制造导体材料。之后，构图导体层以形成导体图案层，以及在导体图案层和基底表面的导体图案之间形成必要的通孔。
更具体地，在权利要求1的特征部分阐述了根据本发明方法的特征。
通过本发明得到了相当多的优点。
使用根据本发明的方法，可以在电路板或其它电子模块表面上添加需要数量的电路板层。使用根据本发明的方法，电路板层也可以添加到包括导体图案的其它表面上。
使用根据本发明的方法，可以制造与接触块或部件的其它接触区域接触的高质量和高可靠性的电接触。这基于当制造接触时，可以使用例如在电路板工业中已知且可靠的一些微通孔方法的事实。可以例如以例如在金属生长在接触开口中之后，借助于激光或等离子体首先清洗接触区域，使用化学和/或电化学金属化方法的方式制造接触。
在下文中，将利用示例和参考附图说明本发明。
图1示出了在本发明的一个实施例中在电路板层的制造中用作初始材料的导体膜。
图2示出了根据一个实施例的中间阶段，其中局部粘结剂层添加到图1的导体层的顶部。
图3示出了根据一个实施例的中间阶段，其中部件粘结到图2的粘结剂层。
图4示出了将图3上下翻转的工件。
图5示出了根据一个实施例的中间阶段，其中图4的工件将要利用绝缘材料层连接到基底表面。
图6示出了根据一个实施例的中间阶段，其中图4的工件利用绝缘材料层连接到基底表面。
图7示出了根据一个实施例的中间阶段，其中除去了导体层的支撑层且其中形成接触开口以形成与部件接触的接触和形成用于通孔的孔。
图8示出了根据一个实施例的中间阶段，其中在图7的接触开口、通孔和导体层的顶上形成导体材料。
图9示出了根据一个实施例的工件，其中构图在图8中示出的工件表面上的导体层以形成导体图案层。
图10示出了根据一个实施例的电子模块，其中在基底表面上彼此的顶部上形成了三个电路板层。
在根据实施例的方法中，可以从例如可以是金属层的裸导体层4开始制造。铜箔(Cu)是适用于制造导体层4的一种材料。如果选择用于工艺的导体膜4非常薄，或由于其他原因导体膜不是机械耐久的，推荐利用支撑层12(图1)支撑导体膜4。然后可以以工艺从制造支撑层12开始的方式继续。支撑层12可以例如是导电材料，例如铝(Al)、钢或铜，或者是绝缘材料例如聚合物。在支撑层12的另一边，可以例如通过使用在电路板工业中已知的制造方法制造未构图的导体层4。例如，通过在支撑层12的表面上层叠铜箔(Cu)制造导体层。可选择地，可以在导体层4的表面上制造支撑层12。导体膜4也可以是刨光的金属膜，或一些包含几层或几种材料的其它膜。
制造也可以例如从第一表面上具有绝缘材料层1(未示出)的导体层4开始。在那种情况下，第一表面是密封在绝缘层1内部的部件连接的表面。在某些实施例中，在绝缘层1的对面表面具有另一个导体层4。如果在实施例中使用了支撑层12，支撑层12将位于导体层4的相对表面上，即在第一表面上。在那种情况下，为了要嵌入的部件，在绝缘材料层1上形成了多个孔和凹槽。也可以在绝缘材料层1之前形成凹槽，且导体层4彼此连接，或者在连接之后在绝缘材料层1之前形成凹槽。在凹槽制造中，可以使用在电路板工业中已知的机械加工方法，例如可以使用铣削或激光钻孔。
在第一实施例中，在导体层4中将被连接(与图3和图7对比)的部件6的接触区域7的位置形成接触开口(在图中未示出)。因此在部件6连接到导体层之前，形成接触开口。可以例如通过借助激光的钻孔形成接触开口。接触开口的相互位置根据部件接触区域7的相互位置选择，每组接触开口的位置和对准通过部件正确地相对于整个电子模块定位的方式选择，在更传统的实施例中，在形成每个电接触的过程中，为每个接触区域7形成一个接触开口，但是也存在对单个接触区域7形成几个接触开口这样的实施例。要形成的接触开口的表面面积可以或多或少地与相应接触区域7的表面面积一样大。当然也可以选择使接触开口的表面面积小于、或在某些实施例中稍微大于相应接触区域7的表面面积。接触开口的形状可以例如是圆形、椭圆形、卵形、有角的或直线形。
可以从导体层的第一或第二表面的方向钻孔形成接触开口。如果在实施例中使用在导体层的第二侧面上的支撑层12，因为被钻的开口不需要完全穿过支撑层12，可以优选从第一表面的方向钻出接触开口。在这样的实施例中，当除去支撑层12时，随后形成接触开口。也可以通过减薄由导体层4形成的材料层和通过从支撑层12的方向蚀刻而形成接触开口。导体层4和支撑层12也可以由单材料层形成。然后除去对应于支撑层12的材料层部分并且形成接触开口。接触开口由此穿过整个导体层4延伸。
在第二实施例中，在部件连接之前，接触开口并没有在导体层4中形成，相反只有在部件(图7)连接之后，形成了接触开口17。在这样的实施例中，使用适当的对准标记来对准部件。  在第一和第二实施例中，为了电路板层和在基底表面2上的导体结构的相互对准，在导体层中(图1)形成了对准开口3。在两个实施例中，对准开口可以在部件6连接到导体层之前形成，或在连接之后形成。
在两个实施例中，部件6利用粘结剂(图3)连接到导体层4的表面。为了粘结，在导体层4的连接表面或部件6的连接表面上、或在两个连接表面(图2)上涂抹粘结剂层5。在此之后，部件6可以借助对准标记在用于部件6的位置对准。
部件6的连接表面指的是部件6对着导体层4的表面。部件6的连接表面包括可以形成到部件的电接触的接触区域。接触区域可以是例如在部件6表面上的平面区域，或更通用的接触突起，例如从部件6表面突出的接触块。通常在部件6中至少具有两个接触区域或突起。在复杂的微电子电路中，甚至有非常多的接触区域。
通常优选在连接表面上涂抹足够多的粘结剂以使粘结剂完全填充部件6和导体层4之间的空隙。这样就不需要单独的填料剂。填充部件6和导体层4之间的空隙加强了在部件6和导体层4之间的机械连接，因此得到了机械性能更耐久的结构。没有间隙的完全的粘结剂层还支撑了后来在导体层4中形成的导体图案14，并且会保护后来的工艺阶段中的结构。在第一实施例中，在粘结期间粘结剂还将进入接触开口。
术语粘结剂指部件通过其可以连接到导体层的材料。粘结剂的一个特性是它可以以相对液体的形式或以与表面形状符合的形式，例如以薄膜的形式布置在导体层和/或部件的表面上。粘结剂的第二属性是在涂抹后，以粘结剂能够把部件固定在适当位置(相对于导体层)的方式硬化粘结剂，或可以至少部分硬化，直到部件以其它方式连接到结构。粘结剂的第三属性是其粘结能力，即其能够紧握被粘结表面的能力。
术语粘结指部件和导体层借助于粘结剂的连接。当粘结时，粘结剂放置在部件和导体层之间，并且部件放置在相对于导体层适当的位置，其中粘结剂与部件和导体层接触且至少部分填充部件和导体层之间的间隙。在此之后，以部件通过粘结剂粘结到导体层的方式，将粘结剂硬化(至少部分地)，或粘结剂活性地(actively)硬化(至少部分地)，。在某些实施例中，部件的接触突起可以在粘结期间穿过粘结剂层突出以与导体层接触。
在实施例中使用的粘结剂是例如已填充或未填充的热固性环氧树脂。以所用的粘结剂对导体膜、电路板和部件具有足够粘性的标准选择粘结剂。粘结剂的一个优选属性是合适的热膨胀系数，以使在工艺期间粘结剂的热膨胀与周围材料的热膨胀不会相差太大。选择的粘结剂应当优选具有短的硬化时间，优选最多为几秒。在这段时间内，粘结剂应当至少部分硬化以使粘结剂能够支撑位置上的部件。最后的硬化可能需要更多的时间，最后的硬化甚至可以结合后面的工艺阶段进行。粘结剂还应当能够承受使用的工艺温度，例如加热到100-265℃几次，以及其它的制造工艺应力，例如化学或机械应力。粘结剂的导电性优选为绝缘材料导电性的级别。
选择适当的绝缘材料层1作为电子模块例如电路板的基底材料。可以从适当的聚合物或包含聚合物的材料制造绝缘材料层1。制造绝缘材料层1的材料可以是例如液体或预硬化形式(例如预浸料)。在绝缘材料层1的制造中可以使用玻璃纤维加强片，例如FR5型片的FR4。在制造绝缘材料层1中使用的材料的其它例子是Pl(聚酰胺)、芳族聚酰胺、聚四氟乙烯和特氟纶(R)。代替热固性塑料或与热固性塑料一起，在制造绝缘材料层1中也可以使用热塑性塑料，例如一些适当的LCP(液晶聚合物)。
使用一些适当的方法(图5)，在绝缘材料层1中形成根据粘结到导体层4的部件6的尺寸和相互位置选择的凹槽或通孔。凹槽或通孔也可以稍微大于部件6，其中绝缘材料层1相对于导体层4的对准不再是非常关键的。如果在工艺中使用其中具有由部件6形成的通孔的绝缘材料层1，通过使用另一单独的其中没有形成通孔的绝缘材料层11可以得到某些优点。这样的绝缘材料层11可以位于绝缘材料层顶部以覆盖为部件形成的通孔。
在此之后，绝缘材料硬化，以产生基本上统一的绝缘材料层1(图6)。在使用单个绝缘材料层1和使用几个绝缘材料片1、11的两个实施例中，形成基本统一的绝缘材料层1。
如果绝缘材料层1不透明，可以为在基底表面2上的电路板层和导体结构的相互对准在绝缘材料层中形成对准开口13。这个工艺可以在第一和第二实施例中使用。以相对应的方式，当使用绝缘材料层11时，可以在其中形成对准开口33。对准开口13和对准开口33可以根据在基底表面上的对准标记39定位。当绝缘材料层1或绝缘材料层1、11以对准开口13和如果必要，对准开口33放置在与对准标记39相同位置处的方式放置在基底表面2顶部时，导体层4可以通过对准开口3相对于基底表面2精确对准。例如，通过位于对准的整个片的边缘区域中的定位销，可以进行对准。
对准的另一选择是把导体层4通过对准开口3对准和把在基底表面2上的正确位置放置的导体层4固定以把导体层4定位在相对于基底表面2的正确位置。在此之后，至少部分未硬化的绝缘材料片1可以放置于导体层4和基底表面2之间并且这些层挤压在一起。如果，当施压时，导体层4和基底表面2不允许彼此横向移动，导体层4和基底表面2将会达到相对于彼此正确的位置。在这样的实施例中，绝缘材料层1不需要包括对准开口13。当使用第二绝缘材料层11时，将不再需要对应的对准开口33。
在连接层后，在电子模块中形成微通孔，通过这些微通孔在部件6的接触区域和导体层4之间形成电接触。
为了形成通孔，清理在第一实施例中的接触开口17的粘结剂和可能进入开口的其它材料。由于部件粘结到第一侧面，所以上述这一点自然从导体材料4的第二表面方向进行。与清洗接触开口一起，也可以清理部件6的接触区域7，这样会进一步改善用于形成高质量电接触的条件。可以例如使用等离子体技术、化学或利用激光进行清洁。如果接触开口和接触区域已经足够清洁，当然可以省略清洗。
在第二实施例的这个阶段，可以通过导体层4(图7)形成接触开口17。接触开口17例如通过对准开口3对准。接触开口17例如通过激光形成。
与接触开口17的制造或清洁一起，也可以为在导体图案层14和在基底表面2上的导体结构19之间形成的通孔形成孔。
在此之后，如果需要可以检查部件6的对准是否成功。这基于当从导体层4的方向看时，部件6的对准的接触区域7通过接触开口17是可见的。
在第一实施例(如果这是必要的)中已经清洁接触开口之后，或在第二实施例中已经形成接触开口之后，导电材料以在部件6和导体层4之间形成电接触的方式进入接触开口17。以相同的连接，也可以形成到达通孔20的导体。导电材料可以通过利用导电膏填充接触开口而形成。导电材料也可以通过使用一些电路板工业中已知的方法而形成。在这种情况下，通过形成冶金结，例如，通过使用化学或电化学方法生长导电材料，可以形成最好的电接触。这样的方法由此使用在最需要的应用中。另一好的选择是使用化学方法的薄层生长以及使用更经济的电化学方法继续生长。除了这些方法，当然也可以使用一些其它方法，其对于最后结果是有益的。与此同时，也可以增加导体层4的厚度(图8)。
之后，可以构图导体层4以形成导体图案层14(图9)。
当根据第一实施例制造电路板层时，也可以在电路板层的制造中采用本申请人于2003年4月1日申请的、在本专利申请的优先权日还未公开的芬兰专利申请号20030493中公开的制造方法。
当根据第二实施例制造电路板层时，也可以在电路板层的制造中采用本申请人于2004年6月15日申请的、在本专利申请的优先权日还未公开的芬兰专利申请号为20040827的专利申请中公开的制造方法。
上述这些示例说明了一些本发明可以利用的可能的工艺。然而，本发明并不严格局限于上述的第一和第二实施例，相反，考虑到权利要求的全部范围和等价解释，本发明也可以覆盖其它不同的工艺和它们的最终产品。本发明并不是严格的局限于示例描述的结构和方法，对于本领域技术人员很显然本发明的多种应用可以用于制造与本发明描述差别很大的各种电子模块和电路板。附图的部件和电路仅仅通过说明本发明的制造工艺而示出。因此对上述示例的工艺可以作出多种修改，只要不超出本发明的基本思想即可。这些修改可以例如涉及在不同阶段所述的制造技术，或工艺阶段的相互顺序。
上述电路板层制造方法可以通过在彼此顶部形成电路板层的方式重复。以这种方式，可以制造例如图10中示出的包括在彼此电连接的、彼此顶部上的、包含某些部件的电路板层结构。
因此电路板层可以添加到非常不同的基底表面2的顶部。如上述实施例中基底表面2也可以是曲面，由于导体层的弯曲在部件和相关导体层之间的电接触不会损坏。这基于在弯曲导体层之后形成电接触的事实。

Claims (19)

1.一种在基底表面(2)上制造电路板层的方法，其中基底表面(2)包括导体图案(19)，并且电路板层包括导体图案层(14)、绝缘材料层(1)和至少在绝缘材料层(1)内部的一个部件(6)，其特征在于：
采用导体层(4)并且在所述导体层的第一表面的一侧上将所述至少一个部件(6)连接到导体层(4)，
相对于基底表面(2)对准导体层(4)并且通过绝缘材料(1)将导体层连接到基底表面(2)，导体层(4)的第一表面面对基底表面(2)，由此形成了在导体层(4)和其中具有所述至少一个部件(6)的基底表面(2)之间的绝缘材料层(1)，
通过在部件(6)的接触区域(7)的位置处形成接触开口(17)和在接触开口(17)中形成导电材料在部件(6)的接触区域(7)和导体层(4)之间形成电接触，
构图导体层(4)以形成导体图案层(14)，以及
在导体图案层(14)和基底表面(2)的导体图案(19)之间形成至少一个通孔(20)。
2.根据权利要求1的方法，其特征在于基底表面(2)是电路板的表面。
3.根据权利要求1或2的方法，其特征在于在导体层和接触区域或接触凸块之间形成电接触的连接之后，通过绝缘粘结剂形成通孔，利用绝缘粘结剂(5)将部件(6)例如微电路连接到导体层(4)。
4.根据权利要求3的方法，其特征在于在导体层(4)已经通过绝缘材料(1)连接到基底表面(2)之后，在部件(6)的接触区域(7)和导体层(14)之间形成电接触。
5.根据权利要求1-4的任一方法，其特征在于使用化学和/或电化学金属化方法在接触开口中制造导体材料。
6.根据权利要求1-5的任一方法，其特征在于当连接部件(6)时，导体层(4)包括用于对准的开口(3)。
7.根据权利要求1-5的任一方法，其特征在于当连接部件(6)时，导体层(4)包括在部件的接触区域(7)的位置处的接触开口(17)。
8.根据权利要求1-7的任一方法，其特征在于当连接部件(6)时，导体层(4)包括用于形成通孔的开口。
9.根据权利要求1-8的任一方法，其特征在于基底表面(2)包括用于相对于基底表面(2)对准正在制造的电路板的对准标记(39)。
10.根据权利要求1-9的任一方法，其特征在于当形成绝缘材料层(1)时，至少部分未硬化的一个绝缘材料片(1)放置于基底表面(2)和导体层(4)的第一表面之间。
11.根据权利要求10的方法，其特征在于当形成绝缘材料层(1)时，绝缘材料片(1，11)包括用于对准的开口(13，33)。
12.根据权利要求1-11的任一方法，其特征在于以统一的由单个绝缘材料构成的绝缘材料层(1)形成在导体层和基底表面(2)之间的方式，将导体层(4)通过一个绝缘材料(1)连接到基底表面(2)。
13.根据权利要求1-12的任意一个的方法，其特征在于在部件(6)的连接之后，在导体层(4)和基底表面(2)之间形成绝缘材料层(1)，和在形成绝缘材料层(1)之后从导体层(4)形成导体图案(14)。
14.根据权利要求1-13的任意一项的方法，通过以绝缘材料围绕部件(6)和与部件(6)的表面接触的方式形成绝缘材料层(1)。
15.根据权利要求1-14的任意一项的方法，其特征在于放置几个部件在电路板层中，和在一个或多个电路板层的导电图案(14)的辅助下组合部件(6)以形成总体的电功能。
16.根据权利要求1-15的任一方法，其特征在于基底表面(2)是曲面。
17.根据权利要求1-16的任一方法，其特征在于该方法用于以第一电路板层首先在基底表面(2)上制造，然后依次在第一电路板层表面上形成每个下面的电路板层，前一电路板层用作基底表面的方式来制造彼此顶部上的至少两个电路板层。
18.根据权利要求1-17的任一方法，其特征在于利用导电材料在一个和相同的工艺步骤中填充接触开口(17)和通孔(20)。
19.根据权利要求1-18的方法，其特征在于使用化学和/或电化学金属化方法在通孔(20)中形成导电材料。
CNB2005800263538A 2004-08-05 2005-08-04 在基底表面上制造电路板层的方法 Active CN100543983C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI20041059A FI117812B (fi) 2004-08-05 2004-08-05 Komponentin sisältävän kerroksen valmistaminen
FI20041059 2004-08-05

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN200910164685A Division CN101686612A (zh) 2004-08-05 2005-08-04 制造包括部件的层

Publications (2)

Publication Number Publication Date
CN101027775A true CN101027775A (zh) 2007-08-29
CN100543983C CN100543983C (zh) 2009-09-23

Family

ID=32922092

Family Applications (2)

Application Number Title Priority Date Filing Date
CNB2005800263538A Active CN100543983C (zh) 2004-08-05 2005-08-04 在基底表面上制造电路板层的方法
CN200910164685A Pending CN101686612A (zh) 2004-08-05 2005-08-04 制造包括部件的层

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN200910164685A Pending CN101686612A (zh) 2004-08-05 2005-08-04 制造包括部件的层

Country Status (7)

Country Link
US (1) US7673387B2 (zh)
JP (1) JP4630333B2 (zh)
KR (1) KR20070041774A (zh)
CN (2) CN100543983C (zh)
AT (1) AT503718B1 (zh)
FI (1) FI117812B (zh)
WO (1) WO2006013230A2 (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101472399B (zh) * 2007-12-26 2011-09-21 欣兴电子股份有限公司 内埋式线路板的制作方法
CN102332408A (zh) * 2010-07-13 2012-01-25 矽品精密工业股份有限公司 芯片尺寸封装件及其制法
CN103098568A (zh) * 2010-09-17 2013-05-08 At&S奥地利科技及系统技术股份公司 由多个印刷电路板区域组成的印刷电路板及制造方法
CN104509222A (zh) * 2012-07-02 2015-04-08 At&S奥地利科技与系统技术股份公司 用于将至少一个部件嵌入印刷电路板的方法
CN105165129A (zh) * 2013-06-18 2015-12-16 株式会社村田制作所 树脂多层基板的制造方法
CN111010808A (zh) * 2019-12-31 2020-04-14 生益电子股份有限公司 一种pcb的制作方法
WO2021146894A1 (zh) * 2020-01-21 2021-07-29 鹏鼎控股(深圳)股份有限公司 内埋电子元件的电路板及制作方法

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI20031341A (fi) 2003-09-18 2005-03-19 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi
FI117814B (fi) * 2004-06-15 2007-02-28 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi
FI117369B (fi) * 2004-11-26 2006-09-15 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi
FI122128B (fi) * 2005-06-16 2011-08-31 Imbera Electronics Oy Menetelmä piirilevyrakenteen valmistamiseksi
FI119714B (fi) 2005-06-16 2009-02-13 Imbera Electronics Oy Piirilevyrakenne ja menetelmä piirilevyrakenteen valmistamiseksi
JP2008544512A (ja) * 2005-06-16 2008-12-04 イムベラ エレクトロニクス オサケユキチュア 回路基板構造体およびその製造方法
KR20140033245A (ko) 2006-05-24 2014-03-17 다이니폰 인사츠 가부시키가이샤 부품 내장 배선판, 부품 내장 배선판의 제조 방법
US9953910B2 (en) 2007-06-21 2018-04-24 General Electric Company Demountable interconnect structure
US9610758B2 (en) 2007-06-21 2017-04-04 General Electric Company Method of making demountable interconnect structure
CN101690434B (zh) * 2007-06-26 2011-08-17 株式会社村田制作所 元器件内置基板的制造方法
US8259454B2 (en) 2008-04-14 2012-09-04 General Electric Company Interconnect structure including hybrid frame panel
US8264085B2 (en) 2008-05-05 2012-09-11 Infineon Technologies Ag Semiconductor device package interconnections
KR101048515B1 (ko) * 2008-10-15 2011-07-12 삼성전기주식회사 전자 소자 내장 인쇄회로기판 및 그 제조 방법
US8124449B2 (en) 2008-12-02 2012-02-28 Infineon Technologies Ag Device including a semiconductor chip and metal foils
FI20095110A0 (fi) * 2009-02-06 2009-02-06 Imbera Electronics Oy Elektroniikkamoduuli, jossa on EMI-suoja
US8735735B2 (en) 2010-07-23 2014-05-27 Ge Embedded Electronics Oy Electronic module with embedded jumper conductor
TWI462194B (zh) * 2011-08-25 2014-11-21 Chipmos Technologies Inc 半導體封裝結構及其製作方法
JP2013211519A (ja) * 2012-02-29 2013-10-10 Ngk Spark Plug Co Ltd 多層配線基板の製造方法
US8860202B2 (en) * 2012-08-29 2014-10-14 Macronix International Co., Ltd. Chip stack structure and manufacturing method thereof
TWI463634B (zh) * 2012-08-29 2014-12-01 Macronix Int Co Ltd 晶片堆疊結構及其製造方法
EP3075006A1 (de) 2013-11-27 2016-10-05 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Leiterplattenstruktur
AT515101B1 (de) 2013-12-12 2015-06-15 Austria Tech & System Tech Verfahren zum Einbetten einer Komponente in eine Leiterplatte
AT515447B1 (de) 2014-02-27 2019-10-15 At & S Austria Tech & Systemtechnik Ag Verfahren zum Kontaktieren eines in eine Leiterplatte eingebetteten Bauelements sowie Leiterplatte
US11523520B2 (en) 2014-02-27 2022-12-06 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method for making contact with a component embedded in a printed circuit board
US10178755B2 (en) * 2017-05-09 2019-01-08 Unimicron Technology Corp. Circuit board stacked structure and method for forming the same
KR102175825B1 (ko) * 2018-11-26 2020-11-06 엘비세미콘 주식회사 반도체 패키지의 제조방법
WO2022209319A1 (ja) * 2021-04-02 2022-10-06 株式会社村田製作所 配線基板及びモジュール

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4246595A (en) 1977-03-08 1981-01-20 Matsushita Electric Industrial Co., Ltd. Electronics circuit device and method of making the same
JPH0744320B2 (ja) 1989-10-20 1995-05-15 松下電器産業株式会社 樹脂回路基板及びその製造方法
JP3094481B2 (ja) * 1991-03-13 2000-10-03 松下電器産業株式会社 電子回路装置とその製造方法
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
JPH11135951A (ja) * 1997-10-30 1999-05-21 Kyocera Corp 多層配線基板
US6038133A (en) 1997-11-25 2000-03-14 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module and method for producing the same
JP4606685B2 (ja) * 1997-11-25 2011-01-05 パナソニック株式会社 回路部品内蔵モジュール
JP3619395B2 (ja) * 1999-07-30 2005-02-09 京セラ株式会社 半導体素子内蔵配線基板およびその製造方法
US6284564B1 (en) 1999-09-20 2001-09-04 Lockheed Martin Corp. HDI chip attachment method for reduced processing
US6271469B1 (en) 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
US6154366A (en) 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
JP2001156457A (ja) * 1999-11-30 2001-06-08 Taiyo Yuden Co Ltd 電子回路装置の製造方法
US6475877B1 (en) * 1999-12-22 2002-11-05 General Electric Company Method for aligning die to interconnect metal on flex substrate
US6876072B1 (en) 2000-10-13 2005-04-05 Bridge Semiconductor Corporation Semiconductor chip assembly with chip in substrate cavity
TW511405B (en) 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
TW511415B (en) 2001-01-19 2002-11-21 Matsushita Electric Ind Co Ltd Component built-in module and its manufacturing method
JP2003037205A (ja) * 2001-07-23 2003-02-07 Sony Corp Ｉｃチップ内蔵多層基板及びその製造方法
JP2003133693A (ja) * 2001-10-29 2003-05-09 Denso Corp 配線形成方法、回路形成方法、配線形成装置、回路形成装置
JP3910045B2 (ja) * 2001-11-05 2007-04-25 シャープ株式会社 電子部品内装配線板の製造方法
FI119215B (fi) * 2002-01-31 2008-08-29 Imbera Electronics Oy Menetelmä komponentin upottamiseksi alustaan ja elektroniikkamoduuli
FI115285B (fi) * 2002-01-31 2005-03-31 Imbera Electronics Oy Menetelmä komponentin upottamiseksi alustaan ja kontaktin muodostamiseksi
US6701614B2 (en) 2002-02-15 2004-03-09 Advanced Semiconductor Engineering Inc. Method for making a build-up package of a semiconductor
JP2003249763A (ja) 2002-02-25 2003-09-05 Fujitsu Ltd 多層配線基板及びその製造方法
JP4288912B2 (ja) * 2002-08-08 2009-07-01 日立化成工業株式会社 配線板、半導体パッケージ用基板、半導体パッケージ及びそれらの製造方法
JP2004146634A (ja) 2002-10-25 2004-05-20 Murata Mfg Co Ltd 樹脂基板の製造方法、および樹脂多層基板の製造方法
JP4489411B2 (ja) * 2003-01-23 2010-06-23 新光電気工業株式会社 電子部品実装構造の製造方法
FI115601B (fi) 2003-04-01 2005-05-31 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi ja elektroniikkamoduuli

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101472399B (zh) * 2007-12-26 2011-09-21 欣兴电子股份有限公司 内埋式线路板的制作方法
CN102332408B (zh) * 2010-07-13 2015-05-13 矽品精密工业股份有限公司 芯片尺寸封装件及其制法
CN102332408A (zh) * 2010-07-13 2012-01-25 矽品精密工业股份有限公司 芯片尺寸封装件及其制法
CN103098568A (zh) * 2010-09-17 2013-05-08 At&S奥地利科技及系统技术股份公司 由多个印刷电路板区域组成的印刷电路板及制造方法
CN104509222B (zh) * 2012-07-02 2019-01-25 At&S奥地利科技与系统技术股份公司 用于将至少一个部件嵌入印刷电路板的方法
CN104509222A (zh) * 2012-07-02 2015-04-08 At&S奥地利科技与系统技术股份公司 用于将至少一个部件嵌入印刷电路板的方法
CN105165129A (zh) * 2013-06-18 2015-12-16 株式会社村田制作所 树脂多层基板的制造方法
CN111010808A (zh) * 2019-12-31 2020-04-14 生益电子股份有限公司 一种pcb的制作方法
CN111010808B (zh) * 2019-12-31 2022-05-13 生益电子股份有限公司 一种pcb的制作方法
WO2021146894A1 (zh) * 2020-01-21 2021-07-29 鹏鼎控股(深圳)股份有限公司 内埋电子元件的电路板及制作方法
CN113498633A (zh) * 2020-01-21 2021-10-12 鹏鼎控股(深圳)股份有限公司 内埋电子元件的电路板及制作方法
CN113498633B (zh) * 2020-01-21 2023-09-15 鹏鼎控股(深圳)股份有限公司 内埋电子元件的电路板及制作方法
US11778752B2 (en) 2020-01-21 2023-10-03 Avary Holding (Shenzhen) Co., Limited. Circuit board with embedded electronic component and method for manufacturing the same

Also Published As

Publication number Publication date
CN100543983C (zh) 2009-09-23
US7673387B2 (en) 2010-03-09
AT503718A5 (de) 2009-04-15
US20080295326A1 (en) 2008-12-04
WO2006013230A3 (en) 2006-05-11
KR20070041774A (ko) 2007-04-19
WO2006013230A2 (en) 2006-02-09
AT503718B1 (de) 2009-06-15
FI117812B (fi) 2007-02-28
FI20041059A (fi) 2006-02-06
AT503718A2 (de) 2007-12-15
FI20041059A0 (fi) 2004-08-05
JP4630333B2 (ja) 2011-02-09
CN101686612A (zh) 2010-03-31
JP2008509549A (ja) 2008-03-27

Similar Documents

Publication Publication Date Title
CN100543983C (zh) 在基底表面上制造电路板层的方法
JP5064210B2 (ja) 電子モジュール及びその製造方法
CN101010994B (zh) 制造电子模块的方法
US20210329788A1 (en) Method for manufacturing an electronic module and electronic module
CN101065843B (zh) 制造电子模块的方法
KR100687976B1 (ko) 전자 모듈 및 그의 제조 방법
CN1812088B (zh) 多层构造半导体微型组件及制造方法
KR101012029B1 (ko) 반도체 장치 내장 다층 배선 기판 및 그 제조 방법
US8222539B2 (en) Wiring board and method for manufacturing the same
US20060218782A1 (en) Method for manufacturing an electronic module
JP2007535156A (ja) 埋込み構成要素からの熱伝導
CN101770959A (zh) 刚柔结合的组件和制造方法
KR20130115323A (ko) 회로화되고 유연한 유기성 기판에 고밀도 다중레벨 박막을 전사하고 전기적으로 결합하는 방법 및 연관된 디바이스
CN109314101A (zh) 模块以及用于制造多种模块的方法
KR101495459B1 (ko) 액정 폴리머 솔더 마스크를 갖는 전자 디바이스 제조 방법 및 관련된 디바이스
JP6511851B2 (ja) 多層回路基板、半導体装置、多層回路基板の製造方法
US20080192453A1 (en) Multilayer interconnection substrate and manufacturing method therefor
EP4095898A1 (en) Thermally improved pcb for semiconductor power die connected by via technique and assembly using such pcb
US7939940B2 (en) Multilayer chip scale package
KR20200096285A (ko) 전력 부품과 회로 캐리어의 금속 층 간의 열 전도성 연결부 형성 방법
CN116918063A (zh) 具有止裂结构的电子器件
JP2009124004A (ja) 電子回路モジュール

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CP03 Change of name, title or address

Address after: Helsinki

Patentee after: GE Embedded Electronics OY

Address before: Espoo, Finland

Patentee before: IMBERA ELECTRONICS OY

CP03 Change of name, title or address
TR01 Transfer of patent right

Effective date of registration: 20200908

Address after: Virginia

Patentee after: Imberatec Co., Ltd

Address before: Helsinki

Patentee before: GE Embedded Electronics OY

TR01 Transfer of patent right