JP5651807B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP5651807B2 JP5651807B2 JP2014512980A JP2014512980A JP5651807B2 JP 5651807 B2 JP5651807 B2 JP 5651807B2 JP 2014512980 A JP2014512980 A JP 2014512980A JP 2014512980 A JP2014512980 A JP 2014512980A JP 5651807 B2 JP5651807 B2 JP 5651807B2
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- buffer layer
- semiconductor element
- metal buffer
- semiconductor device
- layer
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Description
具体的には、本発明においては、
半導体素子、および
半導体素子に電気的に接続された金属緩衝層
を有して成り、
金属緩衝層と半導体素子とが相互に面接触するような形態で金属緩衝層と半導体素子とが接続されており、また
金属緩衝層が、二次実装基板への実装に用いられる外部接続端子になっていると共に、二次実装基板と半導体装置(特に半導体素子)との間にて応力緩和作用を有する緩衝部材となっていることを特徴とする、半導体装置が提供される。
(i)半導体素子を用意する工程、および
(ii)半導体素子と電気的に接続されるように金属緩衝層を形成する工程
を含んで成り、
工程(ii)では、金属緩衝層と半導体素子とが相互に面接触する形態となるように金属緩衝層を形成しており、その金属緩衝層が、二次実装基板への実装に用いられる外部接続端子となると共に、二次実装基板と半導体装置(特に半導体素子)との間にて応力緩和作用を有する緩衝部材となる。
図2(A)〜(C)に、本発明の半導体装置の構成を模式的に示す。図示されるように、本発明の半導体装置100は、金属緩衝層10、金属緩衝層下地30および半導体素子50を有して成る。半導体素子50は、金属緩衝層10上に設置された形態を有しており、金属緩衝層上の下地30の少なくとも一部と接して設けられている。金属緩衝層10は、本発明の半導体装置の二次実装基板への実装に用いられる外部接続端子(例えば半導体素子の電極部材)として用いられると共に、二次実装基板と半導体装置との間で応力緩和作用を呈する緩衝部材として用いられる(図3参照)。
「金属緩衝層・下地の屈曲態様」を図15(a)〜(d)に示す。図示するように、かかる態様では、金属緩衝層10(特にその上面)および反射層30(下地)が屈曲した形態を有している。図15(a)では、中央部分A1(半導体素子領域)が僅かに隆起するように金属緩衝層10およびその下地30が屈曲している。図15(b)は、大部分が窪みつつも中央部分A2(半導体素子領域)が僅かに隆起するように金属緩衝層10およびその下地30が屈曲している。別の観点で見れば、図15(b)の態様は、より外側に位置する金属緩衝層10の厚さが大きくなった態様であるともいえる。図15(c)は、中央部分A3(半導体素子領域およびその近傍領域)が僅かに凹むように金属緩衝層10およびその下地30が屈曲している。かかる態様も同様に、より外側に位置する金属緩衝層の厚さが大きくなった態様であるともいえる。そして、図15(d)は、図15(c)の態様からP部分の絶縁層が除かれたような形態を有している。このような図15(a)〜(d)に示す形態であっても“放熱特性”と“電気的接続”と“応力緩和”とが好適に達成されている。
リフレクタ構造を有する本発明の半導体装置100の態様を図16に示す。リフレクタ態様は、上記金属緩衝層・下地の屈曲態様の変更態様に相当し得、金属緩衝層10(特にその一部分)および下地30が大きく窪むように屈曲しており、その窪んだ領域に半導体素子50が位置付けられている。かかるリフレクタ態様であっても“放熱特性”と“電気的接続”と“応力緩和”とが好適に達成されている。特筆すれば、“リフレクタ”ゆえに、半導体素子50の周囲の下地30によって(特に下地30が発光半導体の発光面より高いレベルにおいても存在する形態となっているので)、半導体素子50からの光を効率的に反射させることができ、その点で“光取出し特性”が向上し得る。更には、リフレクタ構造の半導体装置では、“更なる高密度(小型装置)”、“更なる高熱伝導”および“更に簡易な製造プロセス”などといった効果も奏され得る。
次に、本発明の半導体装置の製造方法について説明する。図17(a)〜(d)に本発明の製造方法に関連したプロセスを模式的に示している。本発明の製造方法は、まず、工程(i)として、図17(a)に示すように半導体素子50を用意する。用意される半導体素子50は、次工程で行う緩衝層形成・その下地形成にとって望ましいものとなっていることが好ましい。例えば、工程(i)では、半導体素子50として「半導体素子の少なくとも主面側に絶縁層が設けられた半導体素子」を用意する。あくまでも一例であるが、半導体素子50を、図17(a)で示すように絶縁層に埋設された形態として用意する。次いで、工程(ii)として、半導体素子50上に金属緩衝層10を形成する(より具体的にいえば、半導体素子50に対してダイレクトメタライズを施す(例えばCuダイレクトメタライズを施す)。かかる工程(ii)においては、まず、図17(b)に示すように金属緩衝層を形成するための下地30を半導体素子50上に形成し(特に半導体素子の主面の一部を覆うように形成し)、次いで、図17(c)に示すように、かかる下地30を介して半導体素子50と面接触するように金属緩衝層10を形成する。以上の工程(i)および工程(ii)を経ることによって、本発明の半導体装置100を得ることができる(図17(d)参照)。
半導体素子に対して直接的に乾式めっきの下地層およびその下地層上に幅広い湿式めっきの金属緩衝層を形成する。乾式めっきの下地層は半導体素子直下に位置づけられた反射層として用いる一方、湿式めっきの金属緩衝層(および乾式めっきの反射層)は発光素子の支持層として用いる。
図18(a)〜(g)に「プロセス態様1」の工程断面図を模式的に示す。かかる態様は、半導体ウエハをベースに半導体装置の製造を実施するプロセスである。まず、図18(a)および(b)に示すように、半導体ウエハ50’の主面に封止層72’を形成する。封止層72’は、封止原料をスピンコート法やドクターブレード法などにより半導体ウエハの主面に塗布した後で熱処理に付すことによって設けることができ、あるいは、半導体ウエハに封止フィルムなどを貼り合わせることによっても設けることができる。次いで、図18(c)に示すように、例えばスパッタリングなどの乾式めっき法によって緩衝層下地30を形成する。次いで、図18(d)に示すように、緩衝層下地30を介して半導体ウエハ50’上に直接的にサブ緩衝層パターン10’を形成する。かかるサブ緩衝層パターン10’の形成は、図19に示すように、「めっき後にエッチングによりパターン化する手法」によって行うことができる。具体的には、図示するように、電気めっき(例えば電解Cuめっき)によって、緩衝層下地の全面に金属層(例えば銅層)を形成する。
図22(a)〜(h)に「プロセス態様2」の工程断面図を模式的に示す。かかる態様は、半導体チップをベースに半導体装置の製造を行うプロセスである。まず、図22(a)に示すように、キャリアフィルム85上に複数の半導体チップ50を相互の間隔を空けて配置する。次いで、図22(b)に示すように、半導体チップ50を覆うようにキャリアフィルム85上に封止層72’(特に発光型の半導体素子の場合は、光透過性封止層)を形成する。そして、封止層72’の形成後にキャリアフィルム85を剥離すると、図22(c)に示すように、封止層72’内に埋設された半導体チップ50を得ることができる(即ち、「少なくとも主面側に封止層が設けられた半導体素子」を用意することができる)。特に、相互に“面一”となるような形態で封止層72’内に埋設された半導体素子50が得られる。
図23(a)〜(g)に「プロセス態様3」の工程断面図を模式的に示す。かかる態様は、上記のプロセス態様2の変更態様に相当する。まず、図23(a)に示すように、キャリアフィルム85上に複数の半導体チップ50を相互の間隔を空けて配置する。次いで、隣接する半導体チップ50の間に絶縁膜72’(例えば無機絶縁膜)を形成する。図示するように、半導体チップ50と面一になるように絶縁膜72’を形成することが好ましい。かかる絶縁層パターン72’の形成は、プロセス態様1にて図21Aまたは図21Bを参照して説明したような手法で行うことができる。引き続いて、発光型の半導体素子の場合は、半導体チップ50および絶縁層パターン72’上に蛍光体層80を形成した後(図23(b)参照)、キャリアフィルム85を剥離すると、図23(c)に示すような形態で半導体素子50を用意することができる。
図24(a)〜(g)に、発光型の半導体素子の場合の「プロセス態様4」の工程断面図を模式的に示す。かかる態様も、上記のプロセス態様2の変更態様に相当する。まず、キャリアフィルム85上に蛍光体層80を形成した後、かかる蛍光体層80上に複数の半導体チップ50を相互の間隔を空けて配置する(図24(a)参照)。次いで、図24(b)に示すように、半導体チップ50を覆うように蛍光体層80上に絶縁層72’(特に感光性材料層)を形成する。引き続いて、図24(c)に示すように、絶縁層72’に対してパターン形成処理を施す。図示するように、隣接する半導体チップ50の間に絶縁層72’を残すようなパターン形成処理を行うことが好ましい。このようなパターン処理は、プロセス態様1にて図21Aを参照して説明したような手法で行うことができる。
図26(a)〜(g)に、発光型の半導体素子の場合の「プロセス態様5」の工程断面図を模式的に示す。かかる態様は、リフレクタ構造を有する半導体装置100の製造プロセス態様に相当する。まず、キャリアフィルム85上にサブ蛍光体層80’を複数形成し、サブ蛍光体層80’の各々に半導体素子チップ50を1つずつ配置する(図26(a)参照)。次いで、図26(b)に示すように、絶縁層原料をスピンコートまたはドクターブレードなどによって全面塗布した後、あるいは、絶縁層フィルムなどを貼り合わせることによって設けた後、パターン形成処理をすることによって、半導体素子チップ50の各々に対して半導体素子チップ50の表面の一部を露出させる局所的な絶縁層72’を形成する(図26(c)参照)。引き続いて、金属緩衝層の下地30を形成した後、半導体素子チップの各々につき2つの第1のサブ緩衝層10’を形成する(図26(d)参照)。尚、“リフレクタ”ゆえ、図26(d)に示すように、「キャリアフィルム85上に設けられたサブ蛍光体層80’、半導体素子チップ50および局所的な絶縁層72’から構成された半導体装置前駆体100’」の輪郭形状に沿うように、下地30および第1のサブ緩衝層10’は屈曲した形態で形成される。
第1態様:半導体装置であって、
半導体素子、および
半導体素子に電気的に接続された金属緩衝層
を有して成り、
金属緩衝層と半導体素子とが相互に面接触するような形態で金属緩衝層と半導体素子とが接続されており、また
金属緩衝層が、二次実装基板への実装に用いられる外部接続端子になっていると共に、二次実装基板と半導体素子との間にて応力緩和作用を有する緩衝部材ともなっていることを特徴とする、半導体装置。
第2態様:上記第1態様において、金属緩衝層が半導体素子を支持する支持層を成していることを特徴とする半導体装置。
第3態様:上記第1態様または第2態様において、半導体素子からはみ出すように金属緩衝層が設けられていることを特徴とする半導体装置(即ち、半導体素子の下方領域のみならず、その外側領域にも横方向へと延在するように“金属緩衝層”及び“反射層(または下地層)”が設けられている半導体装置)。
第4態様:上記第1態様〜第3態様のいずれかにおいて、金属緩衝層の厚みが50μm以上となっていることを特徴とする半導体装置。
第5態様:上記第1態様〜第4態様のいずれかにおいて、金属緩衝層では、その有する結晶粒子構造が局所的に異なっており、半導体素子側の緩衝層領域における平均結晶粒径が、二次実装基板側の緩衝層領域における平均結晶粒径よりも小さくなっていることを特徴とする半導体装置。
第6態様:上記第5態様において、半導体素子側の緩衝層領域における平均結晶粒径が5μm以下となっている一方、二次実装基板側の緩衝層領域における平均結晶粒径が10μm以上となっていることを特徴とする半導体装置。
第7態様:上記第1態様〜第6態様のいずれかにおいて、金属緩衝層が、その母材中に少なくとも1種類以上の粒子を含んで成ることを特徴とする半導体装置。
第8態様:上記第7態様において、金属緩衝層の母材中に含まれる粒子が金属粒子であることを特徴とする半導体装置。
第9態様:上記第7態様において、金属緩衝層の母材中に含まれる粒子が絶縁性粒子であることを特徴とする半導体装置。
第10態様:上記第7態様〜第9態様のいずれかにおいて、金属緩衝層においては、粒子の含有率が局所的に異なっており、半導体素子側の緩衝層領域における粒子含有率が、二次実装基板側の緩衝層領域における粒子含有率よりも大きいことを特徴とする半導体装置。
第11態様:上記第7態様および該第7態様に従属する上記第8態様〜第10態様のいずれかにおいて、金属緩衝層の母材がめっき層から成り、そのめっき層中に粒子が含有されていることを特徴とする半導体装置。
第12態様:上記第1態様〜第11態様のいずれかにおいて、金属緩衝層の周囲に第1絶縁部が設けられている一方、半導体素子の周囲に第2絶縁部が設けられていることを特徴とする半導体装置。
第13態様:上記第2態様に従属する第12態様において、金属緩衝層および第1絶縁部が支持層を成していることを特徴とする半導体装置。
第14態様:上記第12態様または第13態様において、半導体素子が電極を複数有し、その電極に対して電気的に接続するように金属緩衝層が複数設けられており、また
隣接する金属緩衝層の間に第1絶縁部が少なくとも設けられていることを特徴とする半導体装置。
第15態様:上記第14の態様において、隣接する金属緩衝層の間に設けられた第1絶縁部の局所的な領域が、幅狭部分と幅広部分との2つの領域部分から構成されていることを特徴とする半導体装置。
第16態様:上記第1態様〜第15態様のいずれかにおいて、金属緩衝層上に設けられた反射層を更に有してなり、
反射層の少なくとも一部を介して半導体素子と金属緩衝層とが面接触するように接続されていることを特徴とする半導体装置。
第17態様:半導体装置の製造方法であって、
(i)半導体素子を用意する工程、および
(ii)半導体素子と電気的に接続されるように金属緩衝層を形成する工程
を含んで成り、
工程(ii)では、金属緩衝層と半導体素子とが相互に面接触するように金属緩衝層を形成しており、その金属緩衝層が、二次実装基板への実装に用いられる外部接続端子となると共に、二次実装基板と半導体素子との間にて応力緩和作用を有する緩衝部材ともなることを特徴とする、半導体装置の製造方法。
第18態様:上記第17態様において、工程(ii)では、金属緩衝層を形成するための下地を半導体素子上に形成した後、かかる下地を介して半導体素子と面接触するような形態で金属緩衝層を形成することを特徴とする半導体装置の製造方法。
第19態様:上記第18態様において、下地を乾式めっき法で形成する一方、金属緩衝層を湿式めっき法で形成することを特徴とする半導体装置の製造方法。
第20態様:上記第17態様〜第19態様のいずれかにおいて、工程(i)の半導体素子を、その半導体素子の少なくとも主面側に絶縁層が設けられた半導体素子として用意することを特徴とする半導体装置の製造方法。
第21態様:上記第20態様において、半導体素子が半導体素子チップの形態を有しており、
工程(i)では、キャリアフィルムに半導体素子チップを配置した後、その半導体素子チップを覆うようにキャリアフィルム上に絶縁層を形成し、次いで、キャリアフィルムを剥離することによって、絶縁層と面一形態で絶縁層内に埋設された半導体素子チップを用意することを特徴とする半導体装置の製造方法。
第22態様:上記第17態様〜第20態様のいずれかにおいて、工程(i)の半導体素子が半導体素子チップの形態を有しており、
工程(ii)では、金属緩衝層の一部が半導体素子チップから外側へとはみ出すように金属緩衝層を形成することを特徴とする半導体装置の製造方法。
第23態様:上記第17態様〜第20態様のいずれかにおいて、工程(i)の半導体素子が半導体素子ウエハの形態を有しており、
工程(ii)においては半導体素子ウエハ上に複数の金属緩衝層を形成し、
最終的に複数の金属緩衝層の少なくとも1つが2つへと分割される切断操作を行うことを特徴とする半導体装置の製造方法。
第24態様:上記第17態様〜第23態様のいずれかにおいて、金属緩衝層の周囲に絶縁部を形成する工程を更に含んで成り、
金属緩衝層の形成が第1サブ緩衝層の形成と第2サブ緩衝層の形成との2段階に分けて実施され、第1サブ緩衝層の形成と第2サブ緩衝層の形成との間にて絶縁部の形成を実施することを特徴とする半導体装置の製造方法。
第25態様:上記第24態様において、工程(ii)では金属緩衝層を複数形成しており、
絶縁部の形成に際しては、隣接する2つの金属緩衝層の間の空間が絶縁部で満たされることになるように、隣接する2つの金属緩衝層にまたがって絶縁部を形成することを特徴とする半導体装置の製造方法。
第26態様:上記第18態様または該18態様に従属する上記第19態様〜第25態様のいずれかにおいて、下地を最終的に半導体装置における反射層として用いることを特徴とする半導体装置の製造方法。
10’ サブ緩衝層パターン(第1サブ緩衝層パターン)
10” 第2のサブ緩衝層パターン(第2サブ緩衝層パターン)
10a 金属緩衝層
10b 金属緩衝層
15 金属緩衝層に含まれる粒子
30 金属緩衝層の下地
50 半導体素子
50’ 半導体ウエハ
70 第1絶縁部
70A 隣接する金属緩衝層の間の領域に設けられた局所的な第1絶縁部
70A1 局所的な第1絶縁部の幅狭部分
70A2 局所的な第1絶縁部の幅広部分
70’ 絶縁層パターン(例えば樹脂層パターンまたは無機材層パターン)
72 第2絶縁部(絶縁層)
72’ 封止層(例えば封止樹脂層または封止無機材層)
80 蛍光体層
85 キャリアフィルム
90 レンズ部材
100 半導体装置
100’ 半導体装置前駆体
Claims (22)
- 半導体装置であって、
半導体素子、および
前記半導体素子に電気的に接続された金属緩衝層
を有して成り、
前記半導体素子の電極を介して前記金属緩衝層と該半導体素子とが相互に面接触するような形態で該金属緩衝層と該半導体素子とが接続されており、また
前記金属緩衝層が、二次実装基板への実装に用いられる外部接続端子になっていると共に、該二次実装基板と前記半導体素子との間にて応力緩和作用を有する緩衝部材となっており、
前記金属緩衝層が前記半導体素子を支持する支持層を成しており、また
前記半導体素子からはみ出すように前記金属緩衝層が設けられていることを特徴とする、半導体装置。 - 前記金属緩衝層の厚みが50μm以上となっていることを特徴とする、請求項1に記載の半導体装置。
- 前記金属緩衝層では、その有する結晶粒子構造が局所的に異なっており、半導体素子側の緩衝層領域における平均結晶粒径が、二次実装基板側の緩衝層領域における平均結晶粒径よりも小さくなっていることを特徴とする、請求項1に記載の半導体装置。
- 前記半導体素子側の前記緩衝層領域における前記平均結晶粒径が5μm以下となっている一方、前記二次実装基板側の前記緩衝層領域における前記平均結晶粒径が10μm以上となっていることを特徴とする、請求項3に記載の半導体装置。
- 前記金属緩衝層が、その母材中に少なくとも1種類以上の粒子を含んで成ることを特徴とする、請求項1に記載の半導体装置。
- 前記母材中に含まれる前記粒子が金属粒子であることを特徴とする、請求項5に記載の半導体装置。
- 前記母材中に含まれる前記粒子が絶縁性粒子であることを特徴とする、請求項5に記載の半導体装置。
- 前記金属緩衝層においては、前記粒子の含有率が局所的に異なっており、半導体素子側の緩衝層領域における粒子含有率が、二次実装基板側の緩衝層領域における粒子含有率よりも大きいことを特徴とする、請求項5に記載の半導体装置。
- 前記金属緩衝層の前記母材がめっき層から成り、該めっき層中に前記粒子が含有されていることを特徴とする、請求項6に記載の半導体装置。
- 前記金属緩衝層の周囲に第1絶縁部が設けられている一方、前記半導体素子の周囲に第2絶縁部が設けられていることを特徴とする、請求項1に記載の半導体装置。
- 前記金属緩衝層に加えて前記第1絶縁部も前記支持層を成していることを特徴とする、請求項10に記載の半導体装置。
- 前記半導体素子の前記電極が複数設けられ、該電極に対して電気的に接続するように前記金属緩衝層が複数設けられており、また
隣接する前記金属緩衝層の間に前記第1絶縁部が少なくとも設けられていることを特徴とする、請求項10に記載の半導体装置。 - 前記隣接する前記金属緩衝層の間に設けられた前記第1絶縁部の局所的な領域が、幅狭部分と幅広部分との2つの領域部分から構成されていることを特徴とする、請求項12に記載の半導体装置。
- 前記金属緩衝層上に設けられた反射層を更に有してなり、
前記反射層の少なくとも一部を介して前記半導体素子と前記金属緩衝層とが前記面接触するように接続されていることを特徴とする、請求項1に記載の半導体装置。 - 半導体装置の製造方法であって、
(i)半導体素子を用意する工程、および
(ii)前記半導体素子と電気的に接続されると共に、該半導体素子からはみ出すように金属緩衝層を形成する工程
を含んで成り、
前記工程(ii)では、前記半導体素子の電極を介して前記金属緩衝層と該半導体素子とが相互に面接触するように該金属緩衝層を形成しており、該金属緩衝層が、二次実装基板への実装に用いられる外部接続端子となると共に、該二次実装基板と該半導体素子との間にて応力緩和作用を有する緩衝部材となり、
前記工程(ii)では、前記金属緩衝層を形成するための下地を前記半導体素子上に形成した後、該下地を介して前記半導体素子と前記面接触するような形態で前記金属緩衝層を形成し、また
前記金属緩衝層の周囲に絶縁部を形成する工程を更に含んで成り、該金属緩衝層の形成が第1サブ緩衝層の形成と第2サブ緩衝層の形成との2段階に分けて実施され、該第1サブ緩衝層の形成と該第2サブ緩衝層の形成との間にて前記絶縁部の形成を実施する
ことを特徴とする、半導体装置の製造方法。 - 前記下地を乾式めっき法で形成する一方、前記金属緩衝層を湿式めっき法で形成することを特徴とする、請求項15に記載の半導体装置の製造方法。
- 前記工程(i)の前記半導体素子を、該半導体素子の少なくとも主面側に絶縁層が設けられた半導体素子として用意することを特徴とする、請求項15に記載の半導体装置の製造方法。
- 前記半導体素子が半導体素子チップの形態を有しており、
前記工程(i)では、キャリアフィルムに前記半導体素子チップを配置した後、該半導体素子チップを覆うように該キャリアフィルム上に前記絶縁層を形成し、次いで、該キャリアフィルムを剥離することによって、該絶縁層と面一形態で該絶縁層内に埋設された前記半導体素子チップを用意することを特徴とする、請求項17に記載の半導体装置の製造方法。 - 前記工程(i)の前記半導体素子が半導体素子チップの形態を有しており、
前記工程(ii)では、前記金属緩衝層の一部が前記半導体素子チップから外側へとはみ出すように該金属緩衝層を形成することを特徴とする、請求項15に記載の半導体装置の製造方法。 - 前記工程(i)の前記半導体素子が半導体素子ウエハの形態を有しており、
前記工程(ii)においては前記半導体素子ウエハ上に複数の前記金属緩衝層を形成し、
最終的に前記複数の前記金属緩衝層の少なくとも1つが2つへと分割される切断操作を行うことを特徴とする、請求項15に記載の半導体装置の製造方法。 - 前記工程(ii)では前記金属緩衝層を複数形成しており、
前記絶縁部の形成に際しては、隣接する2つの前記金属緩衝層の間の空間が該絶縁部で満たされることになるように、該隣接する2つの該金属緩衝層にまたがって前記絶縁部を形成することを特徴とする、請求項15に記載の半導体装置の製造方法。 - 前記下地を最終的に前記半導体装置における反射層として用いることを特徴とする、請求項15に記載の半導体装置の製造方法。
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Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3057123B1 (en) * | 2013-10-07 | 2021-12-08 | Furukawa Electric Co., Ltd. | Joining structure comprising layers with different average crystal grain sizes for a semiconductor chip |
EP3078063B1 (en) * | 2013-12-06 | 2020-06-10 | Lumileds Holding B.V. | Mounting assembly and lighting device |
DE102016121510A1 (de) | 2016-11-10 | 2018-05-17 | Osram Opto Semiconductors Gmbh | Leiterrahmen, optoelektronisches Bauelement mit einem Leiterrahmen und Verfahren zur Herstellung eines optoelektronischen Bauelements |
DE102017119344A1 (de) * | 2017-08-24 | 2019-02-28 | Osram Opto Semiconductors Gmbh | Träger und Bauteil mit Pufferschicht sowie Verfahren zur Herstellung eines Bauteils |
US10748804B2 (en) * | 2017-12-19 | 2020-08-18 | PlayNitride Inc. | Structure with micro device having holding structure |
JP7063718B2 (ja) * | 2018-05-17 | 2022-05-09 | エイブリック株式会社 | プリモールド基板とその製造方法および中空型半導体装置とその製造方法 |
WO2020137470A1 (ja) * | 2018-12-26 | 2020-07-02 | 豊田合成株式会社 | 半導体発光素子 |
US20210091265A1 (en) * | 2019-08-21 | 2021-03-25 | Industrial Technology Research Institute | Light-emitting device and display apparatus |
US11342248B2 (en) | 2020-07-14 | 2022-05-24 | Gan Systems Inc. | Embedded die packaging for power semiconductor devices |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003017757A (ja) * | 2001-06-29 | 2003-01-17 | Sanken Electric Co Ltd | フリップチップ形半導体発光素子 |
JP2008042041A (ja) * | 2006-08-09 | 2008-02-21 | Fuji Electric Holdings Co Ltd | 半導体装置 |
JP2011071274A (ja) * | 2009-09-25 | 2011-04-07 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2012164956A (ja) * | 2011-01-18 | 2012-08-30 | Napura:Kk | 電子部品支持装置及び電子デバイス |
Family Cites Families (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0605179B1 (en) | 1992-12-22 | 1997-05-02 | Citizen Watch Co. Ltd. | Hard carbon coating-clad base material |
US5353498A (en) | 1993-02-08 | 1994-10-11 | General Electric Company | Method for fabricating an integrated circuit module |
JPH11126863A (ja) * | 1997-10-24 | 1999-05-11 | Ngk Spark Plug Co Ltd | 配線基板およびその製造方法 |
JP2000323510A (ja) * | 1999-05-11 | 2000-11-24 | Shinko Electric Ind Co Ltd | 柱状電極付き半導体ウエハ及びその製造方法並びに半導体装置 |
US6423161B1 (en) | 1999-10-15 | 2002-07-23 | Honeywell International Inc. | High purity aluminum materials |
JP2001217553A (ja) | 2000-02-03 | 2001-08-10 | Nippon Zeon Co Ltd | 多層回路基板の製造方法 |
JP2002170921A (ja) | 2000-12-01 | 2002-06-14 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP4322508B2 (ja) | 2003-01-15 | 2009-09-02 | 新光電気工業株式会社 | 半導体装置の製造方法 |
JP2005019754A (ja) | 2003-06-26 | 2005-01-20 | Sony Corp | 複合部品及びその製造方法 |
DE10334576B4 (de) | 2003-07-28 | 2007-04-05 | Infineon Technologies Ag | Verfahren zum Herstellen eines Halbleiterbauelements mit einem Kunststoffgehäuse |
KR100858309B1 (ko) | 2004-09-01 | 2008-09-11 | 스미토모 긴조쿠 고잔 가부시키가이샤 | 2층 플렉시블 기판 및 그 제조 방법 |
FI117369B (fi) | 2004-11-26 | 2006-09-15 | Imbera Electronics Oy | Menetelmä elektroniikkamoduulin valmistamiseksi |
JP2006339365A (ja) | 2005-06-01 | 2006-12-14 | Mitsui Mining & Smelting Co Ltd | 配線基板およびその製造方法、多層積層配線基板の製造方法並びにビアホールの形成方法 |
US7946022B2 (en) | 2005-07-05 | 2011-05-24 | The Furukawa Electric Co., Ltd. | Copper alloy for electronic machinery and tools and method of producing the same |
KR100797719B1 (ko) | 2006-05-10 | 2008-01-23 | 삼성전기주식회사 | 빌드업 인쇄회로기판의 제조공정 |
KR100875128B1 (ko) | 2007-01-16 | 2008-12-22 | 한국광기술원 | 고내정전압을 갖는 발광다이오드 및 그의 제조방법 |
JP4986082B2 (ja) | 2007-09-10 | 2012-07-25 | 住友金属鉱山株式会社 | プリント配線基板の製造方法 |
JP2009129928A (ja) | 2007-11-19 | 2009-06-11 | Toyoda Gosei Co Ltd | Ledランプ |
TWI364801B (en) | 2007-12-20 | 2012-05-21 | Chipmos Technologies Inc | Dice rearrangement package structure using layout process to form a compliant configuration |
US8531126B2 (en) | 2008-02-13 | 2013-09-10 | Canon Components, Inc. | White light emitting apparatus and line illuminator using the same in image reading apparatus |
US8513534B2 (en) * | 2008-03-31 | 2013-08-20 | Hitachi, Ltd. | Semiconductor device and bonding material |
JP5428667B2 (ja) | 2009-09-07 | 2014-02-26 | 日立化成株式会社 | 半導体チップ搭載用基板の製造方法 |
KR101086828B1 (ko) | 2009-11-30 | 2011-11-25 | 엘지이노텍 주식회사 | 매립형 인쇄회로기판, 다층 인쇄회로기판 및 이들의 제조방법 |
JP5609891B2 (ja) | 2009-12-09 | 2014-10-22 | 宇部興産株式会社 | ポリイミドフィルムの製造方法、およびポリイミドフィルム |
US8414145B2 (en) | 2010-09-06 | 2013-04-09 | Kabushiki Kaisha Toshiba | Light emitting device |
JP5447316B2 (ja) | 2010-09-21 | 2014-03-19 | 株式会社大真空 | 電子部品パッケージ用封止部材、及び電子部品パッケージ |
CN103221583B (zh) | 2010-11-22 | 2015-05-13 | 三井金属矿业株式会社 | 表面处理铜箔 |
US9704793B2 (en) | 2011-01-04 | 2017-07-11 | Napra Co., Ltd. | Substrate for electronic device and electronic device |
US8984747B2 (en) | 2011-04-05 | 2015-03-24 | Electronics And Telecommunications Research Institute | Method for manufacturing fabric type circuit board |
EP2775808A4 (en) | 2011-10-31 | 2015-05-27 | Meiko Electronics Co Ltd | METHOD FOR MANUFACTURING A SUBSTRATE HAVING AN INTEGRATED COMPONENT, AND SUBSTRATE HAVING AN INTEGRATED COMPONENT MANUFACTURED BY SAID METHOD |
US20130256884A1 (en) | 2012-03-27 | 2013-10-03 | Intel Mobile Communications GmbH | Grid fan-out wafer level package and methods of manufacturing a grid fan-out wafer level package |
-
2013
- 2013-08-02 US US14/402,221 patent/US9449937B2/en not_active Expired - Fee Related
- 2013-08-02 CN CN201380026349.6A patent/CN104335343A/zh active Pending
- 2013-08-02 WO PCT/JP2013/004704 patent/WO2014038128A1/ja active Application Filing
- 2013-08-02 JP JP2014512980A patent/JP5651807B2/ja not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003017757A (ja) * | 2001-06-29 | 2003-01-17 | Sanken Electric Co Ltd | フリップチップ形半導体発光素子 |
JP2008042041A (ja) * | 2006-08-09 | 2008-02-21 | Fuji Electric Holdings Co Ltd | 半導体装置 |
JP2011071274A (ja) * | 2009-09-25 | 2011-04-07 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2012164956A (ja) * | 2011-01-18 | 2012-08-30 | Napura:Kk | 電子部品支持装置及び電子デバイス |
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