FI119583B - Förfarande för tillverkning av en elektronikmodul - Google Patents

Förfarande för tillverkning av en elektronikmodul Download PDF

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Publication number
FI119583B
FI119583B FI20030292A FI20030292A FI119583B FI 119583 B FI119583 B FI 119583B FI 20030292 A FI20030292 A FI 20030292A FI 20030292 A FI20030292 A FI 20030292A FI 119583 B FI119583 B FI 119583B
Authority
FI
Finland
Prior art keywords
component
conductor layer
conductor
contact
layer
Prior art date
Application number
FI20030292A
Other languages
English (en)
Finnish (fi)
Other versions
FI20030292A (sv
FI20030292A0 (sv
Inventor
Risto Tuominen
Petteri Palm
Original Assignee
Imbera Electronics Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=8565725&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=FI119583(B) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Publication of FI20030292A0 publication Critical patent/FI20030292A0/sv
Priority to FI20030292A priority Critical patent/FI119583B/sv
Application filed by Imbera Electronics Oy filed Critical Imbera Electronics Oy
Priority to AT04714345T priority patent/ATE524955T1/de
Priority to PCT/FI2004/000101 priority patent/WO2004077902A1/en
Priority to US10/546,820 priority patent/US7299546B2/en
Priority to JP2006502075A priority patent/JP2006520093A/ja
Priority to KR1020057015597A priority patent/KR20050109944A/ko
Priority to EP04714345A priority patent/EP1597947B1/en
Publication of FI20030292A publication Critical patent/FI20030292A/sv
Priority to US11/907,795 priority patent/US7609527B2/en
Application granted granted Critical
Publication of FI119583B publication Critical patent/FI119583B/sv
Priority to US12/603,324 priority patent/US8817485B2/en
Priority to US14/467,079 priority patent/US10085345B2/en
Priority to US16/104,979 priority patent/US10765006B2/en
Priority to US17/005,527 priority patent/US11071207B2/en
Priority to US17/357,399 priority patent/US20210321520A1/en
Priority to US18/184,837 priority patent/US20230225055A1/en

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    • H—ELECTRICITY
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    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04—Assemblies of printed circuits
    • H05K2201/042—Stacked spaced PCBs; Planar parts of folded flexible circuits having mounted components in between or spaced from each other
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/05—Flexible printed circuits [FPCs]
    • H05K2201/056—Folded around rigid support or component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/063—Lamination of preperforated insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/166—Alignment or registration; Control of registration
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49131—Assembling to base an electrical component, e.g., capacitor, etc. by utilizing optical sighting device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)
  • Wire Bonding (AREA)
  • Credit Cards Or The Like (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Combinations Of Printed Boards (AREA)

Claims (20)

1. Förfarande för tillverkning av en elektronikmodul, vid vilket förfarande: - en installationsbas framställs, som omfattar ett isoleringsmaterialskikt (1), S som uppvisar ätminstone en installationskavitet (2) för en komponent (6), samt ett ledarskikt (4) pä ytan av isoleringsmaterialskiktet (1), vilket ledarskikt täcker nämnda installationskavitet (2), - en komponent (6) väljs, som uppvisar en kontaktbildningsyta, som uppvisar kontaktomräden (7), 10. komponenten (6) anordnas i installationskaviteten (2) pä sä sätt, att kontaktbildningsytan kommer mot ledarskiktet (4), - elektriska kontakter mellan komponentens (6) kontaktomräden (7) och installationsbasens ledarskikt (4) bildas, och - ledarmönster (14) tillverkas av installationsbasens ledarskikt (4), 15 kännetecknat av att • · • · · • ·· - ätminstone ett inpassningsmärke (3) tillverkas pä installationsbasen, • · - vid installationen av komponenten (6) i installationskaviteten (2) inpassas * · * · .1 2 3! komponenten (6) i förhällande tili det ätminstone ena inpassningsmärket (3) • φ tillverkat i installtionsbasen, och • · Φ · ··· 20. ledarmönstren (14) inpassas med hjälp av det ätminstone ena • · V,· inpassningsmärket (3) tillverkat i installationsbasen. • · · • · • · *·· · • · t • · · 2 • ·
2. Förfarande enligt patentkrav 1, kännetecknat av att ledarskiktet (4) och . komponentens kontaktomräden (7) bestär av metall och den elektriska kontakten bildas 3 .'. J 25 genom att kontaktomrädena ansluts metallurgiskt tili ledarskiktet. • · 119583
3. Förfarande enligt patentkrav 1, kännetecknat av art komponentens (6) kontaktomräden (7) bestär av metall och varvid det före bildningen av den elektriska kontakten odlas metalliska kontaktknottror (5) pä ledarskiktet (4) och varvid den elektriska kontakten bildas genom metallurgisk anslutning av kontaktomrädena tili 5 kontaktknottroma.
4. Förfarande enligt patentkrav 1,kännetecknat avatt ledarskiktet (4) bestär av metall och varvid det före bildningen av den elektriska kontakten odlas metalliska kontaktknottror (7) pä komponentens (6) kontaktomräden och varvid den elektriska 10 kontakten bildas genom metallurgisk anslutning av kontaktknottroma tili ledarskiktet.
5. Förfarande enligt nägot av patentkraven 2-4, kännetecknat avatt den metallurgiska anslutningen genomförs utan lödning medelst ett ultraljud- eller termokompressionsförfarande. 15 .
6. Förfarande enligt patentkrav 1, kännetecknat avatt ätminstone ett • ♦♦ .«Σ', inpassningsmärke utgörs av ett genomgäende häl (3), vilket penetrerar • · · .·. · isoleringsmaterialskiktet (1) och ledarskiktet (4) pä isoleringsmaterialskiktets yta. • · · φφφ • · · »· · • · · • · .···. 20
7. Förfarande enligt patentkrav 6, kännetecknat avatt ledarmönstren (14) Φ · inpassas i förhällande tili komponenten medelst ätminstone ett genomgäende häl (3). • ♦ φφφ # φ · φ φ • · • m # Φ • Φ ·
8. Förfarande enligt patentkrav 1,kännetecknat avatt ätminstone ett ,···, inpassningsmärke utgörs av ett pä ytan av ledarskiktet framställt mönster, tili exempel • · • · · 25 en metallisk kontaktknottra. • · φ φ φφφ • · · φ φ φ φ φ • · 119583
9. Förfarande enligt nägot av patentkraven 1-8, kännetecknat avatt komponenten fästs vid isoleringsmaterialskiktet (1) före tillverkningen av ledarmönstren (14) av installationsbasens ledarskikt (4). 5
10. Förfarande enligt patentkrav 9, kännetecknat avatt komponenten (6) fasts vid isoleringsmaterialskiktet (1) genom att man fyller installationskaviteten (2) med isoleringsmaterial (8).
11. Förfarande enligt nägot av patentkraven 1-10, kännetecknat av att 10 ledarmönster (14) tillverkas av installationsunderlagets ledarskikt (4) genom att man avlägsnar en del av ledarskiktets material, varvid det äterstäende materialet bildar ledarmönstren.
12. Förfarande enligt nägot av patentkraven 1-11, kännetecknat av att 15 installationsunderlagets ledarskikt (4) är pä en första yta av installationsbasens : isoleringsmaterialskikt (1) och varvid det tillverkas ett andra ledarskikt (9) pä en andra · . ·: ·, yta av isoleringsmaterialskiktet. • · • f • · · * · · • 1 • · • » ·
13. Förfarande enligt patentkrav 12, k ä n n e t e c k n a t av att det andra ledarskiktet • · 20 (9) tillverkas efter det att komponenten (6) installerats i installationskaviteten (2) med ·»· kontakteringsytan mot det första ledarskiktet (4). • · • · · • · · • · • · · • · • · • · 1
]·,, 14. Förfarande enligt patentkrav 12 eller 13, k ä n n e t e c k n a t av att det andra • · · · .···. ledarskiktet (9) mönstras och pä sä sätt bildas ledarmönster (19) av det andra 25 ledarskiktet. • · • · • · · · · • · · • · • · 119583
15. Förfarande enligt nägot av patentkraven 1-14, kännetecknat avatt fler än en komponent (6) insänks i basen pä motsvarande sätt.
16. Förfarande enligt patentkrav 15, k ä n n e t e c k n a t av att det för vaije komponent 5 (6) som skall insänkas i basen tillverkas en egen installationskavitet (2) i installationsbasen och vaije komponent (6) som skall insänkas i basen anordnas i sin egen installationskavitet (2).
17. Förfarande enligt patentkrav 15 eller 16, k ä n n e t e c k n a t av att det av 10 installationsbasens ledarskikt (4) tillverkas ledarmönstren (14) pä sä sätt, att det under förmedling av ledarmönstren bildas en elektrisk kontakt mellan ätminstone tvä komponenter (6).
18. Förfarande enligt nägot av patentkraven 15 - 17, k ä n n e t e c k n a t av att de i 15 basen insänkta komponentema (6) anslutas elektriskt tili varandra för att bilda en . . funktionell helhet. · · • »i • * * ** • · · • · · • · * · · • M
.··.] 19. Förfarande enligt nägot av patentkraven 1-18, kännetecknat av att det • · tillverkas en första bas och ätminstone en andra bas, och att de tillverkade basema fästs • · • · .···.
20 överlappande vid varandra pä sä sätt, att basema kommer att inpassas i förhällande tili • · · varandra. • · ♦ · · • · · • · «*· • * • · ··· \ 20. Förfarande enligt patentkrav 19, k ä n n e t e c k n a t av att det igenom de överlappande fästade basema tillverkas öppningar för genomföringar (31) och i de pä • · •# 25 detta sätt ästadkomna öppningama tillverkas ledare för att koppia de elektroniska • * kretsama pä vaije bas tili varandra tili en funktionell helhet. · · • · • «
FI20030292A 2003-02-26 2003-02-26 Förfarande för tillverkning av en elektronikmodul FI119583B (sv)

Priority Applications (14)

Application Number Priority Date Filing Date Title
FI20030292A FI119583B (sv) 2003-02-26 2003-02-26 Förfarande för tillverkning av en elektronikmodul
EP04714345A EP1597947B1 (en) 2003-02-26 2004-02-25 Method for manufacturing an electronic module
US10/546,820 US7299546B2 (en) 2003-02-26 2004-02-25 Method for manufacturing an electronic module
PCT/FI2004/000101 WO2004077902A1 (en) 2003-02-26 2004-02-25 Method for manufacturing an electronic module
AT04714345T ATE524955T1 (de) 2003-02-26 2004-02-25 Verfahren zur herstellung eines elektronischen moduls
JP2006502075A JP2006520093A (ja) 2003-02-26 2004-02-25 電子モジュールの製造方法
KR1020057015597A KR20050109944A (ko) 2003-02-26 2004-02-25 전자 모듈 제조 방법
US11/907,795 US7609527B2 (en) 2003-02-26 2007-10-17 Electronic module
US12/603,324 US8817485B2 (en) 2003-02-26 2009-10-21 Single-layer component package
US14/467,079 US10085345B2 (en) 2003-02-26 2014-08-25 Electronic module
US16/104,979 US10765006B2 (en) 2003-02-26 2018-08-20 Electronic module
US17/005,527 US11071207B2 (en) 2003-02-26 2020-08-28 Electronic module
US17/357,399 US20210321520A1 (en) 2003-02-26 2021-06-24 Electronic module
US18/184,837 US20230225055A1 (en) 2003-02-26 2023-03-16 Electronic module

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FI20030292A FI119583B (sv) 2003-02-26 2003-02-26 Förfarande för tillverkning av en elektronikmodul
FI20030292 2003-02-26

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EP (1) EP1597947B1 (sv)
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FI20030293A (sv) * 2003-02-26 2004-08-27 Imbera Electronics Oy Förfarande för tillverkning av en elektronikmodul och en elektronikmodul
US8704359B2 (en) * 2003-04-01 2014-04-22 Ge Embedded Electronics Oy Method for manufacturing an electronic module and an electronic module
US8222723B2 (en) * 2003-04-01 2012-07-17 Imbera Electronics Oy Electric module having a conductive pattern layer
DE10330448A1 (de) * 2003-07-05 2005-01-27 Daimlerchrysler Ag Verfahren zum platzsparenden Anbringen elektrischer Leitungen
FI20031341A (sv) 2003-09-18 2005-03-19 Imbera Electronics Oy Förfarande för tillverkning av en elektronikmodul
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US10085345B2 (en) 2018-09-25
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US7609527B2 (en) 2009-10-27
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