JP2006520093A - 電子モジュールの製造方法 - Google Patents
電子モジュールの製造方法 Download PDFInfo
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- JP2006520093A JP2006520093A JP2006502075A JP2006502075A JP2006520093A JP 2006520093 A JP2006520093 A JP 2006520093A JP 2006502075 A JP2006502075 A JP 2006502075A JP 2006502075 A JP2006502075 A JP 2006502075A JP 2006520093 A JP2006520093 A JP 2006520093A
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- 238000004519 manufacturing process Methods 0.000 title claims description 74
- 238000009434 installation Methods 0.000 claims abstract description 92
- 238000000034 method Methods 0.000 claims description 114
- 239000011810 insulating material Substances 0.000 claims description 36
- 229910052751 metal Inorganic materials 0.000 claims description 27
- 239000002184 metal Substances 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 21
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 1
- 239000012774 insulation material Substances 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 95
- 230000008569 process Effects 0.000 description 20
- 239000004020 conductor Substances 0.000 description 11
- 239000000945 filler Substances 0.000 description 10
- 230000008901 benefit Effects 0.000 description 8
- 239000010949 copper Substances 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 229920000642 polymer Polymers 0.000 description 5
- 239000000956 alloy Substances 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 230000005670 electromagnetic radiation Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000010030 laminating Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229920000106 Liquid crystal polymer Polymers 0.000 description 2
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000004760 aramid Substances 0.000 description 1
- 229920003235 aromatic polyamide Polymers 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920006254 polymer film Polymers 0.000 description 1
- -1 polytetrafluoroethylene Polymers 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000002604 ultrasonography Methods 0.000 description 1
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- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- H01L21/4814—Conductive parts
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Abstract
Description
段階Aでは、電子モジュールの製造プロセスのために、据付基部の本体を形成する、絶縁材料板の適切なシート1を選択する。絶縁材料層1は、設置すべきコンポーネントよりも厚いものとするのが好適である。この場合には、電子モジュールは両面共に平坦にしたまま、コンポーネントを据付基部の内部に完全に埋め込むことができる。当然、より厚めの特別なコンポーネントを据付基部内に埋め込み、コンポーネントの背面が、絶縁材料層1の第2面1bの外側に突出するようにすることもできる。これは特に、製造する電子モジュールの頂部に第2の電子モジュールを積み重ねないようにする場合に行うことができる。しかしながら、構成の耐久性の観点からして、コンポーネントを完全に据付基部内に埋め込むようにするのが好適である。
段階Bでは、シートに埋め込むべきコンポーネントに適したサイズ及び形状の通しキャビティ2を、絶縁材料層1に形成する。通しキャビティ2は、例えば、回路板の製造に用いる何らかの既知の方法を用いることにより形成することができる。キャビティ2は、例えば、フライス削り、衝撃、穿孔により、又はレーザにより機械的に形成することができる。キャビティ2は、絶縁材料層1全体を経て、層の第1面1aから層の第2面1bまで延在している。幾つかのキャビティ2を形成する場合には、使用する製造方法にて出来るだけ高い精度の限度内でキャビティが互いに位置付けられるようにする。
実施例の一連の図は、段階Cの2つの別の方法を示している。変形例のプロセスA(図3A)によると、段階Cにおいては、薄い導電膜4又はより一般的には導電層4を、絶縁材料層1の第1面1aに取付ける。導電膜4は、典型的には金属膜4とする。実施例によっては、適切な金属膜は銅(Cu)膜とするが、他の金属及び合金も使用できることは勿論である。銅膜は、例えば積層することにより、絶縁材料層1に取付けることができる。導電膜4を取付ける補助として、導電膜4を積層する前に、絶縁材料層1の表面又は導電膜4の表面に塗布しておく接着層を用いることができる。実施例のプロセスにおいては、この段階では導電膜4にまだパターンを形成していないため、膜4を絶縁材料層1に対して特に整列させる必要はない。導電膜4の取付け中又は取付け後に、後にコンポーネントを据え付ける段階でコンポーネントを整列させるために用いることができる通し孔3を、据付基部に形成することもできる。しかしながら、コンポーネントを整列させるために他の適切な整列マークを用いることもできるため、通し孔3を形成することは不可欠なことではない。通し孔3を形成する場合は、据付基部に通し孔を少なくとも2つ設けるのが最善である。据え付けるべき各コンポーネントに、それぞれ2つの通し孔3を形成するように作業を進めることもできる。図に示す実施例においては、コンポーネントを整列させるために用いる通し孔3は、絶縁材料層1及び導電膜4の双方を経て延在している。このようにすることの利点は、据付基部の両面で、同じ整列マーク(通し孔3)を整列用に用いることができることにある。
段階Dの変形例を3つ示してある。変形例A(図4A)においては、コンポーネントの接続領域に接点バンプ7を具えているコンポーネント6を、据付基部に接続する。コンポーネントの接点バンプ7を導電層4に接続して、接点バンプ7と導電層4との間を電気的に接触させる。後の製造段階又は電子モジュールの作動中に、接続部が簡単に破壊されないように、この接続部は機械的応力にも耐えるようにするのが良い。この接続は、例えば超音波及び熱圧着法のような適切な接続法を用いて行う。接続段階では、コンポーネント6を整列させるために、整列用に形成した通し孔3、又は他に利用可能な整列マークを用いる。
段階Eでは、コンポーネント6と据付基部との間に残存するスペースを、充填材8により完全に充填する。この充填材は、例えば何らかのポリマとするのが好適である。例えば、適切な微粒子で充填したエポキシをポリマとして用いることができる。ポリマは、例えば、この作業に適した既知の真空ペースト圧縮装置を用いて塗布することができる。図5A、5B及び5Cは、プロセスのA、B、及びCに対応してコンポーネントを取付けた後の据付基部を示している。充填材8の目的は、コンポーネント6を絶縁材料層1に機械的に固着させて、電子モジュールが機械的応力により良好に耐え得るようにすることにある。さらに充填材8は、後の製造段階中にコンポーネント6を保護する。導電層4をエッチングすることで導電パターンを形成した実施例、及びコンポーネント6の表面が、使用するエッチング剤の作用に敏感な実施例においては、コンポーネント6を保護することは特に有益である。その他、据付キャビティ2を充填することは、必須の作業では全くなく、少なくとも幾つかの実施例では、段階Eを省略したり、又はもっと後の製造段階で実施することもできる。
図6A、6B及び6Cは、段階Fをそれぞれプロセスの変形例A、B及びCで実施した後の電子モジュールを示している。しかしながら、段階Fそのものは、これらの各変形例において同じ方法により実行される。段階Fでは、何らかの適切な方法を用いて導電層4から導電パターン14を形成する。導電パターン14は、例えば導電層4の導電材料を導電パターンの外側から除去することにより形成することができる。導電材料は、例えば回路板業界で広く用いられかつ周知の選択エッチング法のひとつを用いることにより除去できる。導電層4が特別な材料で形成されている場合は、例えば電磁放射により、導電材料4の導電性を導電パターンの外側から除去する方法で、導電パターン14を形成することもできる。これとは逆の反応をする材料を使用する際には、この材料を、導電パターンの領域で導電状態にする。したがって導電層4は、この方法の前段階では実際には絶縁層とし、これを特別な処置により導電性に変換させることができる。したがって導電パターン14を形成する方法は、それ自体は電子モジュールの製造に不可欠ではない。
図7A、7B及び7Cは、変形例A、B及びCとして製造プロセスの実施例を示しており、ここでは、段階Eの後で、絶縁層1の第2面1b上に導電層9を形成する。したがって図7A、7B及び7Cに示す実施例においては段階Fを省略しており、この方法においては段階Eから直接段階Gに移行する。
段階Hは、絶縁層1の第2面1bに形成した導電層9をパターン化したい場合には、段階Gの後で実施することができる。段階Hは段階Fに対応し、その差異は、段階Hにおいては、導電パターン14に加えて、絶縁層1の第2面1bに形成した導電層9から、他の導電パターン19を形成することにある。段階Hを実施した後には、電子モジュールは絶縁材料層1の両面に導電パターンを含むことになる。第2の導電パターン層により、コンポーネント6間の接続は一層多様性となる。図8A、8B及び8Cは、段階Hをそれぞれプロセスの変形例A、B及びCで実施した後の電子モジュールを示している。しかしながら、段階Fそのものは、それぞれの変形例において同じようにして実施する。
図9は多層化した電子モジュールを示しており、これは、互いの頂部に積層した3つの据付基部1と共に、コンポーネント6、並びに全部で6層の導電パターン層14及び19を具えている。据付基部1は中間層32により互いに取付けられる。中間層32は、据付基部1間に積層され、例えばプリプレグエポキシ層とすることができる。この後、接触部を形成するために、モジュールを貫通するホールを電子モジュールに穿孔する。接触部は、ホール内に成長させた導電層31により形成することができる。電子モジュールを貫通する導電層31により、据付基部1の多様な導電パターン層14及び19を互いに適切に接続して、全体的に多層化の機能を持たせることができる。
Claims (21)
- 電子モジュールを製造する方法であって、当該方法が、
− コンポーネント用の少なくとも1つの据付キャビティを有する絶縁材料層と、絶縁材料層の表面上にあって、前記据付キャビティを覆う導電層と、を具える据付基部を形成するステップと、
− 据付基部に、少なくとも1つの整列マークを形成するステップと、
− 接続表面を有し、接点領域を有するコンポーネントを用立てるステップと、
− 接続表面が導電層に面するように、コンポーネントを据付キャビティ内に位置付け、かつコンポーネントを、据付基部に形成した少なくとも1つの整列マークに対して整列させるステップと、
− コンポーネントの接点領域と、据付基部の導電層との間に、電気的な接点を形成するステップと、
− 据付基部の導電層から導電パターンを形成し、これらの導電パターンを、据付基部に形成した少なくとも1つの整列マークにより整列させるステップと、
を具えている電子モジュールの製造方法。 - 導電層及びコンポーネントの接点領域を金属とし、かつ接点領域を導電層に冶金的に接続することにより電気的な接点を形成する、請求項1に記載の方法。
- 接点領域を金属とし、かつ電気的な接点を形成する前に、導電層の頂部に金属接点バンプを成長させ、かつ接点領域を接点バンプに冶金的に接続することにより電気的な接点を形成する、請求項1に記載の方法。
- 導電層を金属とし、かつ電気的な接点を形成する前に、コンポーネントの接点領域の頂部にて金属接点バンプを成長させ、かつ接点バンプを導電層に冶金的に接続することにより電気的な接点を形成する、請求項1に記載の方法。
- 超音波又は熱圧着法を用いて、冶金的接続を無はんだで行う、請求項2〜4の何れか1項に記載の方法。
- 少なくとも1つの整列マークを、絶縁材料層、及び絶縁材料層の表面上の導電層を貫通する通し孔とする、請求項1〜5の何れか1項に記載の方法。
- 整列マークを少なくとも2つとする、請求項1〜6の何れか1項に記載の方法。
- 少なくとも1つの整列マークを、例えば金属接点バンプのような、導電層の表面に形成されるパターンとする、請求項1〜7の何れか1項に記載の方法。
- 据付基部の導電層から導電パターンを製造する前に、絶縁材料層にコンポーネントを取付ける、請求項1〜8の何れか1項に記載の方法。
- 据付キャビティを絶縁材料で充填することにより、コンポーネントを絶縁材料層に取付ける、請求項9に記載の方法。
- 据付基部の導電層から導電層の材料の一部を除去することによって導電パターンを形成し、残存する材料が導電パターンを形成する、請求項1〜10の何れか1項に記載の方法。
- 据付基部の導電層を据付基部の絶縁材料層の第1の表面上に位置させ、かつ絶縁材料層の第2の表面上に第2の導電層を形成する、請求項1〜11の何れか1項に記載の方法。
- コンポーネントを、その接点表面を第1の導電層に向けて据付キャビティ内に取付けた後に、第2の導電層を形成する、請求項12に記載の方法。
- 第2の導電層をパターン化し、導電パターンを第2の導電層から形成する、請求項12又は13に記載の方法。
- 1つ以上のコンポーネントを、対応する方法で据付基部に埋め込む、請求項1〜14の何れか1項に記載の方法。
- 据付基部に埋め込むべき各コンポーネントに対して、据付基部に個々の据付キャビティを形成し、かつ据付基部に埋め込むべき各コンポーネントをそれぞれの据付キャビティに位置付けるようにする、請求項15に記載の方法。
- 据付基部の導電層から導電パターンを形成し、その導電パターンによって、少なくとも2つのコンポーネント間に電気的な接続を形成する、請求項15又は16に記載の方法。
- 総体的な機能を実現するために、据付基部内に埋め込んだコンポーネントを、互いに電気的に接続する、請求項15〜17の何れか1項に記載の方法。
- 第1の据付基部を、少なくとも1つの第2の据付基部と共に形成し、かつ形成した据付基部を互いに積み重ねて、これらの据付基部を相対的に整列させる、請求項1〜18の何れか1項に記載の方法。
- 各据付基部の電子回路を互いに接続して総体的な機能を実現するために、互いに頂部に取付けた据付基部を経てフィードスルー用のホールを形成し、かつこうして形成したホール内に導電層を形成する、請求項19に記載の方法。
- 導電パターン層及び各コンポーネントを、互いに整列させた整列マークに対して整列させ、導電パターン層をコンポーネントに対して整列させる、請求項1〜20の何れか1項に記載の方法。
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Also Published As
Publication number | Publication date |
---|---|
WO2004077902A1 (en) | 2004-09-10 |
US7299546B2 (en) | 2007-11-27 |
US8817485B2 (en) | 2014-08-26 |
US10765006B2 (en) | 2020-09-01 |
EP1597947B1 (en) | 2011-09-14 |
US20060218782A1 (en) | 2006-10-05 |
US20100103635A1 (en) | 2010-04-29 |
FI20030292A0 (fi) | 2003-02-26 |
US20230225055A1 (en) | 2023-07-13 |
US7609527B2 (en) | 2009-10-27 |
US20080043441A1 (en) | 2008-02-21 |
US20210321520A1 (en) | 2021-10-14 |
US20180376597A1 (en) | 2018-12-27 |
US10085345B2 (en) | 2018-09-25 |
EP1597947A1 (en) | 2005-11-23 |
FI119583B (fi) | 2008-12-31 |
FI20030292A (fi) | 2004-08-27 |
US11071207B2 (en) | 2021-07-20 |
KR20050109944A (ko) | 2005-11-22 |
ATE524955T1 (de) | 2011-09-15 |
US20150043177A1 (en) | 2015-02-12 |
US20210037654A1 (en) | 2021-02-04 |
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