JP2008503076A - 電子モジュールの製造方法 - Google Patents
電子モジュールの製造方法 Download PDFInfo
- Publication number
- JP2008503076A JP2008503076A JP2007515973A JP2007515973A JP2008503076A JP 2008503076 A JP2008503076 A JP 2008503076A JP 2007515973 A JP2007515973 A JP 2007515973A JP 2007515973 A JP2007515973 A JP 2007515973A JP 2008503076 A JP2008503076 A JP 2008503076A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 68
- 239000004020 conductor Substances 0.000 claims abstract description 220
- 238000000034 method Methods 0.000 claims abstract description 109
- 239000000463 material Substances 0.000 claims abstract description 44
- 239000011810 insulating material Substances 0.000 claims description 70
- 239000000853 adhesive Substances 0.000 claims description 42
- 230000001070 adhesive effect Effects 0.000 claims description 42
- 239000000758 substrate Substances 0.000 claims description 19
- 239000000126 substance Substances 0.000 claims description 12
- 238000001465 metallisation Methods 0.000 claims description 8
- 238000004140 cleaning Methods 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 4
- 238000004026 adhesive bonding Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 243
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 20
- 239000012790 adhesive layer Substances 0.000 description 20
- 238000009434 installation Methods 0.000 description 18
- 239000010949 copper Substances 0.000 description 17
- 229910052802 copper Inorganic materials 0.000 description 14
- 239000010408 film Substances 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 11
- 229920000642 polymer Polymers 0.000 description 8
- 238000011049 filling Methods 0.000 description 7
- 229920006254 polymer film Polymers 0.000 description 7
- 239000011889 copper foil Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000000945 filler Substances 0.000 description 4
- 239000011888 foil Substances 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 239000011230 binding agent Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000010030 laminating Methods 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 229920000106 Liquid crystal polymer Polymers 0.000 description 2
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000009412 basement excavation Methods 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000002848 electrochemical method Methods 0.000 description 2
- 230000005670 electromagnetic radiation Effects 0.000 description 2
- 239000003365 glass fiber Substances 0.000 description 2
- 238000010329 laser etching Methods 0.000 description 2
- 239000000615 nonconductor Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000003223 protective agent Substances 0.000 description 2
- 239000007858 starting material Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 239000004760 aramid Substances 0.000 description 1
- 229920003235 aromatic polyamide Polymers 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- -1 polytetrafluoroethylene Polymers 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000010187 selection method Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
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- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
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- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/82009—Pre-treatment of the connector or the bonding area
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- H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
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- H01L2224/8312—Aligning
- H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/83132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
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- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
- H05K3/025—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates by transfer of thin metal foil formed on a temporary carrier, e.g. peel-apart copper
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49133—Assembling to base an electrical component, e.g., capacitor, etc. with component orienting
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor
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Abstract
Description
段階Aにおいて、適切な導体層4をプロセス用の出発材料として選択する。導体層4が支持基材12の表面上に配置された層状シートも、出発材料として選択することができる。層状シートは、例えば、処理に適した支持ベース12を使用し、適切な導体膜をこの支持ベース12の表面上に取り付けることによって製造することができる。
接点開口17を、構成要素の電気接点に必要なバイアから作製する。接点開口17は、例えばレーザによりまたは機械的な掘削により、導体層4を貫いて作製される。図示した実施例において、接点開口17は、導体層の第1表面の方向から掘削されて、支持層12の材料まで延びる。図示される実施例において、位置合わせを手助けすべく使用することのできるバイア3が、接点開口17に加えて形成される。
段階Cにおいて、接着剤層5を、導体層4上の、構成要素6が取り付けられる領域内に塗布する。これらの領域を結合領域と呼ぶことができる。接着剤層5は、例えば、接点開口17を用いて位置合わせすることができる。接着剤層の厚さは、構成要素6を接着剤層5に押し付けたときに、接着剤が構成要素6と導体層4との間の空間を完全に充たすように選択する。構成要素6が接触突起7を含む場合、構成要素6と導体層4との間の空間が充分に充たされるには、接着剤層5の厚さは接触突起7の高さよりも例えば約1.1〜10倍大きくすべきである。構成要素6用に形成される接着剤層5の表面積は、構成要素6の対応する表面領域よりもやや大きくすることもでき、これによって不適切な充填の恐れも低減される。
段階Dにおいて、構成要素6を電子モジュール内の定位置に設定する。これは、例えば組立機械の支援により構成要素6を接着剤層5に押し付けることによって行うことができる。組立段階において、接点開口17を用いて構成要素6を正確に位置合わせすることができる。より概略的な位置合わせでは、バイア3または他の利用可能な位置合わせマークが基板に作製されていれば、これらを使用することもできる。
導体層4に接着される構成要素6用の既製の孔2または凹部がすでに設けられた絶縁材料層1を、絶縁材料層4の上に配置する。絶縁材料層1は適切なポリマーベースから製造することができ、構成要素6の寸法および位置に応じて適切に選択された孔穴または凹部が、何れかの適切な方法を使用することによってこの絶縁材料層1に作製される。ポリマーベースは、例えば、回路基板産業において知られ広く使用されているプリプレグベースにすることができる。絶縁材料層1の代わりとなる材料については、段階2Aと関連づけてより詳細に説明する。
段階Fにおいて、パターン化されていないの絶縁材料層11を絶縁材料層1上に設定し、その後導体層9をその上に設定する。絶縁材料層1と同様に、絶縁材料層11は、適切なポリマー膜、例えば上述のプリプレグベースから製造することができる。導体層9は、例えば銅箔や目的に適した何れかの膜にすることができる。
この段階において、(層1および11にある)ポリマーが、導体層4および9の間にある構成要素6の周りにおいて一体化された密な層を形成するように、層1、11および9を熱および圧力を用いて加圧する。この手順は、第2導体層9を非常に均一かつ平坦にする。
この段階において、支持ベース12を分離し、あるいは構造から除去する。除去は、例えば、機械的にまたはエッチングによって行うことができる。当然、支持ベース12を使用しない実施例では、段階Hを省略することができる。
適切な方法の使用、例えば化学的に、あるいはレーザによってまたはプラズマエッチングによって接点開口17から接着剤を洗浄除去する。同時に、接点開口17の「底」に位置する、構成要素の接触領域7が洗浄される。一部の実施例では、洗浄を省略することができる。
段階Iでは、接点開口17内で導体材料が成長する。プロセスの例では、導体材料はベース上の他の部分でも同時に成長し、従って、絶縁層4および9の厚さも増加する。所望すれば、孔3内で導体材料を成長させることもできる。
段階Kにおいて、所望の導体パターン14および19を、ベースの表面の導体層4および9から作製する。導体層4のみが使用される実施例では、パターンはベースの一方の側のみに作製する。第2導体層9が使用される実施例でも、導体層4からのみ導体パターンを作製することによって進めることもできる。このような実施例では、パターン化されていない導体層9は例えば、機械的に電子モジュールを支持または保護する層として、あるいは電磁放射に対する保護として作用することができる。
電子モジュールの製造プロセス用に適切な絶縁材料シート1を選択し、このシートから設置ベースの本体を形成する。単一の絶縁材料層を使用する実施例において、絶縁材料層1の厚さは、好適には取り付けられる構成要素の厚さよりも大きくなければならない。これにより、構成要素を完全に設置ベースの内部に埋め込むことができ、一方、電子モジュールはその両側に平坦な表面を有することになる。もちろん、より厚い特別な構成要素であって、その表面が絶縁材料層1外に延びるものも、設置ベース内に埋め込むことができる。これは、複数の絶縁材料層を使用し、プロセス中にこれらの材料層を一緒に結合する実施例では、好ましい手順である。絶縁材料層全体の厚さが構成要素の厚さを上回る場合には、その後、構成要素を構造内に完全に埋め込むことができる。これは、構成の耐久性のため、電子モジュールの構成要素が完全に設置ベースの内部に配置されることが好ましいからである。
何らかの適切な方法を使用することにより、導体層4に孔を形成する。孔は、例えばレーザによる気化や、選択的エッチング方法といった、回路基板産業で広く使用されかつよく知られた方法によって作製することができる。作製された孔は、構成要素の電気接点に必要なバイア用の接点開口17、および構成要素の設置凹部2を製造するための開口部12となる。さらに、必要に応じて、バイアの製造用の孔13を形成することができる。孔穴12、13、17は、絶縁材料層1の表面を露出させることによって形成する。
基板に埋め込まれる構成要素にとって適切な寸法および形状を有する凹部2を絶縁材料層1内に形成する。凹部2は、例えば回路基板産業において使用される何れかの既知の方法を使用することによって、適切に形成することができる。凹部2は、例えばCO2レーザアブレーション方法、化学エッチングまたは機械的なミリングによって形成することができる。凹部2は、第2表面1bの方向から形成されるとともに、絶縁材料層1全体を通って、層の逆側の表面上にある導体材料層4の表面1aに向けて真っ直ぐ延びる。
電子モジュールブランクを裏返しにする。
表面1aの方向から、構成要素用の追加的な設置凹部2を絶縁材料層1内に作製する。あるいは、凹部2は段階2Cの方法によって作製することができる。凹部2を化学的なエッチングによって形成する場合、凹部2は、双方の表面に同時に形成することができる。
構成要素6が取り付けられるべき領域において、接合層5を導体層4に塗布する。これらの領域は、結合領域と呼ぶることができる。実際には、結合領域は、凹部2の「底」に設置される。接合層の厚さは、構成要素6が接合層5に押し付けられたときに、接着剤が構成要素6と導体層4との間の空間を完全に充たすように選択する。構成要素6が接触突起7を含む場合、構成要素6と導体層4との間の空間が充分に充たされるためには、接着剤層5の厚みは接触突起7の高さよりも例えば約1.5〜10倍大きくすべきである。構成要素6用に形成される接着剤層5の表面積は、構成要素6の対応する表面領域よりもやや大きくすることもでき、これによって不適切な充填の恐れも低減される。
表面1aの方向から、構成要素6を電子モジュール内の定位置に設定する。これは、例えば組立機械の支援により構成要素6を接着剤層5に押し付けることによって行うことができる。段階Dで説明したように、接点開口17により構成要素6を正確に位置合わせすることができる。
電子モジュールブランクを裏返しにする(段階2D参照)。
第2表面1b上に開口した設置凹部2の底に、接着剤層5を塗布する。段階2Iは、段階2Fと同様ではあるが、電子モジュールの逆側の表面の方向から実行される。
段階Jにおいて、段階2Gと同様に、表面1bの方向から構成要素6を電子モジュール内の定位置に設定する。
段階Kにおいて、構成要素6と設置ベースの間に残った空間を、充填剤8、例えば何らかの適切なポリマーで完全に充たす。
適切な方法の使用、例えば化学的に、あるいはレーザによってまたはプラズマエッチングによって接点開口17から接着剤を洗浄除去する。同時に、接点開口17の「底」に位置する、構成要素の接触領域7が洗浄される。
他の孔、例えばバイア用の、絶縁材料層1を貫通する孔11を作製したい場合、段階2Mを実行する。
接点開口17内で導体材料が成長する。プロセスの例では、導体材料はベース上の他の部分でも同時に成長し、従って、絶縁層4の厚さも増加する。所望すれば、孔11内でも導体材料を成長させることができる。
段階2Oにおいて、導体パターン14が基板1の両面に形成されるように、導体層4をパターン化(パターニング)する。パターン化は、例えば段階Kに記述した方法で実行できる。
基板1の両面上に絶縁材料層21を作製し、絶縁材料層21の表面上に導体層24を作製する。段階2Pは、例えば、適切なRCF膜を基板1の両面上に押し付けることによって実行する。その後、RCF膜は、絶縁材料層21および導体層24を含む。RCF膜が熱および圧力によって押し付けられると、RCF膜および層21のポリマーが導体層14と24との間に、一体化された高密度の絶縁材料層を形成する。この手順によって、導体層24も、非常に均一にかつ平坦になる。
段階Qにおいて、導体層14と24との間にバイアを作製するための孔27を作製する。孔は、例えば、レーザによって作製することができる。
段階2Rでは、孔27内で導体材料が成長し、同時に導体層24も厚くなる。段階2Rは、段階2Nと同様に実行することができる。
Claims (13)
- 導体パターン層(14)に電気的に接続される構成要素(6)を含む電子モジュールを製造する方法において、
導体層(4)内に接点開口(17)を作製するステップであって、前記接点開口どうしの位置関係が、前記構成要素(6)の接触領域(7)どうしの位置関係に対応するステップと、
前記構成要素(6)の前記接触領域(7)が前記接点開口(17)の位置に来る方法で、前記構成要素(6)と前記導体層(4)とを互いに位置合わせして、前記構成要素(6)を固定するステップと、
前記構成要素(6)を前記導体層(4)に接続する導体材料を、少なくとも前記接点開口(17)内および前記構成要素(6)の接触領域(7)に設けるステップと、
前記導体層(4)をパターン化して前記導体パターン層(14)を形成するステップと
を具えていることを特徴とする電子モジュールの製造方法。 - 前記接点開口(17)を、パターン化されていない導体層(4)内に作製することを特徴とする請求項1に記載の方法。
- 前記接点開口(17)を作製する際に、前記導体層(4)の第2表面上に支持層(12)が存在することを特徴とする請求項1または2に記載の方法。
- 前記接点開口(17)を前記導体層(4)の第1表面の方向から作製して、前記接点開口(17)を前記支持層(12)まで延在させ、前記構成要素(6)を前記導体層に接続する前に、前記支持層(12)を除去するか、または薄くすることによって、前記接点開口を露出させることを特徴とする請求項3に記載の方法。
- 絶縁接着剤(5)を用いて、前記構成要素を前記導体層に取り付けることを特徴とする請求項1〜4の何れかに記載の方法。
- 前記構成要素を接着した後に、かつ前記導体材料を前記構成要素の前記接触領域に設ける前に、
前記接点開口および前記構成要素の前記接触領域を、前記接点開口を通して洗浄するステップを具えていることを特徴とする請求項5に記載の方法。 - 前記構成要素を前記導体層に接続する前記導体材料を、化学的および/または電気化学的メタライゼーション法を用いて設けることを特徴とする請求項1〜6の何れかに記載の方法。
- 前記導体層が、第1表面(1a)および第2表面(1b)を有する基板内に含まれ、前記基板は、前記第1表面(1a)と前記第2表面(1b)との間に絶縁材料層(1)を含むとともに、少なくとも前記第1表面(1a)上に前記導体層(4)を含み、
前記方法が、前記構成要素(6)用の少なくとも1つの凹部(2)を前記基板(1)内に作製するステップであって、前記凹部(2)は、前記第2表面(1b)および前記絶縁材料層(1)を通って前記第1表面(1a)上の前記導体層(4)まで延在し、前記導体層(4)は、前記第1表面(1a)の方向から前記凹部(2)を覆うステップを具え、
この場合に、前記接点開口(17)を、前記導体層(4)内の前記凹部(2)の底に作製することを特徴とする請求項1〜7の何れかに記載の方法。 - 前記構成要素(6)を、前記第1表面(1a)および前記第2表面(1b)に共に対向する前記絶縁材料層(1)内に配置し、前記構成要素(6)の少なくとも一部を前記第1表面(1a)上の前記導体層(4)に接続し、かつ前記構成要素(6)の少なくとも一部を前記第2表面(1b)上の前記導体層(4)に接続する方法で、前記構成要素(6)への電気接点を形成することを特徴とする請求項8に記載の方法。
- 前記構成要素が取り付けられる前記導体層(4)の前記第1表面がむき出し面であり、前記構成要素(6)の取り付け後に、
前記導体層(4)に接着された前記構成要素(6)を包囲する絶縁材料層(1)を、前記導体層(4)の前記第1表面上に作製するステップを具えていることを特徴とする請求項1〜7の何れかに記載の方法。 - 前記絶縁材料層(1)の逆側の表面上に第2導体層を作製することを特徴とする請求項10に記載の方法。
- 2つ以上の前記構成要素(6)を電子モジュール内に埋め込み、埋め込まれた前記構成要素(6)を相互に電気的に接続して動作系全体を構成することを特徴とする請求項1〜11の何れかに記載の方法。
- 前記導体層(4)に取り付けるべき少なくとも1つの前記構成要素が、封止されていない微小回路チップである請求項1〜12の何れか一項に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FI20040827A FI117814B (fi) | 2004-06-15 | 2004-06-15 | Menetelmä elektroniikkamoduulin valmistamiseksi |
FI20040827 | 2004-06-15 | ||
PCT/FI2005/000274 WO2005125298A2 (en) | 2004-06-15 | 2005-06-13 | Method for manufacturing an electronics module comprising a component electrically connected to a conductor- pattern layer |
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US8225503B2 (en) | 2008-02-11 | 2012-07-24 | Ibiden Co., Ltd. | Method for manufacturing board with built-in electronic elements |
WO2014041627A1 (ja) * | 2012-09-12 | 2014-03-20 | 株式会社メイコー | 部品内蔵基板の製造方法 |
JP2014107553A (ja) * | 2012-11-29 | 2014-06-09 | Samsung Electro-Mechanics Co Ltd | 電子部品組込み基板及びその製造方法 |
US9425122B2 (en) | 2012-12-21 | 2016-08-23 | Panasonic Intellectual Property Management Co., Ltd. | Electronic component package and method for manufacturing the same |
US9449944B2 (en) | 2012-12-21 | 2016-09-20 | Panasonic Intellectual Property Management Co., Ltd. | Electronic component package and method for manufacturing same |
US9595651B2 (en) | 2012-12-21 | 2017-03-14 | Panasonic Intellectual Property Management Co., Ltd. | Electronic component package and method for manufacturing same |
US9825209B2 (en) | 2012-12-21 | 2017-11-21 | Panasonic Intellectual Property Management Co., Ltd. | Electronic component package and method for manufacturing the same |
JP2015050309A (ja) * | 2013-08-31 | 2015-03-16 | 京セラサーキットソリューションズ株式会社 | 配線基板の製造方法 |
Also Published As
Publication number | Publication date |
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JP4796057B2 (ja) | 2011-10-19 |
US8240032B2 (en) | 2012-08-14 |
KR101034279B1 (ko) | 2011-05-16 |
FI117814B (fi) | 2007-02-28 |
WO2005125298A2 (en) | 2005-12-29 |
CN101010994A (zh) | 2007-08-01 |
DE112005001414T5 (de) | 2007-05-03 |
FI20040827A0 (fi) | 2004-06-15 |
CN101010994B (zh) | 2012-11-07 |
KR20070030838A (ko) | 2007-03-16 |
US20080261338A1 (en) | 2008-10-23 |
FI20040827A (fi) | 2005-12-16 |
WO2005125298A3 (en) | 2006-10-26 |
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