KR100895568B1 - 리세스된 액세스 디바이스 형성 방법 - Google Patents
리세스된 액세스 디바이스 형성 방법 Download PDFInfo
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- KR100895568B1 KR100895568B1 KR1020077021689A KR20077021689A KR100895568B1 KR 100895568 B1 KR100895568 B1 KR 100895568B1 KR 1020077021689 A KR1020077021689 A KR 1020077021689A KR 20077021689 A KR20077021689 A KR 20077021689A KR 100895568 B1 KR100895568 B1 KR 100895568B1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
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Abstract
Description
Claims (47)
- 삭제
- 반도체 구조에 관련된 리세스된 액세스 디바이스들을 형성하는 방법으로서,반도체 기판을 제공하는 단계;상기 기판 내에 리세스된 액세스 디바이스의 트렌치들을 형성하는 단계;상기 리세스된 액세스 디바이스의 트렌치들에 제1 전기적 절연 재료를 채우는 단계;상기 제1 전기적 절연 재료를 복수의 액세스 디바이스 영역들을 정의하는 마스크로 패터닝하는 단계 - 상기 액세스 디바이스 영역들은 아이솔레이션 영역에 의해 둘러싸인 섬모양이며, 상기 액세스 디바이스 영역들은 상기 리세스된 액세스 디바이스의 트렌치들의 일부만을 포함함 - ;상기 아이솔레이션 영역의 기판으로 에칭하여 상기 아이솔레이션 영역의 기판을 리세스하는 단계;상기 리세스된 기판을 제2 전기적 절연 재료로 피복하여 상기 아이솔레이션 영역을 상기 제2 전기적 절연 재료로 채우는 단계;상기 아이솔레이션 영역 내의 상기 제2 전기적 절연 재료를 남겨두면서 상기 제1 전기적 절연 재료를 제거하는 단계; 및상기 제1 전기적 절연 재료를 제거한 후, 상기 액세스된 디바이스 영역들이 포함하는 상기 리세스된 액세스 디바이스의 트렌치들의 일부 내에 게이트 재료를 형성하는 단계를 포함하는 방법.
- 제2항에 있어서,상기 리세스된 기판을 상기 제2 전기적 절연 재료로 피복하는 단계는,상기 아이솔레이션 영역의 리세스된 기판 위 및 상기 제1 전기적 절연 재료 위에 상기 제2 전기적 절연 재료를 형성하는 단계; 및상기 아이솔레이션 영역의 리세스된 기판 위에 상기 제2 전기적 절연 재료를 남기면서, 상기 제1 전기적 절연 재료 위의 상기 제2 전기적 절연 재료를 제거하도록 상기 제2 전기적 절연 재료를 평탄화(planarizing)하는 단계에 의해 수행되는 방법.
- 제2항에 있어서,상기 리세스된 디바이스 영역들의 게이트 재료와 관련된 소스/드레인 영역들을 형성하는 단계를 더 포함하며,상기 게이트 재료는, 소스/드레인 영역들의 쌍들과 전기적으로 상호 접속하는 게이트들을 포함하며, 쌍을 이룬 소스/드레인 영역들 중 적어도 일부는 비트라인 컨택트(bitline contact) 및 스토리지 노드 컨택트(storage node contact)를 포함하고, DRAM 디바이스들에 포함되는 방법.
- 반도체 구조에 관련된 리세스된 액세스 디바이스들을 형성하는 방법으로서,반도체 기판을 제공하는 단계;상기 기판 위에 제1 패터닝 마스크를 형성하는 단계 - 상기 제1 패터닝 마스크는 상기 제1 패터닝 마스크를 통해 연장되어 리세스된 액세스 디바이스들의 트렌치들에 대한 제1 위치들을 정의하는 개구들을 가짐 - ;상기 제1 위치들을 통해 상기 기판을 에칭하여 상기 기판으로 연장되는 리세스된 액세스 디바이스의 트렌치들을 형성하는 단계;상기 리세스된 액세스 디바이스의 트렌치들을 게이트 재료로 채우는 단계;상기 제1 패터닝 마스크의 위 및 상기 게이트 재료의 위에 제1 전기적 절연 재료를 형성하는 단계;복수의 액세스 디바이스 영역들을 정의하는 마스크로 상기 제1 전기적 절연 재료를 패터닝하는 단계 - 상기 액세스 디바이스 영역들은 아이솔레이션 영역에 의해 둘러싸인 섬모양이며, 상기 액세스 디바이스 영역들은 상기 리세스된 액세스 디바이스의 트렌치들의 일부만을 포함함 - ;상기 아이솔레이션 영역의 기판으로 에칭하여 상기 아이솔레이션 영역의 기판을 리세스하는 단계 - 상기 에칭은 또한 액세스 디바이스 영역들 내의 게이트 재료를 남기면서 상기 액세스 디바이스 영역들 사이로부터 게이트 재료를 제거함 - ;상기 리세스된 기판을 제2 전기적 절연 재료로 피복하여 상기 아이솔레이션 영역을 상기 제2 전기적 절연 재료로 채우는 단계;상기 아이솔레이션 영역 내의 상기 제2 전기적 절연 재료를 남겨두면서 상기 제1 전기적 절연 재료를 제거하는 단계; 및상기 제1 전기적 절연 재료를 제거한 후, 복수의 도전성 라인들을 형성하는 단계 - 개개의 도전성 라인들은 다수의 액세스 디바이스 영역들에 걸쳐 연장되며, 다수의 액세스 디바이스 영역들의 게이트 재료를 전기적으로 상호 접속함 -를 포함하는 방법.
- 제5항에 있어서,상기 리세스된 액세스 디바이스의 트렌치들을 게이트 재료로 채우는 단계는,상기 제1 패터닝 마스크를 피복하고 상기 트렌치들 내에 존재하도록 게이트 재료를 형성하는 단계; 및상기 리세스된 액세스 디바이스의 트렌치들 내에 상기 게이트 재료를 남기면서 상기 제1 패터닝 마스크의 위로부터 상기 게이트 재료를 제거하도록 상기 게이트 재료를 평탄화하는 단계를 포함하는 방법.
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US11/090,529 | 2005-03-25 | ||
US11/090,529 US7384849B2 (en) | 2005-03-25 | 2005-03-25 | Methods of forming recessed access devices associated with semiconductor constructions |
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KR100895568B1 true KR100895568B1 (ko) | 2009-04-29 |
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EP (2) | EP1880421B1 (ko) |
JP (1) | JP4962874B2 (ko) |
KR (1) | KR100895568B1 (ko) |
CN (1) | CN100536142C (ko) |
AT (1) | ATE533183T1 (ko) |
TW (1) | TWI314769B (ko) |
WO (1) | WO2006104654A1 (ko) |
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