JP2008171863A - トレンチゲートの形成方法 - Google Patents
トレンチゲートの形成方法 Download PDFInfo
- Publication number
- JP2008171863A JP2008171863A JP2007001199A JP2007001199A JP2008171863A JP 2008171863 A JP2008171863 A JP 2008171863A JP 2007001199 A JP2007001199 A JP 2007001199A JP 2007001199 A JP2007001199 A JP 2007001199A JP 2008171863 A JP2008171863 A JP 2008171863A
- Authority
- JP
- Japan
- Prior art keywords
- trench
- gate
- element isolation
- silicon substrate
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 19
- 238000002955 isolation Methods 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 239000007772 electrode material Substances 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 35
- 229910052710 silicon Inorganic materials 0.000 abstract description 35
- 239000010703 silicon Substances 0.000 abstract description 35
- 239000000463 material Substances 0.000 abstract description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 21
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 21
- 229910052721 tungsten Inorganic materials 0.000 description 17
- 239000010937 tungsten Substances 0.000 description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 229910052814 silicon oxide Inorganic materials 0.000 description 16
- 238000004519 manufacturing process Methods 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 9
- -1 tungsten nitride Chemical class 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
Abstract
【解決手段】まずシリコン基板10上にゲートトレンチ10aを形成し、次いでゲートトレンチ10aが形成されたシリコン基板10上に素子分離領域16aを形成する。そのため、ゲートトレンチ10a内にシリコン基板材料のバリが発生することがなく、理想的なトレンチ形状を得ることができる。
【選択図】図8
Description
10a トレンチ(ゲートトレンチ)
10b 素子分離用溝
10c 凹部
11 シリコン酸化膜
12 シリコン窒化膜
12a 開口パターン
14 シリコン酸化膜
15 シリコン窒化膜
16 シリコン酸化膜
16a 素子分離領域
17 活性領域
18 ゲート酸化膜
19 ポリシリコン膜
19a ポリシリコン膜
20 窒化タングステン膜
20a 窒化タングステン膜
21 タングステン膜
21a タングステン膜
22 シリコン窒化膜
22a ゲートキャップ絶縁膜
23 LDD領域
24 サイドウォール絶縁膜
25 ソース/ドレイン領域
26 層間絶縁膜
27 セルコンタクトプラグ
40 シリコン基板
41 活性領域
42 素子分離領域
42x 素子分離領域42の突き出し部分
42y 子分離領域42の側面と接する部分
43 ゲートトレンチ
44a ゲート電極
44b ゲート電極
100 セルトランジスタ
Claims (4)
- 半導体基板上にゲートトレンチを形成する工程と、
前記ゲートトレンチが形成された前記半導体基板上に素子分離領域を形成する工程とを備えることを特徴とするトレンチゲートの形成方法。 - 前記ゲートトレンチを形成した後であって前記素子分離領域を形成する前に、前記ゲートトレンチ内をチャネルドープする工程をさらに備えることを特徴とする請求項1に記載のトレンチゲートの形成方法。
- 前記ゲートトレンチの内壁にゲート酸化膜を形成する工程と、前記ゲートトレンチ内にゲート電極材料を埋設する工程とをさらに備えることを特徴とする請求項1又は2に記載のトレンチゲートの形成方法。
- 前記素子分離領域をSTI法により形成することを特徴とする請求項1乃至3のいずれか一項に記載のトレンチゲートの形成方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007001199A JP2008171863A (ja) | 2007-01-09 | 2007-01-09 | トレンチゲートの形成方法 |
US11/969,506 US20080166864A1 (en) | 2007-01-09 | 2008-01-04 | Method for forming trench gate and method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007001199A JP2008171863A (ja) | 2007-01-09 | 2007-01-09 | トレンチゲートの形成方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2008171863A true JP2008171863A (ja) | 2008-07-24 |
Family
ID=39594668
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007001199A Pending JP2008171863A (ja) | 2007-01-09 | 2007-01-09 | トレンチゲートの形成方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US20080166864A1 (ja) |
JP (1) | JP2008171863A (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009105227A (ja) * | 2007-10-23 | 2009-05-14 | Elpida Memory Inc | 半導体装置及びその製造方法並びにデータ処理システム |
JP2010157673A (ja) * | 2008-12-30 | 2010-07-15 | Hynix Semiconductor Inc | 半導体素子およびその製造方法 |
US9127017B2 (en) | 2011-05-25 | 2015-09-08 | American Dye Source, Inc. | Compounds with oxime ester and/or acyl groups |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101095787B1 (ko) * | 2009-07-28 | 2011-12-21 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 형성방법 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06140597A (ja) * | 1992-03-19 | 1994-05-20 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
JPH11274478A (ja) * | 1998-02-17 | 1999-10-08 | Internatl Business Mach Corp <Ibm> | 隆起したソ―ス及びドレインを有する高性能mosfet素子 |
JP2006173429A (ja) * | 2004-12-17 | 2006-06-29 | Elpida Memory Inc | 半導体装置の製造方法 |
WO2006104654A1 (en) * | 2005-03-25 | 2006-10-05 | Micron Technology, Inc. | Methods of forming recessed access devices |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6583060B2 (en) * | 2001-07-13 | 2003-06-24 | Micron Technology, Inc. | Dual depth trench isolation |
US6833602B1 (en) * | 2002-09-06 | 2004-12-21 | Lattice Semiconductor Corporation | Device having electrically isolated low voltage and high voltage regions and process for fabricating the device |
KR100546378B1 (ko) * | 2003-09-09 | 2006-01-26 | 삼성전자주식회사 | 리세스 채널을 가지는 트랜지스터 제조 방법 |
JP4552603B2 (ja) * | 2004-11-08 | 2010-09-29 | エルピーダメモリ株式会社 | 半導体装置の製造方法 |
KR100791342B1 (ko) * | 2006-08-09 | 2008-01-03 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
-
2007
- 2007-01-09 JP JP2007001199A patent/JP2008171863A/ja active Pending
-
2008
- 2008-01-04 US US11/969,506 patent/US20080166864A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06140597A (ja) * | 1992-03-19 | 1994-05-20 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
JPH11274478A (ja) * | 1998-02-17 | 1999-10-08 | Internatl Business Mach Corp <Ibm> | 隆起したソ―ス及びドレインを有する高性能mosfet素子 |
JP2006173429A (ja) * | 2004-12-17 | 2006-06-29 | Elpida Memory Inc | 半導体装置の製造方法 |
WO2006104654A1 (en) * | 2005-03-25 | 2006-10-05 | Micron Technology, Inc. | Methods of forming recessed access devices |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009105227A (ja) * | 2007-10-23 | 2009-05-14 | Elpida Memory Inc | 半導体装置及びその製造方法並びにデータ処理システム |
JP2010157673A (ja) * | 2008-12-30 | 2010-07-15 | Hynix Semiconductor Inc | 半導体素子およびその製造方法 |
US9127017B2 (en) | 2011-05-25 | 2015-09-08 | American Dye Source, Inc. | Compounds with oxime ester and/or acyl groups |
US9382259B2 (en) | 2011-05-25 | 2016-07-05 | American Dye Source, Inc. | Compounds with oxime ester and/or acyl groups |
Also Published As
Publication number | Publication date |
---|---|
US20080166864A1 (en) | 2008-07-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4773169B2 (ja) | 半導体装置の製造方法 | |
US7728373B2 (en) | DRAM device with cell epitaxial layers partially overlap buried cell gate electrode | |
JP4552603B2 (ja) | 半導体装置の製造方法 | |
KR100625795B1 (ko) | 반도체 소자의 게이트 및 그 형성방법 | |
KR100763337B1 (ko) | 매립 게이트 라인을 갖는 반도체소자 및 그 제조방법 | |
JP2006339476A (ja) | 半導体装置及びその製造方法 | |
US7842594B2 (en) | Semiconductor device and method for fabricating the same | |
JP5234886B2 (ja) | 半導体装置の製造方法 | |
JP2006303451A (ja) | 半導体装置及び半導体装置の製造方法 | |
JP2007158269A (ja) | 半導体装置及びその製造方法 | |
JP4552908B2 (ja) | 半導体装置の製造方法 | |
JP5718585B2 (ja) | 半導体装置及びその製造方法、並びにデータ処理システム | |
US7692251B2 (en) | Transistor for semiconductor device and method of forming the same | |
JP2008091905A (ja) | FinFETを備えた半導体素子の製造方法 | |
JP2011159760A (ja) | 半導体装置の製造方法及び半導体装置 | |
US8748978B2 (en) | Sense-amp transistor of semiconductor device and method for manufacturing the same | |
JP4600834B2 (ja) | 半導体装置の製造方法 | |
JP2009158813A (ja) | 半導体装置の製造方法、及び半導体装置 | |
JP2008166747A (ja) | 半導体素子の製造方法 | |
JP2005183954A (ja) | 窪んだゲート電極の形成方法 | |
JP2008171863A (ja) | トレンチゲートの形成方法 | |
JP5538672B2 (ja) | 半導体装置及びその製造方法並びにデータ処理システム | |
US8658491B2 (en) | Manufacturing method of transistor structure having a recessed channel | |
US8455309B2 (en) | Method for manufacturing a semiconductor device | |
JP2009009988A (ja) | 半導体装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080512 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090427 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090512 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090710 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20100622 |