JPWO2012144271A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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Abstract
Description
図1は本発明の実施形態1に係る半導体装置の構成を示す図である。図1に示す実施形態1の半導体装置は、炭化珪素の半導体基板を用いてMOSFETとダイオードを備えて構成されている。図1において、炭化珪素のN型高濃度(N+ 型)の半導体基板101の一方の主面には、炭化珪素からなるN型低濃度(N− 型)のエピタキシャル層で構成されたドリフト領域102が形成されている。
図3は本発明の実施形態2に係る半導体装置の構成を示す断面図である。
図5〜図8は本発明の実施形態3に係る半導体装置の平面方向(半導体基板の主面方向)のレイアウトを示す平面図である。
図9〜図11は本発明の実施形態4に係る半導体装置の平面方向(半導体基板の主面方向)のレイアウトを示す平面図である。
Claims (12)
- 半導体基板と、
前記半導体基板の一方の主面上に形成された第1導電型のドリフト領域と、
前記ドリフト領域内に形成された第2導電型のウェル領域と、
前記ウェル領域内に形成された第1導電型のソース領域と、
前記ソース領域ならびに前記ウェル領域を貫通して前記ドリフト領域に至る深さの溝と、
ゲート絶縁膜を介して前記溝の側部に形成されたゲート電極と、
前記ウェル領域および前記ソース領域に接続されたソース電極と、
前記半導体基板の他方の主面に接続されたドレイン電極と、
前記ゲート電極上に形成されて前記ゲート電極を被覆する層間絶縁膜と、
前記溝の底部または前記溝の直下の前記ドリフト領域内に形成されたアノード領域と、
前記溝内に前記アノード領域に至る深さに形成されたコンタクトホールと、
前記コンタクトホールの内壁側面に前記ゲート電極と接して形成された内壁絶縁膜とを有し、
前記ソース電極は、前記内壁絶縁膜を介して前記コンタクトホールに埋設され、前記内壁絶縁膜で前記ゲート電極と絶縁された状態で前記アノード領域と電気的に接続されている
ことを特徴とする半導体装置。 - 前記アノード領域は、前記ドリフト領域内に第2導電型の領域として形成され、前記ドリフト領域との接合面で前記ドリフト領域をカソードとするPN接合型のダイオードを構成する
ことを特徴とする請求項1に記載の半導体装置。 - 前記アノード領域は、前記溝の底部に前記ドリフト領域の材料とは異なる異種材で形成され、前記ドリフト領域との接合面でユニポーラ型のダイオードを構成する
ことを特徴とする請求項1に記載の半導体装置。 - 前記アノード領域は、前記ドリフト領域とバンドギャップが異なる半導体で形成されている
ことを特徴とする請求項3に記載の半導体装置。 - 前記コンタクトホールは、前記半導体基板の主面方向に対して前記溝内に離散的に複数形成され、前記コンタクトホールが形成された部分の前記溝の幅は、前記コンタクトホールが形成されていない部分の前記溝の幅よりも広い
ことを特徴とする請求項1〜4の何れか1項に記載の半導体装置。 - 前記溝は、前記半導体基板の主面方向に対して直線状に複数本形成され、前記コンタクトホールは、前記半導体基板の主面方向に対して前記溝内に離散的に複数形成され、隣り合う前記溝に形成された前記コンタクトホールは、互い違いに非対向して配置形成されている
ことを特徴とする請求項5に記載の半導体装置。 - 前記溝は、前記半導体基板の主面方向に対して網目状に形成され、前記コンタクトホールは、前記溝の網目の交点に離散的に複数配置形成されている
ことを特徴とする請求項1〜4の何れか1項に記載の半導体装置。 - 前記溝は、前記半導体基板の主面方向に対して直線状に形成され、前記コンタクトホールは、前記溝内に沿って直線状に形成されている
ことを特徴とする請求項1〜4の何れか1項に記載の半導体装置。 - 前記溝は、前記半導体基板の主面方向に対して網目状に形成され、前記コンタクトホールは、前記溝内に沿って網目状に形成されている
ことを特徴とする請求項1〜4の何れか1項に記載の半導体装置。 - 半導体基板の一方の主面上に第1導電型のドリフト領域を形成する第1の工程と、
前記ドリフト領域内に第2導電型のウェル領域を形成する第2の工程と、
前記ウェル領域内に第1導電型のソース領域を形成する第3の工程と、
前記ソース領域ならびに前記ウェル領域を貫通して前記ドリフト領域に至る深さの溝を形成する第4の工程と、
絶縁膜を介して前記溝内にゲート電極を形成する第5の工程と、
前記溝の底部または前記溝の直下の前記ドリフト領域内に、前記ドリフト領域をカソードとするダイオードのアノード領域を形成する第6の工程と、
前記ゲート電極に前記アノード領域の表面を露出させるコンタクトホールを形成する第7の工程と、
内壁絶縁膜で前記ゲート電極と絶縁された状態で前記アノード領域と電気的に接続されるソース電極を前記コンタクトホールに埋設形成する第8の工程と
を有することを特徴とする半導体装置の製造方法。 - 前記ゲート電極の上面を被覆する絶縁膜を形成する工程を備え、
前記ゲート電極の上面を被覆する絶縁膜の厚さは、前記コンタクトホールの底面に形成されて前記コンタクトホールを形成する第7の工程で選択的に除去される絶縁膜の厚さよりも厚く形成する
ことを特徴とする請求項10に記載の半導体装置の製造方法。 - 前記第7の工程は、前記コンタクトホールの底部に形成された絶縁膜を選択的に除去する工程を含み、異方性エッチングにより前記内壁絶縁膜を残した状態で自己整合的に前記コンタクトホール底部の前記絶縁膜を除去する
ことを特徴とする請求項10または11に記載の半導体装置の製造方法。
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