JP5993268B2 - 半導体装置及び半導体装置の作製方法 - Google Patents
半導体装置及び半導体装置の作製方法 Download PDFInfo
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- JP5993268B2 JP5993268B2 JP2012225842A JP2012225842A JP5993268B2 JP 5993268 B2 JP5993268 B2 JP 5993268B2 JP 2012225842 A JP2012225842 A JP 2012225842A JP 2012225842 A JP2012225842 A JP 2012225842A JP 5993268 B2 JP5993268 B2 JP 5993268B2
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- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- GZCRRIHWUXGPOV-UHFFFAOYSA-N terbium atom Chemical compound [Tb] GZCRRIHWUXGPOV-UHFFFAOYSA-N 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- FRNOGLGSGLTDKL-UHFFFAOYSA-N thulium atom Chemical compound [Tm] FRNOGLGSGLTDKL-UHFFFAOYSA-N 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- NAWDYIZEMPQZHO-UHFFFAOYSA-N ytterbium Chemical compound [Yb] NAWDYIZEMPQZHO-UHFFFAOYSA-N 0.000 description 1
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
- H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
Description
本実施の形態では、本発明の一態様の半導体装置の基本的な構成及び作製方法について図面を用いて説明する。図1に本発明の一態様の半導体装置を示す。
本実施の形態では、実施の形態1とは異なる本発明の一態様の半導体装置について示す。なお、本実施の形態では実施の形態1と異なる点のみについて説明する。図6に本実施の形態の半導体装置を示す。図6(A)は本発明の一態様であるトランジスタの上面図を示しており、図6(B)は図6(A)の一点鎖線B1−B2における断面図である。
本実施の形態では、実施の形態1及び実施の形態2に示すトランジスタを使用し、電力が供給されない状況でも記憶内容の保持が可能で、かつ、書き込み回数にも制限が無い半導体装置の一例を、図面を用いて説明する。なお、本実施の形態の半導体装置は、トランジスタ162として実施の形態1及び実施の形態2に記載のトランジスタを適用して構成される。トランジスタ162としては、実施の形態1及び実施の形態2で示すトランジスタのいずれの構造も適用することができる
本実施の形態においては、実施の形態1及び実施の形態2に示すトランジスタを使用し、電力が供給されない状況でも記憶内容の保持が可能で、かつ、書き込み回数にも制限が無い半導体装置について、実施の形態3に示した構成と異なる構成について、図10乃至図13を用いて説明を行う。なお、本実施の形態の半導体装置は、トランジスタ162として、実施の形態1及び実施の形態2で示すトランジスタのいずれの構造も適用することができる。
本実施の形態では、先の実施の形態で示した半導体装置を携帯電話、スマートフォン、電子書籍などの携帯機器に応用した場合の例を図14乃至図17を用いて説明する。
108 ゲート絶縁層
110 ゲート電極層
116 チャネル形成領域
120 不純物元素領域
124 金属間化合物領域
130 絶縁層
135 絶縁層
136a 側壁絶縁層
136b 側壁絶縁層
137 上部絶縁層
140 絶縁層
142a 電極層
142b 電極層
143a 電極層
143b 電極層
144 酸化物半導体層
144a 低抵抗領域
144b 低抵抗領域
144c チャネル形成領域
145 絶縁層
146 ゲート絶縁層
148 ゲート電極層
150 絶縁層
156 電極層
157a 配線層
157b 配線層
160 トランジスタ
162 トランジスタ
162a トランジスタ
162b トランジスタ
164 容量素子
172 導電層
173 絶縁層
174 導電層
175a 側壁絶縁層
175b 側壁絶縁層
176 絶縁膜
185 基板
191 導電層
192 導電層
193 絶縁層
194 導電層
195 絶縁層
196 絶縁膜
250 メモリセル
251 メモリセルアレイ
251a メモリセルアレイ
251b メモリセルアレイ
253 周辺回路
254 容量素子
254a 容量素子
254b 容量素子
260 配線
300 基板
301 トランジスタ
306 素子分離絶縁層
310a 配線層
310b 配線層
341a 絶縁層
341b 絶縁層
341c 絶縁層
341d 絶縁層
343a 電極層
343b 電極層
343c 電極層
355a 配線層
355b 配線層
355c 配線層
355d 配線層
400 基板
401 ゲート電極層
402 ゲート絶縁層
403 チャネル形成領域
404a 低抵抗領域
404b 低抵抗領域
405a 電極層
405b 電極層
406 導電膜
406a ソース電極層
406b ドレイン電極層
409 酸化物半導体層
412a 側壁絶縁層
412b 側壁絶縁層
413 上部絶縁層
415 絶縁層
416 絶縁層
417 絶縁層
420 トランジスタ
421 不純物元素
430 トランジスタ
435 下地絶縁膜
436 下地絶縁層
440 トランジスタ
452 ゲート絶縁膜
455a 開口
455b 開口
465a 配線層
465b 配線層
505a 電極層
505b 電極層
520 トランジスタ
530 トランジスタ
536 下地絶縁層
801 トランジスタ
803 トランジスタ
804 トランジスタ
805 トランジスタ
806 トランジスタ
807 Xデコーダー
808 Yデコーダー
811 トランジスタ
812 保持容量
813 Xデコーダー
814 Yデコーダー
901 RF回路
902 アナログベースバンド回路
903 デジタルベースバンド回路
904 バッテリー
905 電源回路
906 アプリケーションプロセッサ
907 CPU
908 DSP
910 フラッシュメモリ
911 ディスプレイコントローラ
912 メモリ回路
913 ディスプレイ
914 表示部
915 ソースドライバ
916 ゲートドライバ
917 音声回路
918 キーボード
919 タッチセンサ
950 メモリ回路
951 メモリコントローラ
952 メモリ
953 メモリ
954 スイッチ
955 スイッチ
956 ディスプレイコントローラ
957 ディスプレイ
1001 バッテリー
1002 電源回路
1003 マイクロプロセッサ
1004 フラッシュメモリ
1005 音声回路
1006 キーボード
1007 メモリ回路
1008 タッチパネル
1009 ディスプレイ
1010 ディスプレイコントローラ
Claims (2)
- 第1の電極層及び第2の電極層と、
前記第1の電極層上の第1の領域と、前記第2の電極層上の第2の領域と、前記第1の領域と前記第2の領域との間のチャネル形成領域と、を含む酸化物半導体層と、
前記酸化物半導体層上のゲート絶縁層と、
前記ゲート絶縁層上のゲート電極層と、
前記ゲート電極層上の上部絶縁層と、
前記ゲート電極層の側面に配置された側壁絶縁層と、
前記第1の領域に接するソース電極層と、
前記第2の領域に接するドレイン電極層と、
前記ソース電極層上及び前記ドレイン電極層上の第1の絶縁層と、
前記上部絶縁層上、前記側壁絶縁層上、前記ソース電極層上及び前記ドレイン電極層上の第2の絶縁層と、
前記第1の絶縁層に設けられた第1の開口及び前記第2の絶縁層に設けられた第2の開口を介して前記ソース電極層と電気的に接続される第1の配線層と、
前記第1の絶縁層に設けられた第3の開口及び前記第2の絶縁層に設けられた第4の開口を介して前記ドレイン電極層と電気的に接続される第2の配線層と、
を有し、
前記第1の領域の抵抗は、前記チャネル形成領域の抵抗よりも低く、
前記第2の領域の抵抗は、前記チャネル形成領域の抵抗よりも低く、
前記ソース電極層の上端の位置及び前記ドレイン電極層の上端の位置は、前記上部絶縁層の上面の位置より下であり、
前記ソース電極層の上端の位置及び前記ドレイン電極層の上端の位置は、前記ゲート電極層の上面の位置より上であり、
前記第1の電極層は、前記第1の開口と重なる領域を有し、
前記第2の電極層は、前記第3の開口と重なる領域を有することを特徴とする半導体装置。 - 第1の電極層及び第2の電極層を形成し、
前記第1の電極層上及び前記第2の電極層上に酸化物半導体層を形成し、
前記酸化物半導体層上にゲート絶縁層を形成し、
前記ゲート絶縁層上に前記酸化物半導体層と重なるゲート電極層及び上部絶縁層を形成し、
前記ゲート電極層及び前記上部絶縁層をマスクとして、前記酸化物半導体層の抵抗を低下させる元素を前記酸化物半導体層に導入して、第1の領域、第2の領域及びチャネル形成領域を形成し、
前記ゲート電極層の側面に側壁絶縁層を形成し、
前記酸化物半導体層、前記ゲート電極層、前記側壁絶縁層及び前記上部絶縁層上に、導電膜を形成し、
前記導電膜上に第1の絶縁膜を形成し、
前記第1の絶縁膜及び前記導電膜を、前記上部絶縁層が露出するまで化学的機械的研磨法により除去することによって前記導電膜を分断して、ソース電極層及びドレイン電極層、及び第1の絶縁層を形成し、
前記第1の絶縁層、前記上部絶縁層、前記ソース電極層及び前記ドレイン電極層上に、第2の絶縁層を形成し、
前記第1の絶縁層及び前記第2の絶縁層に、前記ソース電極層の前記第1の電極層と重なる領域に達する第1の開口と、前記ドレイン電極層の前記第2の電極層と重なる領域に達する第2の開口と、を形成し、
前記第2の絶縁層上に、前記第1の開口において前記ソース電極層と電気的に接続する第1の配線層と、前記第2の開口において前記ドレイン電極層と電気的に接続する第2の配線層と、を形成することを特徴とする半導体装置の作製方法。
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US8637864B2 (en) | 2014-01-28 |
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