JP7068118B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP7068118B2 JP7068118B2 JP2018173563A JP2018173563A JP7068118B2 JP 7068118 B2 JP7068118 B2 JP 7068118B2 JP 2018173563 A JP2018173563 A JP 2018173563A JP 2018173563 A JP2018173563 A JP 2018173563A JP 7068118 B2 JP7068118 B2 JP 7068118B2
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
- H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
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- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Non-Volatile Memory (AREA)
Description
Claims (1)
- 半導体基板上で金属膜と第1絶縁膜とを交互に積層した積層体の階段状の端部に、各段の金属膜に到達するコンタクトホールを形成し、
前記コンタクトホールから露出している前記金属膜上に導電膜を形成し、
前記コンタクトホールの内面および前記導電膜の上面に第2絶縁膜を形成し、
前記第2絶縁膜を覆い、かつ前記第2絶縁膜とともに前記導電膜の上面全体を覆うバリアメタル膜を前記コンタクトホール内に形成し、
前記バリアメタル膜を介して前記導電膜と電気的に接続されるコンタクトを前記コンタクトホール内に形成する、半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018173563A JP7068118B2 (ja) | 2018-09-18 | 2018-09-18 | 半導体装置の製造方法 |
US16/298,056 US10825770B2 (en) | 2018-09-18 | 2019-03-11 | Semiconductor device having a stack body including metal films and first insulating films alternately stacked on a semiconductor substrate and including a stepped end portion and manufacturing method thereof |
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JP2018173563A JP7068118B2 (ja) | 2018-09-18 | 2018-09-18 | 半導体装置の製造方法 |
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JP2020047704A JP2020047704A (ja) | 2020-03-26 |
JP7068118B2 true JP7068118B2 (ja) | 2022-05-16 |
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US11158577B2 (en) * | 2020-01-31 | 2021-10-26 | Micron Technology, Inc. | Methods for fabricating microelectronic devices with contacts to conductive staircase steps, and related devices and systems |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013187335A (ja) | 2012-03-07 | 2013-09-19 | Toshiba Corp | 半導体装置及びその製造方法 |
US20170358590A1 (en) | 2016-06-09 | 2017-12-14 | Shin-Hwan Kang | Integrated circuit device including vertical memory device and method of manufacturing the same |
Family Cites Families (12)
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JPH0945763A (ja) | 1995-08-01 | 1997-02-14 | Sony Corp | コンタクトプラグおよびこれを用いた多層配線形成方法 |
JPH11145281A (ja) | 1997-11-06 | 1999-05-28 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JP2011003833A (ja) * | 2009-06-22 | 2011-01-06 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP2011060958A (ja) | 2009-09-09 | 2011-03-24 | Toshiba Corp | 半導体装置及びその製造方法 |
US9082663B2 (en) | 2011-09-16 | 2015-07-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
JP2013069932A (ja) | 2011-09-22 | 2013-04-18 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
US8637864B2 (en) | 2011-10-13 | 2014-01-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
KR101907069B1 (ko) | 2011-12-28 | 2018-10-12 | 에스케이하이닉스 주식회사 | 비휘발성 메모리 장치 및 그 제조 방법 |
KR101884002B1 (ko) * | 2012-04-13 | 2018-08-01 | 삼성전자주식회사 | 콘택 구조물 형성 방법 |
KR20150120031A (ko) | 2014-04-16 | 2015-10-27 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조 방법 |
KR102342079B1 (ko) * | 2015-05-20 | 2021-12-21 | 삼성전자주식회사 | 반도체 장치 제조 방법 |
KR102422087B1 (ko) | 2015-09-23 | 2022-07-18 | 삼성전자주식회사 | 수직형 메모리 장치 및 이의 제조 방법 |
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2013187335A (ja) | 2012-03-07 | 2013-09-19 | Toshiba Corp | 半導体装置及びその製造方法 |
US20170358590A1 (en) | 2016-06-09 | 2017-12-14 | Shin-Hwan Kang | Integrated circuit device including vertical memory device and method of manufacturing the same |
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US10825770B2 (en) | 2020-11-03 |
JP2020047704A (ja) | 2020-03-26 |
US20200091081A1 (en) | 2020-03-19 |
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