JP5470510B2 - 埋め込まれた導電性ポストを備える半導体パッケージ - Google Patents

埋め込まれた導電性ポストを備える半導体パッケージ Download PDF

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JP5470510B2
JP5470510B2 JP2008206689A JP2008206689A JP5470510B2 JP 5470510 B2 JP5470510 B2 JP 5470510B2 JP 2008206689 A JP2008206689 A JP 2008206689A JP 2008206689 A JP2008206689 A JP 2008206689A JP 5470510 B2 JP5470510 B2 JP 5470510B2
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semiconductor chip
conductive
sealing portion
pad
semiconductor package
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JP2009044160A5 (https=
JP2009044160A (ja
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坪 完 金
澤 勳 李
チョル 容 張
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
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    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
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    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
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    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
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    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
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    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
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    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
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    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
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    • H10W72/823—Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
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    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H10W72/9223—Bond pads being integral with underlying chip-level interconnections with redistribution layers [RDL]
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    • H10W72/921—Structures or relative sizes of bond pads
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    • H10W72/941—Dispositions of bond pads
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
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    • H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
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    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
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    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2008206689A 2007-08-10 2008-08-11 埋め込まれた導電性ポストを備える半導体パッケージ Active JP5470510B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR1020070080595A KR100885924B1 (ko) 2007-08-10 2007-08-10 묻혀진 도전성 포스트를 포함하는 반도체 패키지 및 그제조방법
KR10-2007-0080595 2007-08-10
US12/104,333 2008-04-16
US12/104,333 US8093703B2 (en) 2007-08-10 2008-04-16 Semiconductor package having buried post in encapsulant and method of manufacturing the same

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JP2009044160A JP2009044160A (ja) 2009-02-26
JP2009044160A5 JP2009044160A5 (https=) 2011-10-06
JP5470510B2 true JP5470510B2 (ja) 2014-04-16

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US (2) US8093703B2 (https=)
JP (1) JP5470510B2 (https=)
KR (1) KR100885924B1 (https=)
CN (1) CN101364579B (https=)
TW (1) TWI438883B (https=)

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US8846446B2 (en) 2014-09-30
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