JP5225837B2 - ロジックプロセスで埋め込まれたdramのためのワード線ドライバ - Google Patents
ロジックプロセスで埋め込まれたdramのためのワード線ドライバ Download PDFInfo
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- JP5225837B2 JP5225837B2 JP2008518472A JP2008518472A JP5225837B2 JP 5225837 B2 JP5225837 B2 JP 5225837B2 JP 2008518472 A JP2008518472 A JP 2008518472A JP 2008518472 A JP2008518472 A JP 2008518472A JP 5225837 B2 JP5225837 B2 JP 5225837B2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
101,501 pチャネルMOSトランジスタ
102,502 セルキャパシタ
103,503 ビット線
104,504 ワード線
110 ワード線ドライバ
300,600 ワード線ドライバ
310,610 出力ドライバ
315,615 インバータ
320,620 電圧変換回路
330,630 行アドレスデコーダ
311,611 nチャネルトランジスタ
301,304 pチャネルトランジスタ
303,302 pチャネルトランジスタ
313,312 nチャネルトランジスタ
Claims (32)
- メモリセルをドライブするためのワード線ドライバ回路であって、
正極性ブーストずみ電圧、すなわち前記メモリセルのパスゲートトランジスタを通じたサブスレッショルド漏洩およびゲート誘発ドレーン低下(GIDL)漏洩の合計値を最小にするように選んだ第1の電圧だけ正極性電源電圧よりも高い正極性ブーストずみ電圧を受けるように構成した正極性ブーストずみ電圧端子と、
負極性ブーストずみ電圧端子と前記メモリセルの前記パスゲートトランジスタとの間に接続したnチャネルトランジスタであって、p型基板の中に設けた深いn型ウェル領域の中に配置したp型ウェル領域に前記負極性ブーストずみ電圧端子とともに形成したnチャネルトランジスタと
を含み、
負極性電源電圧以上の電圧を受けるように構成した第1のコンタクト領域を前記深いn型ウェル領域に配置し、前記負極性電源電圧を受けるように構成した第2のコンタクト領域を前記p型基板の中に配置し、
前記負極性ブーストずみ電圧端子を、前記負極性電源電圧と等しいかその負極性電源電圧よりもトランジスタスレッショルド電圧だけ深い負極性の負極性ブーストずみ電圧を受けるように構成した
ワード線ドライバ回路。 - 前記第1の電圧が、0.2ボルトと、前記メモリセルの前記パスゲートトランジスタの前記スレッショルド電圧の絶対値との間の値を有する請求項1記載のワード線ドライバ回路。
- 前記正極性ブーストずみ電圧端子と前記メモリセルの前記パスゲートトランジスタとの間に接続したpチャネルトランジスタ
をさらに含む請求項1記載のワード線ドライバ回路。 - 前記メモリセルが慣用のロジックプロセスで埋め込まれたDRAMセルを含む請求項1記載のワード線ドライバ回路。
- 前記DRAMセルが約10フェムトファラッド(fF)以下の静電容量のキャパシタを含む請求項4記載のワード線ドライバ回路。
- 前記メモリセルが慣用のロジックプロセスで埋め込まれた単一トランジスタスタティックランダムアクセスメモリ(1T SRAM)セルを含む請求項1記載のワード線ドライバ回路。
- 前記正極性ブーストずみ電圧端子および前記負極性ブーストずみ電圧端子に接続され、前記メモリセルの前記パスゲートトランジスタのゲートに接続した出力端子を有する出力ドライバを含む請求項1記載のワード線ドライバ回路。
- 前記出力ドライバの入力端子に接続した電圧変換回路をさらに含む請求項7記載のワード線ドライバ回路。
- 前記パスゲートトランジスタ並びに前記出力ドライバおよび電圧変換回路の中のすべてのトランジスタが同じ厚さのゲート絶縁膜を有する請求項8記載のワード線ドライバ回路。
- 前記負極性ブーストずみ電圧端子を、前記負極性電源電圧よりもトランジスタスレッショルド電圧以上の電圧値だけ深い負極性の電圧値を有する負極性ブーストずみ電圧を受けるように構成した請求項1記載のワード線ドライバ回路。
- 前記第1のコンタクト領域における前記深いn型ウェル領域を接地電位よりも高い電位にバイアスする手段
をさらに含む請求項1記載のワード線ドライバ回路。 - 前記深いn型ウェル領域を前記正極性ブーストずみ電圧端子で接地電位よりも高い電位にバイアスする手段をさらに含む請求項1記載のワード線ドライバ回路。
- 前記p型基板を接地してある請求項1記載のワード線ドライバ回路。
- 前記p型ウェル領域から分離した形で第2のp型ウェル領域に形成したnチャネルロジックトランジスタをさらに含む請求項1記載のワード線ドライバ回路。
- 前記nチャネルロジックトランジスタのゲート絶縁膜よりも厚いゲート絶縁膜を前記nチャネルトランジスタが有する請求項14記載のワード線ドライバ回路。
- 前記pチャネルトランジスタが、前記正極性ブーストずみ電圧端子に接続されたn型ウェル領域に配置してある請求項3記載のワード線ドライバ回路。
- 前記n型ウェル領域が前記深いn型ウェル領域に連続している請求項16記載のワード線ドライバ回路。
- 前記n型ウェル領域が前記深いn型領域から分離している請求項16記載のワード線ドライバ回路。
- 前記DRAMセルが容量約1.5乃至10フェムトファラッドの静電容量を有するキャパシタを含む請求項5記載のワード線ドライバ回路。
- pチャネルパスゲートトランジスタを前記パスゲートトランジスタとして含みセルキャパシタに接続された前記メモリセルと、
前記nチャネルトランジスタのドレーンを前記pチャネルパスゲートトランジスタのゲートに接続するワード線と、
前記負極性ブーストずみ電圧を前記p型ウェル領域および前記nチャネルトランジスタのソースに供給するように構成した負極性ブーストずみ電圧供給源と
をさらに含み、前記単一トランジスタスレッショルド電圧が前記pチャネルパスゲートトランジスタのスレッショルド電圧である請求項1記載のワード線ドライバ回路。 - 前記正極性ブーストずみ電圧を前記深いn型ウェル領域に供給するように構成した正極性ブーストずみ電圧供給源をさらに含む請求項20記載のワード線ドライバ回路。
- 前記ワード線ドライバが、n型ウェル領域内に配置され、ドレーンを前記ワード線に接続されたpチャネルトランジスタをさらに含む請求項20記載のワード線ドライバ回路。
- 前記正極性ブーストずみ電圧を前記n型ウェル領域および前記pチャネルトランジスタのソースに供給するように構成された正極性ブーストずみ電圧供給源をさらに含む請求項22記載のワード線ドライバ回路。
- 前記正極性ブーストずみ電圧を、前記サブスレッショルド漏洩および前記pチャネルパスゲートトランジスタ経由のGIDL漏洩の合計を実質的に最小にするように選んだ請求項23記載のワード線ドライバ回路。
- 前記メモリセルおよびワード線ドライバと同一のチップ上に形成した複数のロジックトランジスタをさらに含む請求項20記載のワード線ドライバ回路。
- 前記セルキャパシタの容量が約10フェムトファラッド以下である請求項20記載のワード線ドライバ回路。
- 前記pチャネルパスゲートトランジスタおよび前記nチャネルトランジスタが同一の厚さのゲート絶縁膜を有する請求項20記載のワード線ドライバ回路。
- 前記単一トランジスタスレッショルド電圧が前記メモリセルのパスゲートトランジスタ、すなわち前記メモリセルのビット線と、前記負極性ブーストずみ電圧端子に接続したトランジスタへのワード線との間に接続したパスゲートトランジスタのスレッショルド電圧である請求項1記載のワード線ドライバ回路。
- 前記ワード線を前記メモリセルの前記パスゲートトランジスタのゲートに接続した請求項28記載のワード線ドライバ回路。
- 前記負極性ブーストずみ電圧が、前記メモリセルの非アクセス時の状態での所定のレベルにある請求項28記載のワード線ドライバ回路。
- 前記単一トランジスタスレッショルド電圧が、前記メモリセルの非アクセス時の状態でのそのメモリセルの前記パスゲートトランジスタのスレッショルド電圧である請求項28記載のワード線ドライバ回路。
- 前記ワード線を、前記負極性ブーストずみ電圧端子に接続したトランジスタに接続した請求項28記載のワード線ドライバ回路。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/166,856 US7274618B2 (en) | 2005-06-24 | 2005-06-24 | Word line driver for DRAM embedded in a logic process |
US11/166,856 | 2005-06-24 | ||
PCT/US2006/024653 WO2007002509A2 (en) | 2005-06-24 | 2006-06-23 | Word line driver for dram embedded in a logic process |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2012116747A Division JP5226144B2 (ja) | 2005-06-24 | 2012-05-22 | ロジックプロセスで埋め込まれたdramのためのワード線ドライバ |
Publications (2)
Publication Number | Publication Date |
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JP2008547152A JP2008547152A (ja) | 2008-12-25 |
JP5225837B2 true JP5225837B2 (ja) | 2013-07-03 |
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JP2008518472A Expired - Fee Related JP5225837B2 (ja) | 2005-06-24 | 2006-06-23 | ロジックプロセスで埋め込まれたdramのためのワード線ドライバ |
JP2012116747A Expired - Fee Related JP5226144B2 (ja) | 2005-06-24 | 2012-05-22 | ロジックプロセスで埋め込まれたdramのためのワード線ドライバ |
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JP2012116747A Expired - Fee Related JP5226144B2 (ja) | 2005-06-24 | 2012-05-22 | ロジックプロセスで埋め込まれたdramのためのワード線ドライバ |
Country Status (5)
Country | Link |
---|---|
US (2) | US7274618B2 (ja) |
EP (1) | EP1894202A4 (ja) |
JP (2) | JP5225837B2 (ja) |
KR (2) | KR101392094B1 (ja) |
WO (1) | WO2007002509A2 (ja) |
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US7447104B2 (en) | 2008-11-04 |
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EP1894202A4 (en) | 2009-03-25 |
US20060291321A1 (en) | 2006-12-28 |
KR101392094B1 (ko) | 2014-05-07 |
EP1894202A2 (en) | 2008-03-05 |
US7274618B2 (en) | 2007-09-25 |
KR101391557B1 (ko) | 2014-05-02 |
JP5226144B2 (ja) | 2013-07-03 |
KR20140012188A (ko) | 2014-01-29 |
JP2012181918A (ja) | 2012-09-20 |
JP2008547152A (ja) | 2008-12-25 |
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