KR950014089B1 - 동기식 디램의 히든 셀프 리프레쉬 방법 및 장치 - Google Patents
동기식 디램의 히든 셀프 리프레쉬 방법 및 장치 Download PDFInfo
- Publication number
- KR950014089B1 KR950014089B1 KR1019930023636A KR930023636A KR950014089B1 KR 950014089 B1 KR950014089 B1 KR 950014089B1 KR 1019930023636 A KR1019930023636 A KR 1019930023636A KR 930023636 A KR930023636 A KR 930023636A KR 950014089 B1 KR950014089 B1 KR 950014089B1
- Authority
- KR
- South Korea
- Prior art keywords
- refresh
- address
- bank
- banks
- cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4082—Address Buffers; level conversion circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Abstract
Description
Claims (3)
- 다수개의 셀 뱅크(cell bank)를 포함하는 동기식 디램(synchronous DRAM)의 히든 셀프 리프레쉬(hidden self rdfresh) 방법에 있어서, 소자 내부적으로 리프레쉬 동작을 개시하는 과정과, 셀 뱅크 선택 어드레스에 의해 선택된 리프레쉬 카운팅 수단을 이용하여 내부 어드레스 신호를 출력하는 과정과, 상기 내부 어드레스 신호를 멀티플렉싱(multiplexing)하고 디코딩(decoding)하는 과정을 포함하고, 다수개의 셀 뱅크 중에서 뱅크 선택 어드레스에 의해 선택된 셀 뱅크는 정상 리드/라이트 동작에 상관없이 항상 리프레쉬 동작을 수행하도록 하는 것을 특징으로 하는 리프레쉬 방법.
- 다수개의 셀 뱅크를 포함하는 동기식 디램의 히든 셀프 리프레쉬 장치에 있어서, 소자 내부적으로 리프레쉬 모드를 개시하는 수단과, 상기 리프레쉬 모드 개시 수단의 출력과 뱅크 선택 어드레스에 의해 제어되어 내부 어드레스 신호를 출력하는 뱅크수와 동일한 갯수의 리프레쉬 카운팅 수단과, 소자 외부로부터 입력되는 어드레스를 일시적으로 래치시키는 로오 어드레스 순간 래치 수단과, 상기 리프레쉬 카운팅 수단의 출력과 상기 로오 어드레스 순간 래치 순간의 출력을 선택적으로 멀티플렉싱하는 어드레스 멀티플렉싱 수단과, 뱅크 선택 어드레스에 의해 제어되며, 어드레스 멀티플렉싱 수단을 통해 멀티플렉싱된 어드레스를 각 뱅크 별로 래치시키고 버퍼링하는 로오 어드레스 래치 수단 및 로오 어드레스 버퍼링 수단을 포함하는 것을 특징으로 하는 리프레쉬 장치.
- 제 2 항에 있어서, 상기 뱅크수와 동일한 갯수의 리프레쉬 카운팅 수단 대신에, 하나의 공통 리프레쉬 카운팅 수단에 접속되고 뱅크 선택 어드레스에 의해 제어되는 뱅크수와 동일한 갯수의 레지스터를 사용하는 것을 특징으로 하는 리프레쉬 장치.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930023636A KR950014089B1 (ko) | 1993-11-08 | 1993-11-08 | 동기식 디램의 히든 셀프 리프레쉬 방법 및 장치 |
| DE4439817A DE4439817C2 (de) | 1993-11-08 | 1994-11-08 | Selbstauffrischungsvorrichtung für eine verborgene Selbstauffrischung in einem synchronen dynamischen Direktzugriffsspeicher |
| JP6273680A JP2781350B2 (ja) | 1993-11-08 | 1994-11-08 | 同期式dramのヒドン・セルフ・リフレッシュ方法及び装置 |
| US08/335,648 US5511033A (en) | 1993-11-08 | 1994-11-08 | Hidden self-refresh method and apparatus for synchronous dynamic random access memory |
| GB9422507A GB2284692B (en) | 1993-11-08 | 1994-11-08 | Hidden self-refresh method and apparatus for synchronous dynamic random access memory |
| HK98111121A HK1010465A1 (en) | 1993-11-08 | 1998-10-07 | Hidden self-refresh method and apparatus for synchronous dynamic random access memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930023636A KR950014089B1 (ko) | 1993-11-08 | 1993-11-08 | 동기식 디램의 히든 셀프 리프레쉬 방법 및 장치 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950015374A KR950015374A (ko) | 1995-06-16 |
| KR950014089B1 true KR950014089B1 (ko) | 1995-11-21 |
Family
ID=19367576
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930023636A Expired - Fee Related KR950014089B1 (ko) | 1993-11-08 | 1993-11-08 | 동기식 디램의 히든 셀프 리프레쉬 방법 및 장치 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5511033A (ko) |
| JP (1) | JP2781350B2 (ko) |
| KR (1) | KR950014089B1 (ko) |
| DE (1) | DE4439817C2 (ko) |
| GB (1) | GB2284692B (ko) |
| HK (1) | HK1010465A1 (ko) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100472251B1 (ko) * | 2001-05-28 | 2005-03-08 | 미쓰비시덴키 가부시키가이샤 | 리프레쉬 회로를 갖는 반도체 기억 장치 |
| KR100472996B1 (ko) * | 2001-05-28 | 2005-03-08 | 미쓰비시덴키 가부시키가이샤 | 리프레쉬 회로를 갖는 반도체 기억 장치 |
Families Citing this family (41)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08138374A (ja) * | 1994-11-10 | 1996-05-31 | Nec Corp | 半導体メモリ装置およびそのリフレッシュ方法 |
| JPH09180442A (ja) * | 1995-12-25 | 1997-07-11 | Fujitsu Ltd | 揮発性メモリ装置及びそのリフレッシュ方法 |
| US5627791A (en) * | 1996-02-16 | 1997-05-06 | Micron Technology, Inc. | Multiple bank memory with auto refresh to specified bank |
| JPH10247384A (ja) * | 1997-03-03 | 1998-09-14 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
| US6373769B1 (en) | 1997-06-12 | 2002-04-16 | Infineon Technologies Ag | Decoded autofresh mode in a DRAM |
| KR19990002763A (ko) * | 1997-06-23 | 1999-01-15 | 윤종용 | 반도체 메모리 장치의 리프레쉬 구조 |
| US6075744A (en) * | 1997-10-10 | 2000-06-13 | Rambus Inc. | Dram core refresh with reduced spike current |
| US6061293A (en) * | 1997-12-31 | 2000-05-09 | Intel Corporation | Synchronous interface to a self-timed memory array |
| JP3490887B2 (ja) | 1998-03-05 | 2004-01-26 | シャープ株式会社 | 同期型半導体記憶装置 |
| US6028804A (en) * | 1998-03-09 | 2000-02-22 | Monolithic System Technology, Inc. | Method and apparatus for 1-T SRAM compatible memory |
| US6504780B2 (en) * | 1998-10-01 | 2003-01-07 | Monolithic System Technology, Inc. | Method and apparatus for completely hiding refresh operations in a dram device using clock division |
| US6898140B2 (en) | 1998-10-01 | 2005-05-24 | Monolithic System Technology, Inc. | Method and apparatus for temperature adaptive refresh in 1T-SRAM compatible memory using the subthreshold characteristics of MOSFET transistors |
| US6415353B1 (en) | 1998-10-01 | 2002-07-02 | Monolithic System Technology, Inc. | Read/write buffers for complete hiding of the refresh of a semiconductor memory and method of operating same |
| US6707743B2 (en) | 1998-10-01 | 2004-03-16 | Monolithic System Technology, Inc. | Method and apparatus for completely hiding refresh operations in a DRAM device using multiple clock division |
| US5999474A (en) | 1998-10-01 | 1999-12-07 | Monolithic System Tech Inc | Method and apparatus for complete hiding of the refresh of a semiconductor memory |
| KR100351889B1 (ko) * | 1998-11-13 | 2002-11-18 | 주식회사 하이닉스반도체 | 카스(cas)레이턴시(latency) 제어 회로 |
| JP2000163956A (ja) * | 1998-11-24 | 2000-06-16 | Sharp Corp | 半導体記憶装置 |
| KR100557975B1 (ko) * | 1998-12-31 | 2006-05-17 | 주식회사 하이닉스반도체 | 메모리의 자동 리프레쉬 회로_ |
| US6282606B1 (en) * | 1999-04-02 | 2001-08-28 | Silicon Aquarius, Inc. | Dynamic random access memories with hidden refresh and utilizing one-transistor, one-capacitor cells, systems and methods |
| US6327209B1 (en) | 2000-08-30 | 2001-12-04 | Micron Technology, Inc. | Multi stage refresh control of a memory device |
| JP2002157880A (ja) * | 2000-11-15 | 2002-05-31 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
| KR100472723B1 (ko) * | 2000-12-26 | 2005-03-08 | 주식회사 하이닉스반도체 | 뱅크 리프레쉬 제어 장치 및 방법 |
| JP2004288226A (ja) * | 2001-03-30 | 2004-10-14 | Internatl Business Mach Corp <Ibm> | Dram及びdramのリフレッシュ方法 |
| US7085186B2 (en) * | 2001-04-05 | 2006-08-01 | Purple Mountain Server Llc | Method for hiding a refresh in a pseudo-static memory |
| US6590822B2 (en) * | 2001-05-07 | 2003-07-08 | Samsung Electronics Co., Ltd. | System and method for performing partial array self-refresh operation in a semiconductor memory device |
| KR100429872B1 (ko) * | 2001-06-27 | 2004-05-04 | 삼성전자주식회사 | 반도체 메모리 장치의 이용 효율을 높이는 메모리 시스템및 상기 반도체 메모리 장치의 리프레쉬 방법 |
| GB2380035B (en) | 2001-09-19 | 2003-08-20 | 3Com Corp | DRAM refresh command operation |
| US6671218B2 (en) | 2001-12-11 | 2003-12-30 | International Business Machines Corporation | System and method for hiding refresh cycles in a dynamic type content addressable memory |
| US7043599B1 (en) | 2002-06-20 | 2006-05-09 | Rambus Inc. | Dynamic memory supporting simultaneous refresh and data-access transactions |
| US6795364B1 (en) * | 2003-02-28 | 2004-09-21 | Monolithic System Technology, Inc. | Method and apparatus for lengthening the data-retention time of a DRAM device in standby mode |
| JP2005222581A (ja) | 2004-02-03 | 2005-08-18 | Renesas Technology Corp | 半導体記憶装置 |
| JP4664622B2 (ja) * | 2004-05-20 | 2011-04-06 | 株式会社東芝 | 半導体集積回路装置 |
| US7274618B2 (en) | 2005-06-24 | 2007-09-25 | Monolithic System Technology, Inc. | Word line driver for DRAM embedded in a logic process |
| JP4894306B2 (ja) * | 2006-03-09 | 2012-03-14 | 富士通セミコンダクター株式会社 | 半導体メモリ、メモリシステムおよび半導体メモリの動作方法 |
| JP5446384B2 (ja) * | 2009-03-30 | 2014-03-19 | 富士通セミコンダクター株式会社 | インターフェース回路、メモリシステム、およびアクセス制御方法 |
| US8982654B2 (en) * | 2013-07-05 | 2015-03-17 | Qualcomm Incorporated | DRAM sub-array level refresh |
| KR20160001098A (ko) * | 2014-06-26 | 2016-01-06 | 에스케이하이닉스 주식회사 | 래치 회로 이를 포함하는 입출력 장치 |
| US20180061484A1 (en) * | 2016-08-29 | 2018-03-01 | Apple Inc. | Systems and Methods for Memory Refresh Timing |
| TWI639920B (zh) | 2017-11-17 | 2018-11-01 | 財團法人工業技術研究院 | 記憶體控制器及其控制方法以及記憶體及其控制方法 |
| TWI671632B (zh) | 2018-10-24 | 2019-09-11 | 財團法人工業技術研究院 | 記憶體裝置及其復新資訊同步方法 |
| CN112786084B (zh) * | 2021-03-16 | 2023-06-23 | 北京时代全芯存储技术股份有限公司 | 记忆体装置 |
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| DE2247835C3 (de) * | 1972-09-29 | 1978-10-05 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Verfahren zum Regenerieren der Speicherinhalte von MOS-Speichern und MOS-Speicher zur Durchführung dieses Verfahrens |
| IT1041882B (it) * | 1975-08-20 | 1980-01-10 | Honeywell Inf Systems | Memoria dinamica a semiconduttori e relativo sistema di recarica |
| US4238842A (en) * | 1978-12-26 | 1980-12-09 | Ibm Corporation | LARAM Memory with reordered selection sequence for refresh |
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| GB2095442A (en) * | 1981-03-25 | 1982-09-29 | Philips Electronic Associated | Refreshing dynamic MOS memories |
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| JPS63282997A (ja) * | 1987-05-15 | 1988-11-18 | Mitsubishi Electric Corp | ブロツクアクセスメモリ |
| JPH01124195A (ja) * | 1987-11-09 | 1989-05-17 | Sharp Corp | セルフリフレッシュ方式 |
| US4933907A (en) * | 1987-12-03 | 1990-06-12 | Mitsubishi Denki Kabushiki Kaisha | Dynamic random access memory device and operating method therefor |
| US5239505A (en) * | 1990-12-28 | 1993-08-24 | Intel Corporation | Floating gate non-volatile memory with blocks and memory refresh |
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| JPH05109266A (ja) * | 1991-10-17 | 1993-04-30 | Sanyo Electric Co Ltd | 半導体記憶装置 |
| JP2988804B2 (ja) * | 1993-03-19 | 1999-12-13 | 株式会社東芝 | 半導体メモリ装置 |
-
1993
- 1993-11-08 KR KR1019930023636A patent/KR950014089B1/ko not_active Expired - Fee Related
-
1994
- 1994-11-08 DE DE4439817A patent/DE4439817C2/de not_active Expired - Fee Related
- 1994-11-08 GB GB9422507A patent/GB2284692B/en not_active Expired - Fee Related
- 1994-11-08 US US08/335,648 patent/US5511033A/en not_active Expired - Lifetime
- 1994-11-08 JP JP6273680A patent/JP2781350B2/ja not_active Expired - Fee Related
-
1998
- 1998-10-07 HK HK98111121A patent/HK1010465A1/xx not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100472251B1 (ko) * | 2001-05-28 | 2005-03-08 | 미쓰비시덴키 가부시키가이샤 | 리프레쉬 회로를 갖는 반도체 기억 장치 |
| KR100472996B1 (ko) * | 2001-05-28 | 2005-03-08 | 미쓰비시덴키 가부시키가이샤 | 리프레쉬 회로를 갖는 반도체 기억 장치 |
Also Published As
| Publication number | Publication date |
|---|---|
| US5511033A (en) | 1996-04-23 |
| KR950015374A (ko) | 1995-06-16 |
| GB2284692B (en) | 1998-04-08 |
| HK1010465A1 (en) | 1999-06-17 |
| DE4439817C2 (de) | 2002-03-14 |
| JPH07226077A (ja) | 1995-08-22 |
| DE4439817A1 (de) | 1995-05-11 |
| JP2781350B2 (ja) | 1998-07-30 |
| GB2284692A (en) | 1995-06-14 |
| GB9422507D0 (en) | 1995-01-04 |
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