JP2012181918A - ロジックプロセスで埋め込まれたdramのためのワード線ドライバ - Google Patents
ロジックプロセスで埋め込まれたdramのためのワード線ドライバ Download PDFInfo
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- JP2012181918A JP2012181918A JP2012116747A JP2012116747A JP2012181918A JP 2012181918 A JP2012181918 A JP 2012181918A JP 2012116747 A JP2012116747 A JP 2012116747A JP 2012116747 A JP2012116747 A JP 2012116747A JP 2012181918 A JP2012181918 A JP 2012181918A
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- Prior art keywords
- transistor
- voltage
- word line
- type well
- boosted voltage
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
【解決手段】慣用のロジックプロセスによるpチャネルトランジスタ101を含むDRAMセルにアクセスするためのワード線ドライバを提供する。このワード線ドライバは、p型基板の中の深いn型ウェル領域の中に配置したp型ウェル領域に設けたnチャネルトランジスタ313を含む。負極性のブースト電圧供給源から前記p型ウェルおよび前記nチャネルトランジスタのソースに負極性ブースト電圧を供給する。この負極性ブースト電圧は、pチャネルアクセストランジスタのスレッショルド電圧以上の電圧値だけ接地電位よりも低い。深いn型ウェルおよびp型基板は接地電位点に接続する。
【選択図】図3
Description
DRAM with 330-mbit/s Data Rate" に記載されている。その構成では、メモリデバイスの基板をpn接合のオン切換防止のために−2.5ボルトにバイアスしている。ワード線活性化のあとメモリアクセスの期間中にワード線負極性ブースト電圧を発生する。この多段ワード線活性化によりメモリサイクル時間は増加する。
101,501 pチャネルMOSトランジスタ
102,502 セルキャパシタ
103,503 ビット線
104,504 ワード線
110 ワード線ドライバ
300,600 ワード線ドライバ
310,610 出力ドライバ
315,615 インバータ
320,620 電圧変換回路
330,630 行アドレスデコーダ
311,611 nチャネルトランジスタ
301,304 pチャネルトランジスタ
303,302 pチャネルトランジスタ
313,312 nチャネルトランジスタ
Claims (15)
- セルキャパシタに接続したpチャネルパスゲートトランジスタを含むメモリセルと、
深いn型ウェル領域の中に配置したp型ウェル領域に形成したnチャネルトランジスタを含むワード線ドライバと、
前記nチャネルトランジスタのドレーンを前記pチャネルパスゲートトランジスタのゲートに接続するワード線と
を含む回路。 - 前記p型ウェル領域および前記nチャネルトランジスタのソースに負極性ブーストずみ電圧を供給するように構成した負極性ブーストずみ電圧供給源をさらに含む請求項1記載の回路。
- 前記負極性ブーストずみ電圧が、前記pチャネルパスゲートトランジスタのスレッショルド電圧以上の電圧値だけ接地電位よりも低い請求項2記載の回路。
- 接地電位以上の電圧を前記深いn型領域に供給するように構成した電圧供給源をさらに含む請求項2記載の回路。
- 前記深いn型ウェル領域がp型基板の中に形成されており、前記接地電位供給源が前記p型基板に接続されている請求項4記載の回路。
- 正極性のブーストずみ電圧を前記深いn型ウェル領域に供給するように構成した正極性ブーストずみ電圧供給源をさらに含む請求項2記載の回路。
- 前記ワード線ドライバが、n型ウェル領域内に形成され前記ワード線に接続したドレーンを有するpチャネルトランジスタをさらに含む請求項2記載の回路。
- 前記n型ウェル領域および前記pチャネルトランジスタのソースに正極性ブーストずみ電圧を供給するように構成した正極性ブーストずみ電圧供給源をさらに含む請求項7記載の回路。
- 前記正極性ブーストずみ電圧が正極性電源電圧よりも高く、前記pチャネルパスゲートトランジスタを通じたサブスレッショルド漏洩およびGIDL漏洩の合計値を最小にするように選んだ値を有する請求項8記載の回路。
- 前記pチャネルトランジスタのゲートおよび前記nチャネルトランジスタのゲートに接続した出力端子を有し、前記正極性ブーストずみ電圧および前記負極性ブーストずみ電圧を受けるように接続したインバータをさらに含む請求項8記載の回路。
- 前記正極性ブーストずみ電圧供給源と前記インバータの入力との間に接続したpチャネルトランジスタをさらに含む請求項10記載の回路。
- 前記インバータの入力を前記正極性ブーストずみ電圧供給源または接地電位供給源に接続する手段をさらに含む請求項11記載の回路。
- 前記メモリセルおよび前記ワード線ドライバと同じチップの上に形成した複数のロジックトランジスタをさらに含む請求項1記載の回路。
- 前記セルキャパシタの静電容量が約10フェムトファラッド(fF)以下である請求項1記載の回路。
- 前記パスゲートトランジスタおよび前記nチャネルトランジスタのゲート絶縁膜の厚さが互いに等しい請求項1記載の回路。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/166,856 US7274618B2 (en) | 2005-06-24 | 2005-06-24 | Word line driver for DRAM embedded in a logic process |
US11/166,856 | 2005-06-24 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008518472A Division JP5225837B2 (ja) | 2005-06-24 | 2006-06-23 | ロジックプロセスで埋め込まれたdramのためのワード線ドライバ |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012181918A true JP2012181918A (ja) | 2012-09-20 |
JP5226144B2 JP5226144B2 (ja) | 2013-07-03 |
Family
ID=37567173
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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JP2008518472A Expired - Fee Related JP5225837B2 (ja) | 2005-06-24 | 2006-06-23 | ロジックプロセスで埋め込まれたdramのためのワード線ドライバ |
JP2012116747A Expired - Fee Related JP5226144B2 (ja) | 2005-06-24 | 2012-05-22 | ロジックプロセスで埋め込まれたdramのためのワード線ドライバ |
Family Applications Before (1)
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JP2008518472A Expired - Fee Related JP5225837B2 (ja) | 2005-06-24 | 2006-06-23 | ロジックプロセスで埋め込まれたdramのためのワード線ドライバ |
Country Status (5)
Country | Link |
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US (2) | US7274618B2 (ja) |
EP (1) | EP1894202A4 (ja) |
JP (2) | JP5225837B2 (ja) |
KR (2) | KR101392094B1 (ja) |
WO (1) | WO2007002509A2 (ja) |
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KR20140012188A (ko) | 2014-01-29 |
EP1894202A4 (en) | 2009-03-25 |
KR101392094B1 (ko) | 2014-05-07 |
JP2008547152A (ja) | 2008-12-25 |
US20060291321A1 (en) | 2006-12-28 |
JP5226144B2 (ja) | 2013-07-03 |
JP5225837B2 (ja) | 2013-07-03 |
WO2007002509A3 (en) | 2007-06-21 |
EP1894202A2 (en) | 2008-03-05 |
KR20080034433A (ko) | 2008-04-21 |
WO2007002509A2 (en) | 2007-01-04 |
KR101391557B1 (ko) | 2014-05-02 |
US7447104B2 (en) | 2008-11-04 |
US20070109906A1 (en) | 2007-05-17 |
US7274618B2 (en) | 2007-09-25 |
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