JP5041760B2 - 半導体集積回路装置 - Google Patents
半導体集積回路装置 Download PDFInfo
- Publication number
- JP5041760B2 JP5041760B2 JP2006215489A JP2006215489A JP5041760B2 JP 5041760 B2 JP5041760 B2 JP 5041760B2 JP 2006215489 A JP2006215489 A JP 2006215489A JP 2006215489 A JP2006215489 A JP 2006215489A JP 5041760 B2 JP5041760 B2 JP 5041760B2
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- JP
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- Prior art keywords
- conductivity type
- well region
- mosfet
- semiconductor integrated
- integrated circuit
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
12、13 リミッタ回路
15 基本セル
16、16a ラッチアップ防止セル
21 pウェル領域
22 nウェル領域
23、24 基板バイアス供給用電源配線
25、26、41、42、50、52 n+拡散層
27、43、48 ゲート電極
28、29、45、46、47、51 p+拡散層
30、31、44、44a、49、49a 配線
32 電源配線
33 接地配線
P1、P2 pMOSFET
N1、N2 nMOSFET
Claims (10)
- CMOS回路を備える半導体集積回路装置であって、
CMOS回路を構成する第1のMOSFETと、
前記第1のMOSFETのバックゲートとソース間に接続され、該バックゲートとソース間に形成されるpn接合における順方向電流を遮断するように該pn接合の順方向電圧を制限する第1のリミッタ回路と、
を備え、
前記第1のリミッタ回路は、前記第1のMOSFETと同一の導電型である第2のMOSFETから構成され、
前記第2のMOSFETは、ゲートとドレインとバックゲートとを前記第1のMOSFETのバックゲートに接続し、ソースを前記第1のMOSFETのソースに接続することを特徴とする半導体集積回路装置。 - 前記CMOS回路を構成する、前記第1のMOSFETと逆導電型である第3のMOSFETと、
前記第3のMOSFETのバックゲートとソース間に接続され、該バックゲートとソース間に形成されるpn接合における順方向電流を遮断するように該pn接合の順方向電圧を制限する第2のリミッタ回路と、
をさらに備え、
前記第2のリミッタ回路は、前記第3のMOSFETと同一の導電型である第4のMOSFETから構成され、
前記第4のMOSFETは、ゲートとドレインとバックゲートとを前記第3のMOSFETのバックゲートに接続し、ソースを前記第3のMOSFETのソースに接続することを特徴とする請求項1記載の半導体集積回路装置。 - CMOS回路を備える半導体集積回路装置であって、
基板内に帯状に形成される第1導電型ウェル領域と、
前記基板内に帯状に形成されると共に、前記第1導電型ウェル領域と平行に隣接して配置される第2導電型ウェル領域と、
前記第1導電型ウェル領域内に形成され、前記第1導電型ウェル領域に供給される第1の基板バイアス供給用電源配線に接続される第1の第1導電型拡散領域と、
前記CMOS回路に電源を供給する第1および第2の電源配線と、
前記第1導電型ウェル領域に形成されると共に、ゲートとドレインとを前記第1導電型ウェル領域に接続し、前記第1の電源配線にソースを接続する第2導電型MOSFETと、
を備えることを特徴とする半導体集積回路装置。 - 前記第1導電型ウェル領域に対して複数の前記第1の第1導電型拡散領域が存在し、前記第2導電型MOSFETのドレインの前記第1導電型ウェル領域への接続点となる第2の第1導電型拡散領域を、2つの前記第1の第1導電型拡散領域間に配置することを特徴とする請求項3記載の半導体集積回路装置。
- 前記第1導電型ウェル領域と前記第2導電型ウェル領域とに跨って形成される複数のセルを備え、
前記複数のセルの少なくとも一部は、前記第2導電型MOSFETと、前記第2導電型MOSFETのドレインの前記第1導電型ウェル領域への接続点となる第2の第1導電型拡散領域とをそれぞれ含むことを特徴とする請求項3記載の半導体集積回路装置。 - 前記第2導電型MOSFETのドレイン領域と、前記第2の第1導電型拡散領域とは、隣接して前記第1導電型ウェル領域中に形成されることを特徴とする請求項4または5記載の半導体集積回路装置。
- 前記第2導電型ウェル領域内に形成され、前記第2導電型ウェル領域に供給される第2の基板バイアス供給用電源配線に接続される第1の第2導電型拡散領域と、
前記第2導電型ウェル領域に形成されると共に、ゲートとドレインとを前記第2導電型ウェル領域に接続し、前記第2の電源配線にソースを接続する第1導電型MOSFETと、
をさらに備えることを特徴とする請求項3記載の半導体集積回路装置。 - 前記第2導電型ウェル領域に対して複数の前記第1の第2導電型拡散領域が存在し、前記第1導電型MOSFETのドレインの前記第2導電型ウェル領域への接続点となる第2の第2導電型拡散領域を、2つの前記第1の第2導電型拡散領域間に配置することを特徴とする請求項7記載の半導体集積回路装置。
- 前記第1導電型ウェル領域と前記第2導電型ウェル領域とに跨って形成される複数のセルを備え、
前記複数のセルの少なくとも一部は、前記第1導電型MOSFETと、前記第1導電型MOSFETのドレインの前記第2導電型ウェル領域への接続点となる第2の第2導電型拡散領域と、前記第2導電型MOSFETと、前記第2導電型MOSFETのドレインの前記第1導電型ウェル領域への接続点となる第2の第1導電型拡散領域とを含むことを特徴とする請求項7に記載の半導体集積回路装置。 - 前記第1導電型MOSFETのドレイン領域と、前記第2の第2導電型拡散領域とは、隣接して前記第2導電型ウェル領域中に形成されることを特徴とする請求項8または9記載の半導体集積回路装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006215489A JP5041760B2 (ja) | 2006-08-08 | 2006-08-08 | 半導体集積回路装置 |
CN2007101399358A CN101123255B (zh) | 2006-08-08 | 2007-08-03 | 半导体集成电路装置 |
US11/882,802 US8072032B2 (en) | 2006-08-08 | 2007-08-06 | Semiconductor integrated circuit device having latchup preventing function |
US12/967,479 US8198688B2 (en) | 2006-08-08 | 2010-12-14 | Semiconductor integrated circuit device with MOSFET limiter circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006215489A JP5041760B2 (ja) | 2006-08-08 | 2006-08-08 | 半導体集積回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008041986A JP2008041986A (ja) | 2008-02-21 |
JP5041760B2 true JP5041760B2 (ja) | 2012-10-03 |
Family
ID=39049863
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006215489A Expired - Fee Related JP5041760B2 (ja) | 2006-08-08 | 2006-08-08 | 半導体集積回路装置 |
Country Status (3)
Country | Link |
---|---|
US (2) | US8072032B2 (ja) |
JP (1) | JP5041760B2 (ja) |
CN (1) | CN101123255B (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5041760B2 (ja) * | 2006-08-08 | 2012-10-03 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
JP2008182004A (ja) * | 2007-01-24 | 2008-08-07 | Renesas Technology Corp | 半導体集積回路 |
US8017471B2 (en) * | 2008-08-06 | 2011-09-13 | International Business Machines Corporation | Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry |
JP5341426B2 (ja) * | 2008-08-12 | 2013-11-13 | パナソニック株式会社 | 半導体集積回路 |
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-
2006
- 2006-08-08 JP JP2006215489A patent/JP5041760B2/ja not_active Expired - Fee Related
-
2007
- 2007-08-03 CN CN2007101399358A patent/CN101123255B/zh not_active Expired - Fee Related
- 2007-08-06 US US11/882,802 patent/US8072032B2/en not_active Expired - Fee Related
-
2010
- 2010-12-14 US US12/967,479 patent/US8198688B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US8072032B2 (en) | 2011-12-06 |
US20080036011A1 (en) | 2008-02-14 |
US20110084342A1 (en) | 2011-04-14 |
JP2008041986A (ja) | 2008-02-21 |
US8198688B2 (en) | 2012-06-12 |
CN101123255B (zh) | 2010-09-29 |
CN101123255A (zh) | 2008-02-13 |
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