JP5096669B2 - 半導体集積回路装置の製造方法 - Google Patents

半導体集積回路装置の製造方法 Download PDF

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Publication number
JP5096669B2
JP5096669B2 JP2005197938A JP2005197938A JP5096669B2 JP 5096669 B2 JP5096669 B2 JP 5096669B2 JP 2005197938 A JP2005197938 A JP 2005197938A JP 2005197938 A JP2005197938 A JP 2005197938A JP 5096669 B2 JP5096669 B2 JP 5096669B2
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JP
Japan
Prior art keywords
film
insulating film
interlayer insulating
wiring
forming
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2005197938A
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English (en)
Japanese (ja)
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JP2007019187A5 (https=
JP2007019187A (ja
Inventor
勝彦 堀田
郷子 笹原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
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Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2005197938A priority Critical patent/JP5096669B2/ja
Priority to US11/453,882 priority patent/US7354855B2/en
Priority to TW098120878A priority patent/TWI389254B/zh
Priority to TW095122404A priority patent/TWI385757B/zh
Priority to TW102102115A priority patent/TWI525747B/zh
Priority to CNB2006101002616A priority patent/CN100559565C/zh
Priority to CN2009101691985A priority patent/CN101656229B/zh
Priority to KR1020060063325A priority patent/KR101328862B1/ko
Publication of JP2007019187A publication Critical patent/JP2007019187A/ja
Priority to US12/031,046 priority patent/US7932606B2/en
Priority to US12/141,195 priority patent/US7557034B2/en
Priority to US12/141,172 priority patent/US7629251B2/en
Publication of JP2007019187A5 publication Critical patent/JP2007019187A5/ja
Priority to US13/081,332 priority patent/US8487412B2/en
Priority to KR1020110054737A priority patent/KR101344146B1/ko
Priority to US13/525,195 priority patent/US8518821B2/en
Priority to US13/525,251 priority patent/US8581415B2/en
Publication of JP5096669B2 publication Critical patent/JP5096669B2/ja
Application granted granted Critical
Priority to US14/042,938 priority patent/US8704373B2/en
Priority to US14/214,975 priority patent/US20140199831A1/en
Priority to US14/696,365 priority patent/US9391022B2/en
Priority to US15/181,995 priority patent/US9899316B2/en
Priority to US15/616,899 priority patent/US10141257B2/en
Priority to US16/169,796 priority patent/US10600683B2/en
Priority to US16/817,544 priority patent/US10796953B2/en
Priority to US17/023,327 priority patent/US11062938B2/en
Priority to US17/343,448 priority patent/US11600522B2/en
Priority to US18/164,153 priority patent/US12154823B2/en
Priority to US18/922,646 priority patent/US20250046653A1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
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    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
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    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/075—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698—Local interconnections
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    • H10W20/00—Interconnections in chips, wafers or substrates
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    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/085—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/087—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving multiple stacked pre-patterned masks
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
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    • H10W20/00—Interconnections in chips, wafers or substrates
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    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H10W20/493—Fuses, i.e. interconnections changeable from conductive to non-conductive
    • H10W20/494—Fuses, i.e. interconnections changeable from conductive to non-conductive changeable by the use of an external beam, e.g. laser beam or ion beam
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Drying Of Semiconductors (AREA)
JP2005197938A 2005-07-06 2005-07-06 半導体集積回路装置の製造方法 Expired - Lifetime JP5096669B2 (ja)

Priority Applications (26)

Application Number Priority Date Filing Date Title
JP2005197938A JP5096669B2 (ja) 2005-07-06 2005-07-06 半導体集積回路装置の製造方法
US11/453,882 US7354855B2 (en) 2005-07-06 2006-06-16 Semiconductor device and a method of manufacturing the same
TW095122404A TWI385757B (zh) 2005-07-06 2006-06-22 Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device
TW102102115A TWI525747B (zh) 2005-07-06 2006-06-22 Semiconductor integrated circuit device and method for manufacturing semiconductor integrated circuit device
TW098120878A TWI389254B (zh) 2005-07-06 2006-06-22 Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device
CN2009101691985A CN101656229B (zh) 2005-07-06 2006-07-05 半导体器件及其制造方法
CNB2006101002616A CN100559565C (zh) 2005-07-06 2006-07-05 半导体器件及其制造方法
KR1020060063325A KR101328862B1 (ko) 2005-07-06 2006-07-06 반도체집적회로장치 및 반도체집적회로장치의 제조 방법
US12/031,046 US7932606B2 (en) 2005-07-06 2008-02-14 Semiconductor device and a method of manufacturing the same
US12/141,195 US7557034B2 (en) 2005-07-06 2008-06-18 Semiconductor device and a method of manufacturing the same
US12/141,172 US7629251B2 (en) 2005-07-06 2008-06-18 Semiconductor device and a method of manufacturing the same
US13/081,332 US8487412B2 (en) 2005-07-06 2011-04-06 Semiconductor device and a method of manufacturing the same
KR1020110054737A KR101344146B1 (ko) 2005-07-06 2011-06-07 반도체집적회로장치 및 반도체집적회로장치의 제조 방법
US13/525,251 US8581415B2 (en) 2005-07-06 2012-06-15 Semiconductor device and a method of manufacturing the same
US13/525,195 US8518821B2 (en) 2005-07-06 2012-06-15 Semiconductor device and a method of manufacturing the same
US14/042,938 US8704373B2 (en) 2005-07-06 2013-10-01 Semiconductor device and a method of manufacturing the same
US14/214,975 US20140199831A1 (en) 2005-07-06 2014-03-16 Semiconductor device and a method of manufacturing the same
US14/696,365 US9391022B2 (en) 2005-07-06 2015-04-24 Semiconductor device and a method of manufacturing the same
US15/181,995 US9899316B2 (en) 2005-07-06 2016-06-14 Semiconductor device and a method of manufacturing the same
US15/616,899 US10141257B2 (en) 2005-07-06 2017-06-07 Semiconductor device and a method of manufacturing the same
US16/169,796 US10600683B2 (en) 2005-07-06 2018-10-24 Semiconductor device and a method of manufacturing the same
US16/817,544 US10796953B2 (en) 2005-07-06 2020-03-12 Semiconductor device and a method of manufacturing the same
US17/023,327 US11062938B2 (en) 2005-07-06 2020-09-16 Semiconductor device and a method of manufacturing the same
US17/343,448 US11600522B2 (en) 2005-07-06 2021-06-09 Semiconductor device and a method of manufacturing the same
US18/164,153 US12154823B2 (en) 2005-07-06 2023-02-03 Semiconductor device and a method of manufacturing the same
US18/922,646 US20250046653A1 (en) 2005-07-06 2024-10-22 Semiconductor device and a method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005197938A JP5096669B2 (ja) 2005-07-06 2005-07-06 半導体集積回路装置の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2008174669A Division JP4891296B2 (ja) 2008-07-03 2008-07-03 半導体集積回路装置の製造方法

Publications (3)

Publication Number Publication Date
JP2007019187A JP2007019187A (ja) 2007-01-25
JP2007019187A5 JP2007019187A5 (https=) 2008-08-21
JP5096669B2 true JP5096669B2 (ja) 2012-12-12

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JP2005197938A Expired - Lifetime JP5096669B2 (ja) 2005-07-06 2005-07-06 半導体集積回路装置の製造方法

Country Status (5)

Country Link
US (18) US7354855B2 (https=)
JP (1) JP5096669B2 (https=)
KR (2) KR101328862B1 (https=)
CN (2) CN100559565C (https=)
TW (3) TWI389254B (https=)

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JP5096669B2 (ja) 2005-07-06 2012-12-12 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
JP4699172B2 (ja) * 2005-10-25 2011-06-08 ルネサスエレクトロニクス株式会社 半導体装置
JP4830455B2 (ja) * 2005-11-10 2011-12-07 ルネサスエレクトロニクス株式会社 半導体装置
US20080272435A1 (en) * 2007-05-02 2008-11-06 Chien-Ting Lin Semiconductor device and method of forming the same
US7825010B2 (en) * 2007-06-07 2010-11-02 Micron Technology, Inc. Die singulation methods
KR100854863B1 (ko) * 2007-06-29 2008-08-28 주식회사 하이닉스반도체 반도체 소자의 제조방법
CN101110393B (zh) * 2007-07-05 2012-03-07 复旦大学 一种CuxO电阻存储器制备与铜互连工艺集成的方法
US7936072B2 (en) 2007-11-12 2011-05-03 Renesas Electronics Corporation Semiconductor device having dual damascene structure
JP5310721B2 (ja) * 2008-06-18 2013-10-09 富士通株式会社 半導体装置とその製造方法
DE102008044984A1 (de) * 2008-08-29 2010-07-15 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit Verspannungsrelaxationsspalte zur Verbesserung der Chipgehäusewechselwirkungsstabilität
US8338265B2 (en) 2008-11-12 2012-12-25 International Business Machines Corporation Silicided trench contact to buried conductive layer
JP5559775B2 (ja) * 2009-04-30 2014-07-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US8227339B2 (en) 2009-11-02 2012-07-24 International Business Machines Corporation Creation of vias and trenches with different depths
JP5622433B2 (ja) * 2010-04-28 2014-11-12 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US8946904B2 (en) * 2010-08-27 2015-02-03 Avago Technologies General Ip (Singapore) Pte. Ltd. Substrate vias for heat removal from semiconductor die
CN102386126B (zh) * 2010-09-03 2013-10-30 中芯国际集成电路制造(上海)有限公司 制作用于形成双大马士革结构的半导体器件结构的方法
JP5755471B2 (ja) * 2011-03-10 2015-07-29 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN102437090B (zh) * 2011-07-12 2015-01-14 上海华力微电子有限公司 无金属阻挡层的铜后道互连工艺
CN103094179B (zh) * 2011-10-27 2015-06-17 中芯国际集成电路制造(上海)有限公司 连接孔形成方法
US9553043B2 (en) * 2012-04-03 2017-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure having smaller transition layer via
US9111998B2 (en) 2012-04-04 2015-08-18 Samsung Electronics Co., Ltd Multi-level stack having multi-level contact and method
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