TW201322372A - 半導體積體電路裝置及半導體積體電路裝置之製造方法 - Google Patents

半導體積體電路裝置及半導體積體電路裝置之製造方法 Download PDF

Info

Publication number
TW201322372A
TW201322372A TW102102115A TW102102115A TW201322372A TW 201322372 A TW201322372 A TW 201322372A TW 102102115 A TW102102115 A TW 102102115A TW 102102115 A TW102102115 A TW 102102115A TW 201322372 A TW201322372 A TW 201322372A
Authority
TW
Taiwan
Prior art keywords
insulating film
film
barrier insulating
wiring
barrier
Prior art date
Application number
TW102102115A
Other languages
English (en)
Other versions
TWI525747B (zh
Inventor
Katsuhiko Hotta
Kyoko Sasahara
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of TW201322372A publication Critical patent/TW201322372A/zh
Application granted granted Critical
Publication of TWI525747B publication Critical patent/TWI525747B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

本發明簡化使用雙道金屬鑲嵌(Dual-Damascene)法之多層銅布線之形成步驟。其係將形成於層間絕緣膜45上之光阻膜51作為遮罩，乾式蝕刻層間絕緣膜45，藉由在形成於層間絕緣膜45中途部之停止膜46之表面蝕刻，而形成布線溝52、53。此時，藉由光反射率低之SiCN膜構成停止膜46，藉由使光阻膜51作為曝光時之防反射膜之功能，而無須在光阻膜51之下層形成防反射膜之步驟。

Description

半導體積體電路裝置及半導體積體電路裝置之製造方法
本發明係關於半導體積體電路裝置之製造技術，特別是關於適用於使用雙道金屬鑲嵌(Dual-Damascene)法形成布線之有效技術。
近年來，微細化之半導體積體電路裝置之製造步驟，係以稱為金屬鑲嵌(Damascene)法之微細布線形成方法為主流。
金屬鑲嵌法係藉由在半導體基板上之層間絕緣膜中形成微細之布線溝後，在包含該布線溝之內部之層間絕緣膜上堆積金屬膜，其次，使用化學性機械研磨(CMP：Chemical Mechanical Polishing)法，除去布線溝外部之金屬膜，而在布線溝之內部形成微細之埋入布線之方法。
上述金屬鑲嵌法中，稱為雙道金屬鑲嵌法之方法，係在形成於層間絕緣膜之布線溝之下部，形成下層布線連接用之通孔，藉由在布線溝與通孔中同時埋入金屬膜而形成布線，謀求縮短步驟數。另外，預先在通孔之內部形成金屬插塞後，在布線溝之內部形成埋入布線之方法，則稱為單道金屬鑲嵌(Single-Damascene)法。
埋入布線用之金屬材料，主要使用即使細線化仍可確保高度可靠性之銅(Cu)。此外，使用金屬鑲嵌法，於層間絕緣膜中形成埋入布線時，為了減少鄰接布線間產生之電容，係以介電常數低之絕緣材料構成層間絕緣膜。在包含 低介電常數材料之層間絕緣膜中，以金屬鑲嵌法形成埋入布線之技術，如記載於日本特開2004-221275號公報(專利文獻1)及日本特開2003-124307號公報(專利文獻2)等。
此外，於日本特開2003-163265號公報(專利文獻3)中揭示有：藉由單道金屬鑲嵌法形成布線層時，於開設通孔時，使用SiCN膜作為抗蝕圖案之防反射膜之製造方法。
[專利文獻1]日本特開2004-221275號公報
[專利文獻2]日本特開2003-124307號公報
[專利文獻3]日本特開2003-163265號公報
本發明人檢討之藉由雙道金屬鑲嵌法形成多層銅布線之步驟的概要如下。
(步驟1)首先，使用先前熟知之方法，在半導體基板上形成半導體元件，並在半導體元件之上部形成下層布線。
(步驟2)其次，在下層布線之上部堆積層間絕緣膜，在層間絕緣膜上形成防反射膜後，在防反射膜上形成光阻膜。光阻膜藉由使用形成有通孔圖案之光罩進行曝光，繼續進行顯影，而轉印將通孔形成區域予以開口之圖案。形成防反射膜係為了防止將光阻膜予以曝光時，在下層布線之表面反射之曝光之光入射於光阻膜，而降低解像度。形成於光阻膜下層之防反射膜亦稱為BARC(底部防反射塗佈(Bottom Anti Reflective Coating))。
(步驟3)其次，將光阻膜作為遮罩，藉由乾式蝕刻防反射 膜及層間絕緣膜，而在層間絕緣膜中形成通孔。繼續除去光阻膜與防反射膜，在通孔之內部填充埋入劑。埋入劑包含與防反射膜大致相同組成之絕緣材料。在通孔之內部填充埋入劑時，於包含通孔之內部之層間絕緣膜上堆積埋入劑後，藉由回蝕除去通孔外部之埋入劑。進行該回蝕時，填充於通孔之埋入劑之表面形成大致平坦，且與層間絕緣膜之表面大致相同高度。
(步驟4)其次，在層間絕緣膜上形成第二防反射膜，在該防反射膜上形成第二光阻膜。第二光阻膜藉由使用形成有布線溝圖案之光罩進行曝光，繼續進行顯影，而轉印將布線溝形成區域予以開口之圖案。其次，藉由將第二光阻膜作為遮罩，乾式蝕刻第二防反射膜，繼續乾式蝕刻層間絕緣膜至其中途，而在通孔之上部形成布線溝。
(步驟5)其次，除去第二光阻膜後，除去第二防反射膜。除去第二防反射膜時，亦除去填充於通孔之埋入劑，使下層布線之表面露出於通孔之底部。而後，在布線溝及通孔之內部形成銅布線。形成銅布線時，係在包含布線溝及通孔內部之層間絕緣膜上，以濺鍍法或電鍍法堆積銅膜後，藉由化學性機械研磨法除去布線溝外部之銅膜。以下，藉由反覆進行上述步驟2~步驟5，而在半導體基板上形成多層銅布線。
一般而言，形成於半導體基板上之多層銅布線，如同上層之布線，寬度及厚度變大。因此，形成於上層之層間絕緣膜之通孔之直徑及深度亦比形成於下層之層間絕緣膜之 通孔大。
然而，通孔之直徑及深度變大時，在上述步驟3中，不易在通孔之內部良好地填充埋入劑。因而，在包含通孔之內部之層間絕緣膜上堆積埋入劑後，藉由回蝕除去通孔外部之埋入劑時，填充於通孔之埋入劑之表面不平坦，而在與層間絕緣膜之表面之間產生階差。因而發生在其次之步驟4中，無法在層間絕緣膜上均一地形成防反射膜之問題。
本發明之目的在提供一種良率佳地藉由雙道金屬鑲嵌法形成多層銅布線之技術。
本發明之其他目的在提供一種可簡化藉由雙道金屬鑲嵌法形成多層銅布線之步驟之技術。
本發明之上述及其他目的與新型特徵，從本說明書之內容及附圖即可明瞭。
本專利中揭示之發明中，代表性之發明概要簡單說明如下。
本發明之半導體積體電路裝置之製造方法，包含以下步驟：(a)在半導體基板之主面上形成半導體元件，在上述半導體元件之上部形成一層或數層第一布線；(b)在上述第一布線之上部形成第一層間絕緣膜，在上述第一層間絕緣膜之中途部形成第一停止膜；(c)在上述第一層間絕緣膜之上部形成第一防反射膜，在上述第一防反射膜之上部形成第一光阻膜；(d)將上述第一光阻膜作為遮罩，藉由蝕刻上述第一防反射膜、上述第一層間絕緣膜及上述第一停止膜， 而在上述第一層間絕緣膜中形成第一通孔；(e)除去上述第一光阻膜及上述第一防反射膜後，在上述第一通孔之內部填充第一埋入劑；(f)在上述步驟(e)之後，於上述第一層間絕緣膜之上部，不經由防反射膜，而形成第二光阻膜；(g)將上述第二光阻膜作為遮罩，藉由蝕刻包含形成有上述第一通孔區域之區域之上述第一層間絕緣膜，而在上述第一停止膜上部之上述第一層間絕緣膜上形成第一布線溝；及(h)除去上述第二光阻膜及上述第一埋入劑後，在上述第一布線溝及上述第一通孔之內部埋入金屬膜，而形成第二布線；藉由以光反射率低之材料構成上述第一停止膜，將形成於上述第一層間絕緣膜上部之上述第二光阻膜予以曝光，而轉印上述第一布線溝之圖案時，係利用上述第一停止膜作為防反射膜者。
本專利中揭示之發明中，藉由代表性之發明而獲得之效果簡單說明如下。
可良率佳地藉由雙道金屬鑲嵌法形成多層銅布線。此外，可簡化藉由雙道金屬鑲嵌法而形成多層銅布線之步驟。
以下，依據圖式詳細說明本發明之實施形態。另外，說明實施形態用之全部圖式中，原則上相同之構件上註記相同符號，並省略其重複說明。
(第一種實施形態)
本實施形態如係包含4層銅布線與保險絲之半導體積體 電路裝置，並使用圖1~圖26，按照步驟順序說明其製造方法。
首先，如圖1所示，如在包含單結晶矽之半導體基板(以下簡稱為基板)1之主面上，作為半導體元件而形成n通道型MISFET(Qn)及p通道型MISFET(Qp)。另外，圖中之符號2表示元件分離溝，符號4表示p型井，符號5表示n型井。
元件分離溝2係在蝕刻基板1而形成之溝內部，作為絕緣膜如埋入氧化矽膜3而形成。p型井4及n型井5係藉由在基板1上離子佈植p型雜質(硼)及n型雜質(磷)，繼續熱處理基板1，而使此等雜質擴散於基板1中而形成。
n通道型MISFET(Qn)藉由：包含形成於p型井4表面之氧化矽膜或氧氮化矽膜之閘極絕緣膜6，包含形成於閘極絕緣膜6上部之多結晶矽膜等之閘極電極7，包含形成於閘極電極7側壁之氧化矽膜等之側壁間隔物8，及形成於閘極電極7兩側之p型井4之一對n型半導體區域(源極、汲極)11等而構成。p通道型MISFET(Qp)係由：閘極絕緣膜6、閘極電極7、側壁間隔物8、及形成於閘極電極7兩側之n型井5之一對p型半導體區域(源極、汲極)12等而構成。構成n通道型MISFET(Qn)之閘極電極7之多結晶矽膜中導入n型雜質(磷)，在構成p通道型MISFET(Qp)之閘極電極7之多結晶矽膜中導入p型雜質(硼)。此外，在n通道型MISFET(Qn)之閘極電極7與n型半導體區域(源極、汲極)11之各個表面，及p通道型MISFET(Qp)之閘極電極7與p型半導體區域(源極、汲極)12之各個表面，形成矽化鈷(Co)膜9，使閘極電極7及源 極、汲極達到低電阻化。
其次，如圖2所示，在n通道型MISFET(Qn)及p通道型MISFET(Qp)之上部形成插塞16及第一層布線19，並經由插塞16而電性連接n通道型MISFET(Qn)及p通道型MISFET(Qp)與第一層布線19。
第一層布線19係由以下之方法而形成。首先，在基板1上堆積蝕刻停止膜13與絕緣膜14後，以化學性機械研磨法將絕緣膜14之表面予以平坦化。蝕刻停止膜13如由以CVD法堆積之氮化矽膜而構成，絕緣膜14如由以CVD法堆積之氧化矽膜而構成。
其次，蝕刻n通道型MISFET(Qn)之n型半導體區域(源極、汲極)11及p通道型MISFET(Qp)之p型半導體區域(源極、汲極)12之各個上部的絕緣膜14，繼續，蝕刻其下層之蝕刻停止膜13，而形成接觸孔15。其次，在接觸孔15之內部形成插塞16。插塞16如由氮化鈦(TiN)膜與鎢(W)膜之疊層膜而構成。此時，氮化鈦膜作為鎢膜之障壁金屬膜之功能。障壁金屬膜亦可由氮化鈦膜與鈦(Ti)膜之疊層膜而構成。
其次，在絕緣膜14之上部，以CVD法堆積膜厚為200nm程度之絕緣膜17(SiOC膜17)與膜厚為50nm程度之包含氧化矽膜之絕緣膜18後，將光阻膜(圖上未顯示)作為遮罩，藉由乾式蝕刻絕緣膜18及SiOC膜17，而形成布線溝20。絕緣膜17(SiOC膜17)係減少布線間電容用之低介電常數絕緣膜，如可採用具有介電常數比氧化矽膜(如TEOS(四乙氧基矽 烷)氧化膜)之介電常數低之絕緣膜。一般而言，將TEOS氧化膜之相對介電常數ε=4.1~4.2程度以下稱為低介電常數之絕緣膜。本實施形態中，其相對介電常數為2.7程度。形成於SiOC膜17上部之絕緣膜18，作為防止機械性強度低之SiOC膜17藉由化學性機械研磨而惡化之保護膜的功能。
其次，在布線溝20之內部，以濺鍍法堆積包含膜厚50 nm程度之氮化鈦膜，或氮化鈦膜與鈦膜之疊層膜之障壁金屬膜，繼續，以濺鍍法或電鍍法堆積完全埋入布線溝20內部之厚度(800 nm~1600 nm程度)之銅膜。障壁金屬膜作為防止銅膜擴散於周圍之絕緣膜中之障壁膜的功能。障壁金屬膜除氮化鈦膜之外，可使用氮化鎢(WN)膜及氮化鉭(TaN)膜等氮化金屬膜或在此等中添加矽之合金膜，或是鉭膜、鈦膜、鎢膜、鎢化鈦膜等高熔點金屬膜，或是此等高熔點金屬膜之疊層膜等，而不易與銅反應之各種導電膜。
其次，藉由化學性機械研磨法除去布線溝20外部之銅膜與障壁金屬膜，在布線溝20之內部埋入以銅為主要成分之金屬膜而形成。如此，形成包含保留於布線溝20內部之障壁金屬膜與銅膜之疊層膜之第一層布線19。
其次，如圖3所示，在第一層布線19之上層依序堆積障壁絕緣膜21、22、層間絕緣膜23及絕緣膜24。障壁絕緣膜21係防止第一層布線19材料之銅擴散於層間絕緣膜23中用之絕緣膜，如藉由以電漿CVD法堆積之膜厚為20 nm~100 nm程度之SiCN膜而構成。此外，障壁絕緣膜22係防止構成下層之障壁絕緣膜21之SiCN膜中包含之胺化合物擴散於層間 絕緣膜23中用之絕緣膜，如藉由以CVD法堆積之膜厚10 nm~100 nm程度之SiCO膜而構成。胺化合物擴散於層間絕緣膜23中時，在其次之步驟，胺化合物擴散於形成於絕緣膜24上層之光阻膜中，而可能導致光阻膜之感光功能鈍化。
層間絕緣膜23，為了減少在第一層布線19與爾後步驟中形成之第二層布線之間形成之電容，而由介電常數低之絕緣膜，如由上述之SiOC膜而構成。SiOC膜以CVD法堆積，其膜厚為460 nm程度。此外，層間絕緣膜23之低介電常數之膜亦可藉由塗佈法而形成。此外，形成於層間絕緣膜23上部之絕緣膜24，與下層之絕緣膜18相同，係藉由化學性機械研磨形成銅布線時，為了保護包含機械性強度低之SiOC膜之層間絕緣膜23用的絕緣膜，如由以CVD法堆積之膜厚50 nm程度之氧化矽膜而構成。
其次，如圖4所示，在絕緣膜24上形成防反射膜25，在防反射膜25上形成光阻膜26。防反射膜25係為了防止將光阻膜26予以曝光時，在第一層布線19之表面反射之曝光之光入射於光阻膜26造成解像度降低而形成。防反射膜係稱為BARC(底部防反射塗佈)之膜，且係折射率比基底之絕緣膜24及層間絕緣膜23高之膜。光阻膜26藉由使用形成有通孔圖案之光罩(圖上未顯示)進行曝光，繼續進行顯影，而轉印將通孔形成區域予以開口之圖案。
其次，如圖5所示，將光阻膜26作為遮罩，藉由依序乾式蝕刻防反射膜25、絕緣膜24及層間絕緣膜23，而在第一層布線19之上部形成通孔27。
其次，除去光阻膜26與防反射膜25。此時，以上述之BARC形成防反射膜25時，因膜之組成與光阻膜26類似，因此可藉由一次洗淨而同時除去光阻膜26及防反射膜25。而後如圖6所示，在通孔27之內部填充埋入劑28。埋入劑28包含與防反射膜25大致相同組成之絕緣材料。填充埋入劑28時，係在包含通孔27內部之絕緣膜24上旋轉塗佈埋入劑28使其硬化後，藉由回蝕而除去通孔27外部之埋入劑28。連接第一層布線19與爾後形成之第二層布線之通孔27之直徑比較小。因而，進行該回蝕時，填充於通孔27之埋入劑28表面成為大致平坦之面，且與絕緣膜24之表面大致同高。
其次，如圖7所示，在絕緣膜24上形成防反射膜30，並在防反射膜30上形成光阻膜31。本實施形態中，防反射膜30使用上述之BARC。光阻膜31藉由使用形成有布線溝圖案之光罩(圖上未顯示)進行曝光，繼續進行顯影，而轉印將布線溝形成區域予以開口之圖案。
其次，如圖8所示，將光阻膜31作為遮罩，依序乾式蝕刻防反射膜30及絕緣膜24，繼續藉由乾式蝕刻層間絕緣膜23至其中途，而形成布線溝32。此時，由於層間絕緣膜23中不存在成為蝕刻停止器之膜，因此布線溝32形成之蝕刻係藉由時間控制來進行。亦如後述所示，由於下層之布線尺寸係比上層之布線尺寸微細地佈局，因此形成介電常數比層間絕緣膜23高之膜時，布線間電容增大。本實施形態藉由不在層間絕緣膜23中形成蝕刻停止膜，可減少布線間之電容。此外，由於下層布線溝之深度係比上層布線溝之深 度淺地佈局，因此，布線溝形成時之蝕刻量減少，因而，即使不特別設置蝕刻停止膜，仍可藉由蝕刻之時間控制來控制膜厚。
其次，除去光阻膜31後，如圖9所示，藉由乾式蝕刻除去絕緣膜24上之防反射膜30。此時，亦蝕刻填充於通孔27之埋入劑28與其下層之障壁絕緣膜22、21，而使第一層布線19之表面露出於通孔27之底部。
其次，如圖10所示，在布線溝32及通孔27之內部形成第二層布線33。形成第二層布線33時，首先，在包含布線溝32及通孔27內部之絕緣膜24上，藉由濺鍍法堆積50 nm程度之薄氮化鈦膜(障壁金屬膜)。繼續，在該氮化鈦膜上，以濺鍍法或電鍍法堆積完全埋入布線溝32及通孔27內部之厚銅膜後，藉由化學性機械研磨法除去布線溝32外部之銅膜與障壁金屬膜。此時，由於絕緣膜24之機械性強度比層間絕緣膜23強，因此作為層間絕緣膜23之保護膜的功能。
其次，如圖11所示，在第二層布線33之上層堆積障壁絕緣膜34、層間絕緣膜35及防反射膜36後，將形成於防反射膜36上之光阻膜37作為遮罩，藉由乾式蝕刻防反射膜36及層間絕緣膜35，而在第二層布線33之上部形成通孔38。
障壁絕緣膜34與覆蓋第一層布線19表面之障壁絕緣膜21相同，係防止布線材料之銅擴散於層間絕緣膜35中用之絕緣膜，如由藉由電漿CVD法堆積之膜厚20 nm~100 nm程度之SiCN膜而構成。
一般而言，由於形成於基板1上之多層布線如同上層之布 線，各布線之間隔加寬，因此布線間電容變小。因此，層間絕緣膜35於爾後步驟中形成之各第三層布線，及第三層布線與第二層布線33間之電容無問題時，如由以CVD法堆積之膜厚700 nm程度之氧化矽膜而構成。由於氧化矽膜之膜質比低介電常數材料之SiCO膜緻密，因此以氧化矽膜構成層間絕緣膜35時，即使在包含SiCN膜之障壁絕緣膜34上直接堆積層間絕緣膜35，不致發生胺化合物擴散之問題。另外，由於SiCN膜與氧化矽膜之接合性較低，因此基於提高障壁絕緣膜34與層間絕緣膜35之接合性之目的，亦可在兩者之間形成SiCO膜。此外，構成層間絕緣膜35之氧化矽系材料，亦可使用添加氟(F)，而降低介電常數之氧化矽。
另外，各第三層布線(43)及第三層布線(43)與第二層布線33之間之電容成為問題時，係由SiCO膜之低介電常數材料構成層間絕緣膜35。此時，須在障壁絕緣膜34與層間絕緣膜35之間形成SiCO膜，防止障壁絕緣膜34中之胺化合物擴散。以下說明以氧化矽膜構成層間絕緣膜35之情況。
其次，除去光阻膜37與防反射膜36後，如圖12所示，在通孔38之內部填充埋入劑39。如上述，埋入劑39包含與上述防反射膜大致相同組成之絕緣材料。埋入劑39之填充方法亦與在上述之通孔27內部填充埋入劑28之方法相同。由於連接第二層布線33與爾後形成之第三層布線之通孔38直徑比較小，因此填充於通孔38之埋入劑39之表面成為大致平坦之面，且與層間絕緣膜35之表面大致同高。
其次，如圖13所示，在層間絕緣膜35中形成布線溝42。 形成布線溝42時，係在層間絕緣膜35上形成防反射膜40，並在防反射膜40上形成光阻膜41後，將光阻膜41作為遮罩，乾式蝕刻防反射膜40，繼續乾式蝕刻層間絕緣膜35至其中途。本實施形態中，與上述布線溝32之形成同樣地，係藉由時間控制之蝕刻而形成布線溝42。
其次，如圖14所示，在布線溝42及通孔38之內部形成第三層布線43。形成第三層布線43時，首先，除去光阻膜41，繼續以乾式蝕刻除去防反射膜40。除去防反射膜40時，亦除去填充於通孔38之埋入劑39與其下層之障壁絕緣膜34，而使第二層布線33之表面露出於通孔38之底部。其次，在包含布線溝42及通孔38內部之層間絕緣膜35上，以濺鍍法堆積薄氮化鈦膜(障壁金屬膜)，繼續，在該氮化鈦膜上，以濺鍍法或電鍍法堆積厚銅膜後，藉由化學性機械研磨法除去布線溝42外部之銅膜與障壁金屬膜。
其次，如圖15所示，在第三層布線43之上層堆積障壁絕緣膜44與層間絕緣膜45。障壁絕緣膜44係防止銅擴散用之絕緣膜，且與下層之障壁絕緣膜34,21相同，係由以電漿CVD法堆積之膜厚50 nm~100 nm程度之SiCN膜而構成。在其次之步驟中，形成於層間絕緣膜45中之第四層布線與下層之布線比較，其布線之尺寸、各布線之間隔及布線之膜厚較大。因此，層間絕緣膜45係由以CVD法堆積之膜厚為1 μm程度之氧化矽膜而構成。另外，在障壁絕緣膜44與層間絕緣膜45之間，基於提高兩者接合性之目的，亦可形成SiCO膜。此外，構成層間絕緣膜45之氧化矽系材料，亦可使用 添加氟而降低介電常數之氧化矽。
層間絕緣膜45之膜厚變大時，蝕刻層間絕緣膜45至其中途，而形成布線溝時，高精密度控制布線溝之深度困難。亦即，由於布線溝52、53之深度比上述之布線溝32、42深，因此，不易如上述之布線溝32、42藉由時間控制之蝕刻而形成。因此，係將蝕刻選擇比具有與層間絕緣膜45不同之蝕刻選擇比之停止膜46形成於層間絕緣膜45之中途，藉由在停止膜46之表面停止蝕刻，來控制布線溝之深度。本實施形態中，形成於層間絕緣膜45中途之停止膜46，係使用以電漿CVD法堆積之膜厚10 nm~100 nm程度之SiCN膜。由於SiCN膜對氧化矽膜之蝕刻選擇比大，且介電常數低，因此可用作停止膜46。此外，由於具有光之反射率低(折射率比層間絕緣膜45小)之特性，因此如後述，亦可作為防反射膜之功能。
其次，如圖16所示，在層間絕緣膜45上形成防反射膜47後，將形成於防反射膜47上之光阻膜48作為遮罩，藉由依序乾式蝕刻防反射膜47、層間絕緣膜45、停止膜46及層間絕緣膜45，而在第三層布線43之上部形成通孔38。
其次，除去光阻膜48與防反射膜47後，如圖17所示，在通孔49之內部填充埋入劑50。埋入劑50之材料及填充方法與上述者相同。不過，由於形成第四層布線用之通孔49之直徑及深度比下層之通孔38、27大，不易良好地埋入埋入劑50。因此，填充於通孔49之埋入劑50表面不平坦，且在與層間絕緣膜45表面之間產生階差。
其次，如圖18所示，在層間絕緣膜45上形成光阻膜51。如上述，由於填充於通孔49之埋入劑50表面不平坦，且在與層間絕緣膜45表面之間產生階差，因此，在層間絕緣膜45之表面全體塗佈均一膜厚之防反射膜困難。因此，此時不使用防反射膜，而係在層間絕緣膜45上直接形成光阻膜51。
光阻膜51藉由使用形成有布線溝圖案與保險絲圖案之光罩(圖上未顯示)進行曝光，繼續進行顯影，而轉印將布線溝形成區域與保險絲形成區域予以開口之圖案。如上述，在層間絕緣膜45之中途形成有以光之反射率低之SiCN膜構成之停止膜46。因而，即使不在光阻膜51之下層形成防反射膜，仍可抑制第三層布線43表面反射之曝光之光入射於光阻膜51，而使解像度降低之問題。藉此，由於不需要在光阻膜51下層形成防反射膜之步驟，因此可簡化步驟。因而，在形成於層間絕緣膜45中途之停止膜46中，要求蝕刻選擇比與氧化矽膜不同、光之反射率低及介電常數低。此種絕緣材料除上述之SiCN之外，如有氮化矽(SiN)及氧氮化矽(SiON)，不過，其中最宜為SiCN。
其次，如圖19所示，將光阻膜51作為遮罩，乾式蝕刻層間絕緣膜45，在停止膜46之表面停止蝕刻。藉此，在停止膜46上層之層間絕緣膜45中形成布線溝52、53。
其次，除去光阻膜51後，如圖20所示，藉由乾式蝕刻除去填充於通孔49之埋入劑50，而使第三層布線43之表面露出於通孔49之底部。
其次，如圖21所示，在布線溝52及通孔49之內部形成第四層布線54，並在布線溝53之內部形成成為保險絲55之第四層布線54。保險絲55經由下層布線而連接於電阻元件，不過圖上並未顯示。電阻元件使用與MISFET(Qn,Qp)之閘極電極7同層之多結晶矽膜而形成。因此，藉由後述之探針測試，而在CMOS記憶體之一部分發現瑕疵時，藉由使用雷射光束等切斷保險絲55，使電阻元件之電阻值變化，而將瑕疵記憶體替換成冗長記憶體。
形成第四層布線54及保險絲55時，在包含布線溝52、53及通孔49內部之層間絕緣膜45上，以濺鍍法堆積薄的氮化鈦膜(障壁金屬膜)，繼續，在該氮化鈦膜上，以濺鍍法或電鍍法堆積厚的銅膜後，藉由化學性機械研磨法除去布線溝52、53外部之銅膜與障壁金屬膜。
此外，層間絕緣膜45中保留有蝕刻停止膜46，不過，與下層之第一、第二及第三布線層比較時，上層之第四布線層佈局成其布線間距離較大，且層間絕緣膜45之膜厚形成較厚，因此可大致忽略布線間電容及布線層間電容之增加。
其次，如圖22所示，在第四層布線54及保險絲55之上層堆積障壁絕緣膜56與層間絕緣膜57。障壁絕緣膜56係防止銅擴散用之絕緣膜，且與下層之障壁絕緣膜44、34、21相同，係由以電漿CVD法堆積之SiCN膜而構成。層間絕緣膜57與下層之層間絕緣膜45,35相同，係由氧化矽系之絕緣膜而構成，膜厚為900 nm程度。另外，在圖22及以下之圖中，省略第四層布線54更下層部分之圖示。
如後述，在第四層布線54及保險絲55之上層形成層間絕緣膜與表面保護膜。此外，在保險絲55上部之層間絕緣膜與表面保護膜中形成照射雷射光束於保險絲55用之開口。因而，外部之水分通過該開口而侵入電路內時，可能造成保險絲55腐蝕。因此，本實施形態形成上述障壁絕緣膜56之膜厚比下層之障壁絕緣膜44、34、21之膜厚大(如為150 nm~200 nm程度)，使保險絲55之耐濕性提高。
其次，如圖23所示，在層間絕緣膜57之上部形成最上層布線(第五層布線)60，繼續，在最上層布線60之上部形成表面保護膜61。形成最上層布線60時，首先，將光阻膜(圖上未顯示)作為遮罩，而乾式蝕刻第四層布線54上層之層間絕緣膜57，繼續乾式蝕刻其下層之障壁絕緣膜56，而形成穿通孔58後，在穿通孔58之內部形成插塞59。插塞59與下層之插塞16相同，係以氮化鈦膜與鎢膜之疊層膜而構成。其次，在層間絕緣膜57之上部，以濺鍍法堆積膜厚50 nm~100 nm程度之氮化鈦膜、膜厚1 μm程度之鋁(Al)合金膜及膜厚50 nm~100 nm程度之氮化鈦膜，將光阻膜(圖上未顯示)作為遮罩，藉由蝕刻此等之導電膜，而形成最上層布線60。此外，最上層布線60上部之表面保護膜61係由以電漿CVD法堆積之膜厚200 nm程度之氧化矽膜與膜厚600 nm程度之氮化矽膜之疊層膜而構成。
其次，如圖24所示，將光阻膜(圖上未顯示)作為遮罩而乾式蝕刻表面保護膜61，藉由使最上層布線60之一部分露出，而形成接合焊墊60B。此外，藉由乾式蝕刻保險絲55 上層之表面保護膜61及層間絕緣膜57，而形成開口62。此時，在覆蓋保險絲55之障壁絕緣膜56表面停止蝕刻，而在保險絲55之上部保留障壁絕緣膜56。
此時，由於形成保險絲55上部之障壁絕緣膜56之膜厚比下層之障壁絕緣膜44、34、21厚，因此可確保耐濕性。亦即，如上述之障壁絕緣膜56之膜厚與下層之障壁絕緣膜44、34、21之膜厚相等時，如藉由在保險絲55上部形成開口62時之蝕刻步驟、除去光阻膜時之氧電漿灰化步驟及其他洗淨步驟等，障壁絕緣膜56之膜厚更薄，而隨之發生耐濕性降低之問題。特別是開口62之蝕刻需要蝕刻比下層之層間絕緣膜更厚之膜厚，可能因過度蝕刻而發生障壁絕緣膜56之膜厚減少。因此，如本實施形態，需要將障壁絕緣膜56之膜厚形成比下層之障壁絕緣膜44、34、21厚。
其次，在接合焊墊60B之表面抵接探針(圖上未顯示)，進行電路之電性測試(探針測試)。經該探針測試而在半導體元件之一部分發現瑕疵情況下，藉由通過開口62照射雷射光束於保險絲55，切斷保險絲55，而將瑕疵記憶體替換成冗長記憶體。
此外，保留於保險絲55上之絕緣膜，只須具有可藉由後述之雷射光束照射而切斷之膜厚即可，依需要亦可保留絕緣膜57。
其次，如圖25所示，在表面保護膜61上堆積聚醯亞胺樹脂膜63後，藉由在聚醯亞胺樹脂膜63之上部形成引出布線64，而電性連接接合焊墊60B與引出布線64。該引出布線64 係電性連接構成CMOS記憶體之外部連接端子之焊接凸塊與接合焊墊60B用之布線。形成引出布線64時，首先，係在表面保護膜61上堆積聚醯亞胺樹脂膜63，繼續將光阻膜(圖上未顯示)作為遮罩，藉由蝕刻接合焊墊60B上部之聚醯亞胺樹脂膜63，而使接合焊墊60B之表面露出。其次，在表面保護膜61上形成將形成引出布線64之區域予以開口之光阻膜(圖上未顯示)後，使用電鍍法或濺鍍法，在表面保護膜61上堆積銅膜。
其次，如圖26所示，以聚醯亞胺樹脂膜65覆蓋包含銅膜之引出布線64表面後，藉由蝕刻聚醯亞胺樹脂膜65之一部分，使引出布線64之一端部露出，而在其表面，以電鍍法形成金(Au)膜66。而後，藉由在金(Au)膜66之表面以印刷法形成焊接凸塊67，而形成半導體積體電路裝置之外部連接端子。
上述引出布線64之形成步驟，保險絲55上部之障壁絕緣膜56雖亦因蝕刻處理及光阻膜之灰化處理而變薄，但是，藉由預先增加障壁絕緣膜56之膜厚，可防止耐濕性惡化。
(第二種實施形態)
上述第一種實施形態係說明在層間絕緣膜中形成通孔後，形成布線溝之情況，而本實施形態係說明在層間絕緣膜中形成布線溝後，形成通孔之情況。
首先，如圖27所示，在第三層布線43之上層堆積障壁絕緣膜44與層間絕緣膜45。此外，在層間絕緣膜45之中途形成停止膜46。停止膜46係使用以電漿CVD法堆積之膜厚10 nm~100 nm程度之SiCN膜。至此之步驟與上述第一種實施形態之圖1~圖15所示之步驟相同。
其次，如圖28所示，在層間絕緣膜45上形成光阻膜51後，將光阻膜51作為遮罩而乾式蝕刻層間絕緣膜45，藉由在停止膜46之表面停止蝕刻，而在停止膜46上層之層間絕緣膜45中形成布線溝52、53。此時，並未在層間絕緣膜45與光阻膜51之間形成防反射膜，不過與上述第一種實施形態相同，係在層間絕緣膜45之中途形成以光反射率低之SiCN膜構成之停止膜46。因而，即使光阻膜51之下層不形成防反射膜，仍可抑制在第三層布線43表面反射之曝光之光入射於光阻膜51而使解像度降低之問題。
其次，如圖29所示，在層間絕緣膜45上形成光阻膜48後，將光阻膜48作為遮罩，藉由乾式蝕刻層間絕緣膜45及障壁絕緣膜44而形成通孔38，使第三層布線43露出於通孔38之底部。此時，由於停止膜46作為防反射膜之功能，因此，仍可抑制在第三層布線43表面反射之曝光之光入射於光阻膜48而使解像度降低之問題。
其次，除去光阻膜48後，如圖30所示，在布線溝52及通孔49之內部形成第四層布線54，並在布線溝53之內部形成保險絲55。形成第四層布線54及保險絲55之方法與上述第一種實施形態中說明之方法相同。
如此，在層間絕緣膜45中形成布線溝52、53後，形成通孔38之本實施形態中，亦可簡化第四層布線54之形成步驟。此外，可良率佳地形成第四層布線54。
以上，係依據實施形態具體說明本發明人之發明，不過，本發明並不限定於上述實施形態，在不脫離其要旨之範圍內，當然可作各種變更。如本發明亦可適用於包含5層以上銅布線之半導體積體電路裝置之製造方法。
[產業上之可利用性]
本發明係有效適用於使用雙道金屬鑲嵌法而形成多層布線之半導體積體電路裝置者。
1‧‧‧半導體基板
2‧‧‧元件分離溝
3‧‧‧氧化矽膜
4‧‧‧p型井
5‧‧‧n型井
6‧‧‧閘極絕緣膜
7‧‧‧閘極電極
8‧‧‧側壁間隔物
9‧‧‧矽化鈷膜
11‧‧‧n型半導體區域(源極、汲極)
12‧‧‧p型半導體區域(源極、汲極)
13‧‧‧蝕刻停止膜
14‧‧‧絕緣膜
15‧‧‧接觸孔
16‧‧‧插塞
17‧‧‧絕緣膜(SiOC膜)
18‧‧‧絕緣膜
19‧‧‧第一層布線
20‧‧‧布線溝
21、22‧‧‧障壁絕緣膜
23‧‧‧層間絕緣膜
24‧‧‧絕緣膜
25‧‧‧防反射膜
26‧‧‧光阻膜
27‧‧‧通孔
28‧‧‧埋入劑
30‧‧‧防反射膜
31‧‧‧光阻膜
32‧‧‧布線溝
33‧‧‧第二層布線
34‧‧‧障壁絕緣膜
35‧‧‧層間絕緣膜
36‧‧‧防反射膜
37‧‧‧光阻膜
38‧‧‧通孔
39‧‧‧埋入劑
40‧‧‧防反射膜
41‧‧‧光阻膜
42‧‧‧布線溝
43‧‧‧第三層布線
44‧‧‧障壁絕緣膜
45‧‧‧層間絕緣膜
46‧‧‧停止膜
47‧‧‧防反射膜
48‧‧‧光阻膜
49‧‧‧通孔
50‧‧‧埋入劑
51‧‧‧光阻膜
52、53‧‧‧布線溝
54‧‧‧第四層布線
55‧‧‧保險絲
56‧‧‧障壁絕緣膜
57‧‧‧層間絕緣膜
58‧‧‧穿通孔
59‧‧‧插塞
60‧‧‧最上層布線(第五層布線)
60B‧‧‧接合焊墊
61‧‧‧表面保護膜
62‧‧‧開口
63‧‧‧聚醯亞胺樹脂膜
64‧‧‧引出布線
65‧‧‧聚醯亞胺樹脂膜
66‧‧‧金膜
67‧‧‧焊接凸塊
Qn‧‧‧n通道型MISFET
Qp‧‧‧p通道型MISFET
圖1係顯示本發明一種實施形態之半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖2係繼續圖1顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖3係繼續圖2顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖4係繼續圖3顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖5係繼續圖4顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖6係繼續圖5顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖7係繼續圖6顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖8係繼續圖7顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖9係繼續圖8顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖10係繼續圖9顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖11係繼續圖10顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖12係繼續圖11顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖13係繼續圖12顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖14係繼續圖13顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖15係繼續圖14顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖16係繼續圖15顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖17係繼續圖16顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖18係繼續圖17顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖19係繼續圖18顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖20係繼續圖19顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖21係繼續圖20顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖22係繼續圖21顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖23係繼續圖22顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖24係繼續圖23顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖25係繼續圖24顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖26係繼續圖25顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖27係顯示本發明其他實施形態之半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖28係繼續圖27顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖29係繼續圖28顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
圖30係繼續圖29顯示半導體積體電路裝置之製造方法之半導體基板之重要部分剖面圖。
1‧‧‧半導體基板
2‧‧‧元件分離溝
3‧‧‧氧化矽膜
4‧‧‧p型井
5‧‧‧n型井
6‧‧‧閘極絕緣膜
7‧‧‧閘極電極
8‧‧‧側壁間隔物
9‧‧‧矽化鈷膜
11‧‧‧n型半導體區域(源極、汲極)
12‧‧‧p型半導體區域(源極、汲極)
13‧‧‧蝕刻停止膜
14‧‧‧絕緣膜
15‧‧‧接觸孔
16‧‧‧插塞
17‧‧‧絕緣膜(SiOC膜)
18‧‧‧絕緣膜
19‧‧‧第一層布線
20‧‧‧布線溝
21,22‧‧‧障壁絕緣膜
23‧‧‧層間絕緣膜
24‧‧‧絕緣膜
27‧‧‧通孔
32‧‧‧布線溝
33‧‧‧第二層布線
34‧‧‧障壁絕緣膜
35‧‧‧層間絕緣膜
38‧‧‧通孔
42‧‧‧布線溝
43‧‧‧第三層布線
44‧‧‧障壁絕緣膜
45‧‧‧層間絕緣膜
46‧‧‧停止膜
49‧‧‧通孔
50‧‧‧埋入劑
51‧‧‧光阻膜
52,53‧‧‧布線溝
Qn‧‧‧n通道型MISFET
Qp‧‧‧p通道型MISFET

Claims (9)

  1. 一種半導體裝置，其特徵在於包含：第一布線，其係形成於半導體基板上且以銅為主成份；第一障壁絕緣膜，其係直接形成於上述第一布線上，且具有防止銅之擴散之功能；第二障壁絕緣膜，其係形成於上述第一障壁絕緣膜上；第一層間絕緣膜，其係形成於上述第二障壁絕緣膜上；第二布線，其係形成於上述第一層間絕緣膜中且以銅為主成份；第三障壁絕緣膜，其係直接形成於上述第二布線上，且具有防止銅之擴散之功能；及第二層間絕緣膜，其係形成於上述第三障壁絕緣膜上；且上述第一障壁絕緣膜係形成於上述第一布線與上述第二障壁絕緣膜之間；上述第二障壁絕緣膜係形成於上述第一障壁絕緣膜與上述第一層間絕緣膜之間；上述第一障壁絕緣膜與上述第二障壁絕緣膜之膜厚係分別小於上述第一層間絕緣膜之膜厚；上述第三障壁絕緣膜之膜厚係小於上述第二層間絕緣膜之膜厚； 上述第一層間絕緣膜係包含Si、O及C；上述第二層間絕緣膜係包含氧化矽膜或添加有氟之氧化矽膜；上述第一障壁絕緣膜之氮的濃度係高於上述第二障壁絕緣膜之氮的濃度。
  2. 如請求項1之半導體裝置，其中：上述第一層間絕緣膜之膜厚係小於上述第二層間絕緣膜之膜厚。
  3. 如請求項2之半導體裝置，其中：上述第三障壁絕緣膜係以與上述第一障壁絕緣膜相同之材料所形成；上述第二障壁絕緣膜係以與上述第一障壁絕緣膜及上述第三障壁絕緣膜不同之材料所形成。
  4. 如請求項3之半導體裝置，其中：上述第一障壁絕緣膜係包含Si、C及N；上述第二障壁絕緣膜係包含Si、C及O；上述第三障壁絕緣膜係包含Si、C及N。
  5. 一種半導體裝置，其特徵在於包含：第一布線，其係形成於半導體基板上且以銅為主成份；第一障壁絕緣膜，其係直接形成於上述第一布線上，且具有防止銅之擴散之功能；第二障壁絕緣膜，其係形成於上述第一障壁絕緣膜上； 第一層間絕緣膜，其係形成於上述第二障壁絕緣膜上；第二布線，其係形成於上述第一層間絕緣膜中且以銅為主成份；第三障壁絕緣膜，其係直接形成於上述第二布線上，且具有防止銅之擴散之功能；及第二層間絕緣膜，其係形成於上述第三障壁絕緣膜上；且上述第一障壁絕緣膜係形成於上述第一布線與上述第二障壁絕緣膜之間；上述第二障壁絕緣膜係形成於上述第一障壁絕緣膜與上述第一層間絕緣膜之間；上述第一障壁絕緣膜與上述第二障壁絕緣膜之膜厚係分別小於上述第一層間絕緣膜之膜厚；上述第三障壁絕緣膜之膜厚係小於上述第二層間絕緣膜之膜厚；上述第一層間絕緣膜係包含Si、O及C；上述第二層間絕緣膜係包含氧化矽膜或添加有氟之氧化矽膜；上述第一障壁絕緣膜及上述第三障壁絕緣膜係分別包含有氮；上述第二障壁絕緣膜不包含氮。
  6. 如請求項5之半導體裝置，其中：上述第一層間絕緣膜之膜厚係小於上述第二層間絕 緣膜之膜厚。
  7. 如請求項6之半導體裝置，其中：上述第三障壁絕緣膜係以與上述第一障壁絕緣膜相同之材料所形成；上述第二障壁絕緣膜係以與上述第一障壁絕緣膜及上述第三障壁絕緣膜不同之材料所形成。
  8. 如請求項7之半導體裝置，其中：上述第一障壁絕緣膜係包含Si、C及N；上述第二障壁絕緣膜係包含Si、C及O；上述第三障壁絕緣膜係包含Si、C及N。
  9. 一種半導體裝置，其特徵在於包含：第一布線，其係形成於半導體基板上且以銅為主成份；第一障壁絕緣膜，其係直接形成於上述第一布線上，且具有防止銅之擴散之功能；第二障壁絕緣膜，其係形成於上述第一障壁絕緣膜上；第一層間絕緣膜，其係形成於上述第二障壁絕緣膜上；第二布線，其係形成於第一層間絕緣膜中且以銅為主成份；第三障壁絕緣膜，其係直接形成於上述第二布線上，且具有防止銅之擴散之功能；及第二層間絕緣膜，其係形成於上述第三障壁絕緣膜 上；且上述第一障壁絕緣膜係形成於上述第一布線與上述第二障壁絕緣膜之間；上述第二障壁絕緣膜係形成於上述第一障壁絕緣膜與上述第一層間絕緣膜之間；上述第一障壁絕緣膜與上述第二障壁絕緣膜之膜厚係分別小於上述第一層間絕緣膜之膜厚；上述第三障壁絕緣膜之膜厚係小於上述第二層間絕緣膜之膜厚；上述第一層間絕緣膜之膜厚係小於上述第二層間絕緣膜之膜厚；上述第一層間絕緣膜係包含Si、O及C；上述第二層間絕緣膜係包含氧化矽膜或添加有氟之氧化矽膜；上述第一障壁絕緣膜係包含Si、C及N；上述第二障壁絕緣膜係包含Si、C及O；上述第三障壁絕緣膜係包含Si、C及N；上述第三障壁絕緣膜係以與上述第一障壁絕緣膜相同之材料所形成；上述第二障壁絕緣膜係以與上述第一障壁絕緣膜及上述第三障壁絕緣膜不同之材料所形成。
TW102102115A 2005-07-06 2006-06-22 Semiconductor integrated circuit device and method for manufacturing semiconductor integrated circuit device TWI525747B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005197938A JP5096669B2 (ja) 2005-07-06 2005-07-06 半導体集積回路装置の製造方法

Publications (2)

Publication Number Publication Date
TW201322372A true TW201322372A (zh) 2013-06-01
TWI525747B TWI525747B (zh) 2016-03-11

Family

ID=37597708

Family Applications (3)

Application Number Title Priority Date Filing Date
TW095122404A TWI385757B (zh) 2005-07-06 2006-06-22 Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device
TW102102115A TWI525747B (zh) 2005-07-06 2006-06-22 Semiconductor integrated circuit device and method for manufacturing semiconductor integrated circuit device
TW098120878A TWI389254B (zh) 2005-07-06 2006-06-22 Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device

Family Applications Before (1)

Application Number Title Priority Date Filing Date
TW095122404A TWI385757B (zh) 2005-07-06 2006-06-22 Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW098120878A TWI389254B (zh) 2005-07-06 2006-06-22 Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device

Country Status (5)

Country Link
US (17) US7354855B2 (zh)
JP (1) JP5096669B2 (zh)
KR (2) KR101328862B1 (zh)
CN (2) CN100559565C (zh)
TW (3) TWI385757B (zh)

Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5096669B2 (ja) * 2005-07-06 2012-12-12 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
JP4699172B2 (ja) * 2005-10-25 2011-06-08 ルネサスエレクトロニクス株式会社 半導体装置
JP4830455B2 (ja) * 2005-11-10 2011-12-07 ルネサスエレクトロニクス株式会社 半導体装置
US20080272435A1 (en) * 2007-05-02 2008-11-06 Chien-Ting Lin Semiconductor device and method of forming the same
US7825010B2 (en) * 2007-06-07 2010-11-02 Micron Technology, Inc. Die singulation methods
KR100854863B1 (ko) * 2007-06-29 2008-08-28 주식회사 하이닉스반도체 반도체 소자의 제조방법
CN101110393B (zh) * 2007-07-05 2012-03-07 复旦大学 一种CuxO电阻存储器制备与铜互连工艺集成的方法
US7936072B2 (en) 2007-11-12 2011-05-03 Renesas Electronics Corporation Semiconductor device having dual damascene structure
WO2009153834A1 (ja) * 2008-06-18 2009-12-23 富士通株式会社 半導体装置とその製造方法
DE102008044984A1 (de) * 2008-08-29 2010-07-15 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit Verspannungsrelaxationsspalte zur Verbesserung der Chipgehäusewechselwirkungsstabilität
US8338265B2 (en) 2008-11-12 2012-12-25 International Business Machines Corporation Silicided trench contact to buried conductive layer
JP5559775B2 (ja) * 2009-04-30 2014-07-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US8227339B2 (en) 2009-11-02 2012-07-24 International Business Machines Corporation Creation of vias and trenches with different depths
JP5622433B2 (ja) * 2010-04-28 2014-11-12 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US8946904B2 (en) * 2010-08-27 2015-02-03 Avago Technologies General Ip (Singapore) Pte. Ltd. Substrate vias for heat removal from semiconductor die
CN102386126B (zh) * 2010-09-03 2013-10-30 中芯国际集成电路制造(上海)有限公司 制作用于形成双大马士革结构的半导体器件结构的方法
JP5755471B2 (ja) * 2011-03-10 2015-07-29 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN102437090B (zh) * 2011-07-12 2015-01-14 上海华力微电子有限公司 无金属阻挡层的铜后道互连工艺
CN103094179B (zh) * 2011-10-27 2015-06-17 中芯国际集成电路制造(上海)有限公司 连接孔形成方法
US9553043B2 (en) * 2012-04-03 2017-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure having smaller transition layer via
US9111998B2 (en) 2012-04-04 2015-08-18 Samsung Electronics Co., Ltd Multi-level stack having multi-level contact and method
US9006101B2 (en) * 2012-08-31 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method
US9390937B2 (en) * 2012-09-20 2016-07-12 Applied Materials, Inc. Silicon-carbon-nitride selective etch
US9287162B2 (en) 2013-01-10 2016-03-15 Samsung Austin Semiconductor, L.P. Forming vias and trenches for self-aligned contacts in a semiconductor structure
US8994173B2 (en) 2013-06-26 2015-03-31 International Business Machines Corporation Solder bump connection and method of making
KR102063808B1 (ko) 2013-07-15 2020-01-08 삼성전자주식회사 정보 저장 소자의 제조 방법
US9040423B2 (en) * 2013-07-17 2015-05-26 United Microelectronics Corp. Method for manufacturing semiconductor device
WO2015095394A1 (en) * 2013-12-17 2015-06-25 Texas Instruments Incorporated Elongated contacts using litho-freeze-litho-etch process
US9997457B2 (en) * 2013-12-20 2018-06-12 Intel Corporation Cobalt based interconnects and methods of fabrication thereof
JP6282474B2 (ja) * 2014-01-31 2018-02-21 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2016025147A (ja) * 2014-07-17 2016-02-08 ソニー株式会社 電子デバイスおよびその製造方法、並びに電子機器
KR102258112B1 (ko) * 2015-04-01 2021-05-31 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US9583442B2 (en) * 2015-06-29 2017-02-28 International Business Machines Corporation Interconnect structure including middle of line (MOL) metal layer local interconnect on etch stop layer
RU2601203C1 (ru) * 2015-07-08 2016-10-27 Акционерное общество "Научно-производственная фирма "Микран" Монолитная интегральная схема на основе полупроводникового соединения
KR102415952B1 (ko) 2015-07-30 2022-07-05 삼성전자주식회사 반도체 소자의 레이아웃 설계 방법, 및 그를 이용한 반도체 소자의 제조 방법
CN108028224B (zh) * 2015-10-16 2022-08-16 索尼公司 半导体装置以及半导体装置的制造方法
KR102579880B1 (ko) 2016-05-12 2023-09-18 삼성전자주식회사 인터포저, 반도체 패키지, 및 인터포저의 제조 방법
WO2018035091A1 (en) 2016-08-15 2018-02-22 University Of Florida Research Foundation, Inc. Methods and compositions relating to tunable nanoporous coatings
US9711501B1 (en) * 2016-09-26 2017-07-18 International Business Machines Corporation Interlayer via
KR102616489B1 (ko) 2016-10-11 2023-12-20 삼성전자주식회사 반도체 장치 제조 방법
WO2018213570A2 (en) 2017-05-17 2018-11-22 University Of Florida Research Foundation Methods and sensors for detection
CN109411406A (zh) * 2017-08-18 2019-03-01 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
TWI628756B (zh) * 2017-08-22 2018-07-01 鳳凰先驅股份有限公司 封裝結構及其製作方法
KR102492733B1 (ko) 2017-09-29 2023-01-27 삼성디스플레이 주식회사 구리 플라즈마 식각 방법 및 디스플레이 패널 제조 방법
WO2019126248A1 (en) 2017-12-20 2019-06-27 University Of Florida Research Foundation Methods and sensors for detection
WO2019126171A1 (en) * 2017-12-21 2019-06-27 University Of Florida Research Foundation Substrates having a broadband antireflection layer and methods of forming a broadband antireflection layer
WO2019182872A1 (en) * 2018-03-19 2019-09-26 Lam Research Corporation Chamfer-less via integration scheme
US10727275B2 (en) * 2018-05-18 2020-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Memory layout for reduced line loading
WO2019246370A1 (en) 2018-06-20 2019-12-26 University Of Florida Research Foundation Intraocular pressure sensing material, devices, and uses thereof
JP6640391B2 (ja) * 2019-01-22 2020-02-05 ルネサスエレクトロニクス株式会社 半導体装置
US11171052B2 (en) * 2019-04-29 2021-11-09 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of forming interconnect structures with selectively deposited pillars and structures formed thereby
US11024533B2 (en) 2019-05-16 2021-06-01 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of forming interconnect structures using via holes filled with dielectric film
US11257755B2 (en) * 2020-06-15 2022-02-22 Taiwan Semiconductor Manufacturing Co., Ltd. Metal loss prevention in conductive structures
CN113013090B (zh) * 2021-02-07 2022-06-24 长鑫存储技术有限公司 半导体结构的熔断填充方法及半导体结构
US20220390833A1 (en) * 2021-06-03 2022-12-08 Viavi Solutions Inc. Method of replicating a microstructure pattern

Family Cites Families (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08191104A (ja) * 1995-01-11 1996-07-23 Hitachi Ltd 半導体集積回路装置およびその製造方法
FR2748601B1 (fr) * 1996-05-07 1998-07-24 Sgs Thomson Microelectronics Procede de formation d'interconnexions dans un circuit integre
US5886410A (en) * 1996-06-26 1999-03-23 Intel Corporation Interconnect structure with hard mask and low dielectric constant materials
US6025226A (en) * 1998-01-15 2000-02-15 International Business Machines Corporation Method of forming a capacitor and a capacitor formed using the method
JP2000077625A (ja) * 1998-08-31 2000-03-14 Hitachi Ltd 半導体集積回路装置の製造方法
JP2000156480A (ja) 1998-09-03 2000-06-06 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6406995B1 (en) 1998-09-30 2002-06-18 Intel Corporation Pattern-sensitive deposition for damascene processing
US6649515B2 (en) 1998-09-30 2003-11-18 Intel Corporation Photoimageable material patterning techniques useful in fabricating conductive lines in circuit structures
US20030089992A1 (en) 1998-10-01 2003-05-15 Sudha Rathi Silicon carbide deposition for use as a barrier layer and an etch stop
US6974766B1 (en) * 1998-10-01 2005-12-13 Applied Materials, Inc. In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application
EP1192656A1 (en) * 1999-06-30 2002-04-03 Intel Corporation Method of protecting an underlying wiring layer during dual damascene processing
US6159818A (en) * 1999-09-02 2000-12-12 Micron Technology, Inc. Method of forming a container capacitor structure
JP4858895B2 (ja) * 2000-07-21 2012-01-18 富士通セミコンダクター株式会社 半導体装置の製造方法
US6821896B1 (en) * 2001-05-31 2004-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method to eliminate via poison effect
JP2002373937A (ja) 2001-06-15 2002-12-26 Fujitsu Ltd 半導体装置及びその製造方法
JP3745257B2 (ja) * 2001-08-17 2006-02-15 キヤノン販売株式会社 半導体装置及びその製造方法
JP2003092349A (ja) * 2001-09-18 2003-03-28 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2003092287A (ja) * 2001-09-19 2003-03-28 Nec Corp アッシング方法
JP2003124307A (ja) 2001-10-15 2003-04-25 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2003163265A (ja) * 2001-11-27 2003-06-06 Nec Corp 配線構造およびその製造方法
US6605874B2 (en) * 2001-12-19 2003-08-12 Intel Corporation Method of making semiconductor device using an interconnect
JP2003309172A (ja) * 2002-04-17 2003-10-31 Nec Electronics Corp デュアルダマシンプロセスにおけるパターン形成方法
JP2003332426A (ja) 2002-05-17 2003-11-21 Renesas Technology Corp 半導体装置の製造方法および半導体装置
JP4040363B2 (ja) 2002-05-20 2008-01-30 富士通株式会社 半導体装置
US6617690B1 (en) 2002-08-14 2003-09-09 Ibm Corporation Interconnect structures containing stress adjustment cap layer
JP2004119698A (ja) * 2002-09-26 2004-04-15 Seiko Epson Corp 半導体装置およびその製造方法
TW582084B (en) * 2002-10-03 2004-04-01 Taiwan Semiconductor Mfg Method for manufacturing capacitor by combining dual damascene process and structure thereof
JP2004153015A (ja) * 2002-10-30 2004-05-27 Fujitsu Ltd 半導体装置及びその製造方法
DE10250889B4 (de) * 2002-10-31 2006-12-07 Advanced Micro Devices, Inc., Sunnyvale Verbesserte SiC-Barrierenschicht für eine Kupfermetallisierungsschicht mit einem Dielektrikum mit kleinem ε und Verfahren zur Herstellung derselben
US6709918B1 (en) * 2002-12-02 2004-03-23 Chartered Semiconductor Manufacturing Ltd. Method for making a metal-insulator-metal (MIM) capacitor and metal resistor for a copper back-end-of-line (BEOL) technology
JP3898133B2 (ja) 2003-01-14 2007-03-28 Ｎｅｃエレクトロニクス株式会社 ＳｉＣＨＮ膜の成膜方法。
DE10301243B4 (de) * 2003-01-15 2009-04-16 Infineon Technologies Ag Verfahren zum Herstellen einer integrierten Schaltungsanordnung, insbesondere mit Kondensatoranordnung
JP3683570B2 (ja) * 2003-02-19 2005-08-17 松下電器産業株式会社 半導体装置の製造方法
JP4454242B2 (ja) 2003-03-25 2010-04-21 株式会社ルネサステクノロジ 半導体装置およびその製造方法
US7021320B2 (en) * 2003-04-11 2006-04-04 Taiwan Semiconductor Manufacturing Co., Ltd. Method of removing a via fence
US20040222527A1 (en) * 2003-05-06 2004-11-11 Dostalik William W. Dual damascene pattern liner
US6977218B2 (en) 2003-07-17 2005-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method for fabricating copper interconnects
US7052990B2 (en) 2003-09-03 2006-05-30 Infineon Technologies Ag Sealed pores in low-k material damascene conductive structures
US7345350B2 (en) * 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
JP2005142369A (ja) 2003-11-06 2005-06-02 Renesas Technology Corp 半導体装置の製造方法
KR100534103B1 (ko) * 2004-01-14 2005-12-06 삼성전자주식회사 초임계 유체를 이용한 미세 전자소자의 제조 방법
US7015133B2 (en) 2004-04-14 2006-03-21 Taiwan Semiconductor Manufacturing Company Dual damascene structure formed of low-k dielectric materials
TWI267116B (en) * 2004-07-14 2006-11-21 Taiwan Semiconductor Mfg Method of preventing photoresist poisoning of a low-dielectric-constant insulator
US7605033B2 (en) * 2004-09-01 2009-10-20 Micron Technology, Inc. Low resistance peripheral local interconnect contacts with selective wet strip of titanium
US7253121B2 (en) * 2004-09-09 2007-08-07 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming IMD films
JP4492949B2 (ja) * 2004-11-01 2010-06-30 ルネサスエレクトロニクス株式会社 電子デバイスの製造方法
TWI254986B (en) * 2004-12-29 2006-05-11 United Microelectronics Corp Method for fabricating a dual damascene and polymer removal
WO2007004282A1 (ja) * 2005-07-04 2007-01-11 Fujitsu Limited 半導体装置及びその製造方法
JP5096669B2 (ja) * 2005-07-06 2012-12-12 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
KR100632467B1 (ko) * 2005-08-12 2006-10-09 삼성전자주식회사 반도체 메모리 소자 및 그 제조 방법
US7964470B2 (en) * 2006-03-01 2011-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Flexible processing method for metal-insulator-metal capacitor formation

Also Published As

Publication number Publication date
CN100559565C (zh) 2009-11-11
US10796953B2 (en) 2020-10-06
US20190088537A1 (en) 2019-03-21
US20120252205A1 (en) 2012-10-04
US8518821B2 (en) 2013-08-27
US9391022B2 (en) 2016-07-12
US9899316B2 (en) 2018-02-20
TWI389254B (zh) 2013-03-11
US20080286964A1 (en) 2008-11-20
KR101328862B1 (ko) 2013-11-13
TW200945495A (en) 2009-11-01
TWI385757B (zh) 2013-02-11
US20080211108A1 (en) 2008-09-04
US7354855B2 (en) 2008-04-08
US7932606B2 (en) 2011-04-26
JP2007019187A (ja) 2007-01-25
CN1893020A (zh) 2007-01-10
US20150228579A1 (en) 2015-08-13
US20080254616A1 (en) 2008-10-16
US8487412B2 (en) 2013-07-16
US20170271259A1 (en) 2017-09-21
US11062938B2 (en) 2021-07-13
US20210296165A1 (en) 2021-09-23
US7629251B2 (en) 2009-12-08
US8704373B2 (en) 2014-04-22
US20110183513A1 (en) 2011-07-28
KR20070005519A (ko) 2007-01-10
US20070020829A1 (en) 2007-01-25
US10600683B2 (en) 2020-03-24
CN101656229A (zh) 2010-02-24
KR20110082500A (ko) 2011-07-19
US11600522B2 (en) 2023-03-07
US10141257B2 (en) 2018-11-27
US20140199831A1 (en) 2014-07-17
TWI525747B (zh) 2016-03-11
US20200211897A1 (en) 2020-07-02
KR101344146B1 (ko) 2013-12-23
US20120248613A1 (en) 2012-10-04
US20160293542A1 (en) 2016-10-06
JP5096669B2 (ja) 2012-12-12
US7557034B2 (en) 2009-07-07
TW200705602A (en) 2007-02-01
US8581415B2 (en) 2013-11-12
US20140038409A1 (en) 2014-02-06
US20200411370A1 (en) 2020-12-31
US20230187275A1 (en) 2023-06-15
CN101656229B (zh) 2012-02-01

Similar Documents

Publication Publication Date Title
TWI525747B (zh) Semiconductor integrated circuit device and method for manufacturing semiconductor integrated circuit device
US7602040B2 (en) Semiconductor device and a method of manufacturing the same
JP4891296B2 (ja) 半導体集積回路装置の製造方法
JP2007116011A (ja) 半導体集積回路装置の製造方法