JP4006419B2 - ハイブリッド・プレーナおよびFinFETCMOSデバイス - Google Patents
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
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- 238000004544 sputter deposition Methods 0.000 description 1
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- 238000003631 wet chemical etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Description
埋込み絶縁層上に位置する少なくとも1つの頂部半導体層を備えるシリコン・オン・インシュレータ構造を提供するステップであって、前記頂部半導体層が、前記構造のFinFET領域内に位置する少なくとも1つのパターン化されたハードマスクと前記構造のFET領域内に位置する少なくとも1つのパターン化されたハードマスクを有している、ステップと、
FET領域を保護し、前記FinFET領域内の少なくとも1つのパターン化されたハードマスクをトリミングするステップと、
前記埋込み絶縁体層上の前記ハードマスク・ストッピングで保護されていない頂部半導体の露出している部分をエッチングするステップであって、前記エッチングがFinFET能動デバイス領域およびFET能動デバイス領域を形成し、前記FinFET能動デバイス領域がFET能動デバイス領域に垂直となっている、ステップと、
FinFET能動デバイス領域を保護し、及びFET能動デバイス領域を薄くすることで、FETデバイス領域がFinFET能動デバイス領域の高さより低くなるようにするステップと、
FinFET能動デバイス領域の各露出垂直面上にゲート誘電体を形成し、一方、FETデバイス領域の露出水平面上にゲート誘電体を形成するステップと、
ゲート誘電体の各露出面上にパターン化されたゲート電極を形成するステップと、
を含む。
12 底部半導体層
14 埋込み絶縁領域
16 頂部半導体層
18 酸化膜層
20 キャップ層
22,24 パターン化されたフォトレジスト画像
26,28 ハードマスク・パターン
30,36 レジスト・マスク
32 FinFET能動デバイス領域
34 FET能動デバイス領域
40 ゲート誘電体
42 ゲート導体材料
44,46 ゲート電極
48 FinFETスペーサ
50 FETスペーサ
Claims (14)
- 集積半導体回路を形成するための方法であって、
埋込み絶縁層上に位置する少なくとも1つの頂部半導体層を含むシリコン・オン・インシュレータ構造を提供するステップであって、前記頂部半導体層の上に、前記構造のFinFET領域内に位置する少なくとも1つのパターン化されたハードマスクと前記構造のFET領域内に位置する少なくとも1つのパターン化されたハードマスクとが構成されるようにする、ステップと、
前記提供するステップの後、前記FET領域を保護し、前記FinFET領域内の前記少なくとも1つのパターン化されたハードマスクをトリミングするステップと、
前記トリミングするステップの後、前記埋込み絶縁体層上の前記FinFET領域内の前記少なくとも1つのパターン化されたハードマスクおよび前記FET領域内の前記少なくとも1つのパターン化されたハードマスクのいずれにも保護されていない前記頂部半導体の露出部分をエッチングするステップであって、前記エッチングが、FinFET能動デバイス領域およびFET能動デバイス領域を形成し、前記FinFET能動デバイス領域が、前記FET能動デバイス領域が拡がる前記埋込み絶縁層の端面に対して垂直方向に沿って形成されるようにする、ステップと、
前記エッチングするステップの後、前記FinFET能動デバイス領域を保護し、保護した状態で、前記FET能動デバイス領域内のパターン化されたハードマスクを除去した後、前記FinFET能動デバイス領域に対する前記保護を除去し、その後、前記FinFET能動デバイス領域の前記パターン化されたハードマスクをマスクとして前記FET能動デバイス領域を薄くするステップであって、その結果前記FETデバイス領域が、前記FinFET能動デバイス領域の高さより低くなるようにするステップと、
前記薄くするステップの後、前記FinFET能動デバイス領域の各露出垂直面上にゲート誘電体を形成し、一方で、前記FETデバイス領域の露出水平面上にゲート誘電体を形成するステップと、
前記ゲート誘電体を形成するステップの後、前記ゲート誘電体の各露出面上に、パターン化されたゲート電極を形成するステップと、
を有する方法。 - 前記パターン化されたゲート電極と端接するスペーサを形成するステップをさらに有する、請求項1に記載の方法。
- 前記パターン化されたハードマスクが、
前記頂部半導体層の表面上に酸化膜層を形成するステップと、
前記酸化膜層上にキャップ層を形成するステップと、
前記キャップ層の露出表面にフォトレジストを塗布するステップと、
前記フォトレジストを照射パターンに露出するステップと、
前記パターンをフォトレジストに現像するステップと、
前記パターンを前記フォトレジストから前記キャップ層および前記酸化膜層に移送するステップと、
により形成される、請求項1に記載の方法。 - 前記FET領域を保護するステップが、前記FET領域にレジスト・マスクを適用するステップを含む、請求項1に記載の方法。
- 前記トリミング・ステップが、化学的酸化物除去プロセスまたは湿式エッチング・プロセスを含む、請求項1に記載の方法。
- 前記FinFET能動デバイス領域が、(110)の表面オリエンテーションを有し、前記FET能動デバイス領域が(100)の表面オリエンテーションを有する、請求項1に記載の方法。
- 前記FinFET能動デバイス領域を保護する前記ステップが、前記FinFET能動デバイス領域にレジスト・マスクを適用するステップを含む、請求項1に記載の方法。
- 前記FinFET能動デバイス領域が(100)の表面オリエンテーションを有し、前記FETデバイス領域が(110)の表面オリエンテーションを有する、請求項1に記載の方法。
- 前記酸化膜層はSiO2による層を含み、 前記厚さを薄くするステップが、SiO2に対して高度に選択的なエッチング・プロセスを含む、請求項3に記載の方法。
- 前記ゲート誘電体が、熱酸化プロセスにより形成された酸化物である、請求項1に記載の方法。
- 前記パターン化されたゲート電極が、
ゲート導体材料を堆積するステップと、
前記ゲート導体材料の頂部上にパターン化されたレジストを形成するするステップと、
前記パターン化されたレジストにより保護されていない前記ゲート導体の露出部分をエッチングするステップと、
により形成される、請求項1に記載の方法。 - 前記厚さを薄くするステップの代わりに、前記FinFET能動デバイス領域を保護し、保護した状態で、前記FET能動デバイス領域内のパターン化されたハードマスクを除去した後、前記FinFET能動デバイス領域に対する前記保護を除去せずにこれをマスクとして前記FET能動デバイス領域を薄くし、その後で前記保護を除去するステップを有する、請求項1に記載の方法。
- 前記頂部半導体層がSiからなる、請求項1に記載の方法。
- 前記埋込み絶縁層が酸化物からなる、請求項1に記載の方法。
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US10/604,097 US6911383B2 (en) | 2003-06-26 | 2003-06-26 | Hybrid planar and finFET CMOS devices |
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JP2005019996A JP2005019996A (ja) | 2005-01-20 |
JP4006419B2 true JP4006419B2 (ja) | 2007-11-14 |
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US (2) | US6911383B2 (ja) |
JP (1) | JP4006419B2 (ja) |
CN (1) | CN1292473C (ja) |
TW (1) | TWI283018B (ja) |
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US7049662B2 (en) * | 2003-11-26 | 2006-05-23 | International Business Machines Corporation | Structure and method to fabricate FinFET devices |
US7018551B2 (en) * | 2003-12-09 | 2006-03-28 | International Business Machines Corporation | Pull-back method of forming fins in FinFets |
US7180134B2 (en) * | 2004-01-30 | 2007-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and structures for planar and multiple-gate transistors formed on SOI |
JP4852694B2 (ja) * | 2004-03-02 | 2012-01-11 | 独立行政法人産業技術総合研究所 | 半導体集積回路およびその製造方法 |
US7087471B2 (en) * | 2004-03-15 | 2006-08-08 | International Business Machines Corporation | Locally thinned fins |
JP4565097B2 (ja) * | 2004-04-08 | 2010-10-20 | 独立行政法人産業技術総合研究所 | 二重ゲートmosトランジスタおよび二重ゲートcmosトランジスタ、その製造方法 |
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KR100618827B1 (ko) * | 2004-05-17 | 2006-09-08 | 삼성전자주식회사 | FinFET을 포함하는 반도체 소자 및 그 제조방법 |
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