TWI283018B - Hybrid planar and finFET CMOS devices - Google Patents
Hybrid planar and finFET CMOS devices Download PDFInfo
- Publication number
- TWI283018B TWI283018B TW093117787A TW93117787A TWI283018B TW I283018 B TWI283018 B TW I283018B TW 093117787 A TW093117787 A TW 093117787A TW 93117787 A TW93117787 A TW 93117787A TW I283018 B TWI283018 B TW I283018B
- Authority
- TW
- Taiwan
- Prior art keywords
- field effect
- effect transistor
- active device
- layer
- device region
- Prior art date
Links
- 238000000034 method Methods 0.000 claims abstract description 67
- 239000004065 semiconductor Substances 0.000 claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 14
- 230000005669 field effect Effects 0.000 claims description 198
- 229920002120 photoresistant polymer Polymers 0.000 claims description 48
- 239000013078 crystal Substances 0.000 claims description 19
- 239000004020 conductor Substances 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 12
- 229910052732 germanium Inorganic materials 0.000 claims description 9
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 4
- 229910000420 cerium oxide Inorganic materials 0.000 claims 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 claims 1
- 238000003384 imaging method Methods 0.000 abstract 2
- 239000012212 insulator Substances 0.000 abstract 2
- 238000009966 trimming Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 108
- 235000012431 wafers Nutrition 0.000 description 13
- 239000007943 implant Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 229910052736 halogen Inorganic materials 0.000 description 3
- 150000002367 halogens Chemical class 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000000224 chemical solution deposition Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000002309 gasification Methods 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 150000002923 oximes Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Description
1283018 玖、發明說明: 【發明所屬之技術領域】 本發明係關於積體半導體裝置,尤其係關於積體半導 體電路之發明。該積體半導體電路包括一平面單閘極互補式 金屬氧化物半導體(CMOS )裝置及製備於同一半導體基材 上之雙閘極裝置,如鰭狀場效電晶體(FinFET )。在一個 實例中,該平面單閘極CMOS裝置為形成於薄絕緣層上覆 矽層(SOI )上之n型場效電晶體,而該鰭狀場效電晶體係 為Ρ型鰭狀場效電晶體結構,其垂直通道表面方位為(丨丨〇 ) 方向。或者,該平面單閘極CMOS裝置為ρ型場效電晶體, 形成於薄SOI層之上,具有(1 1〇)表面方位,而該鰭狀場效 電晶體係η型鰭狀場效電晶體結構,其垂直通道具有表面 (100)方位。本發明還提供一種製備本發明積體半導體電 路的方法。 【先前技術】 在當今半導體技術中,互補式金屬氧化物半導體 (CMOS )裝置,如η型場效電晶體及ρ型場效電晶體等, 在單表面方位上,典型地製備在半導體晶圓上。尤其係,大 多數半導體裝置係被製備於一石夕基材之上,以具有(1〇〇) 表面方位。 人們已知’電子在(100)矽表面方位具有高的遷移率, 但電洞在(110)表面方位具有高的遷移率。也就是說,電 洞在(1 00 )矽上之遷移率值,比該結晶方向之對應電洞的 遷移率約低2Χ-4Χ。為了補償這種差異,典型地將ρ型場效 3 1283018 電晶體設計為具有較大甯 ,古._ u 相對η型場效電晶體下拉電 ^ ,平衡上拉電流,進 ^ ^ % 1電路交換;具有較大寬 度的η两效電晶體係不 ^ ^ 要的口為它占據明顯數量的晶片 面積。另一方面,在(nfn 夕上之電洞遷移率比在(100) 矽上高2x,因此,(11〇) μ θ丄 取两上形成之ρ型場效電晶體, 將八有明顯兩於(100)表面上 $成之Ρ型場效電晶體的驅 動電流。不幸的是,與(100) /表面相比,(1丨0 )矽表面 上之電子遷移率明顯降低。 傳統的Ρ型場效電晶體及η型場效電晶體都係平面單 閑極裳置,與雙問極裝置相比,它們典型地具有低次臨界電 壓特點及低驅動電流,用於非常短的通道長度。與傳統平面 裝置相比,雙閘極結構的次臨界電壓及驅動電、流得到改進。 一種特別重要的雙閘極裝置類型係籍狀場效電晶體。鰭狀場 效電晶體係一種雙間極裝置,包含有高而薄的垂直通道區。 由於垂直通道結構的緣故,具有(i00)表面方位之晶 圓’能夠用來製備具有(1 1 0 )通道表面方位之鰭狀場效電 晶體。在這種情況下,該ρ型鰭狀場效電晶體經由經驗得知 有關在(100)表面方位晶圓上製備傳統CMOS裝置的遷移 率提鬲。但是’與(100)表面通道方位上之傳統η型場效 電晶體相比,在(1 〇 〇 )表面方位上製備之η型鰭狀場效電 晶體遷移率降低。 儘管人們知道,在半導體晶圓上形成不同類型的平面 單閘極裝置或不同類型的雙閘極裝置,需要將平面及鰭狀場 效電晶體裝置積體在同一晶圓之上,使裝置形成之表面方 4 1283018 位,能夠提高每種裝置之性能。尤其是,人們需要提供一種 積體半導體電路,該電路包括至少一個η型場效電晶體作為 平面CMOS裝置和至少一個ρ型鰭狀場效電晶體作為其它裝 置。該p型鰭狀場效電晶體應該這樣製備,即其結構具有 (110)方向之表面通道。或者,需要提供一種電路,該電 路係由一 η型鰭狀場效電晶體和一具有(π 〇 )表面方位之 平面Ρ型場效電晶體裝置所組成。而該η型鰭狀場效電晶體 係製備於具有(11 0 )表面方位之晶圓上,以使該η型鰭狀 %效電晶體具有(1 0 0 )表面方位,並且平面ρ型場效電晶 體裝置具有(110)表面方位。 【發明内容】 本發明的一個目的係提供一種積體半導體電路。該電 路在同一半導體基材之上,包括至少一種鰭狀場效電晶體 裝置和至少一種平面單閘極場效電晶體裝置。 本發明的另一目的係提供一種積體半導體電路。該電 路包括至少一種鰭狀場效電晶體裝置和至少一種平面單閘 極场效電晶體裝置。它們製備於同一半導體基材,以每種 裝置的定位方位能夠提高裝置性能的方式製備。 本發明的又-目的係提供一種由一 ”場效電晶體和 一 Ρ型鰭狀場效電晶體所組成之積體半導體電路。其中該ρ 型鰭狀場效電晶體結構具有(110)表面方位,而該η型場 效電晶體則具有(100 )表面方位。 本發明的再-個目的係提供―種由_ ρ型場效電晶體 和一 η型鰭狀場效電晶體所組成之積體半導體電路。其中 1283018 該ρ場效電晶體結構具有(1 1 0 )表面方位。 本發明的再一目的係提供一種簡單衮異 ΓΊ平谷易的方法,以 製備混合平面及鰭狀場效電晶體 CMOS裝置。 本發明的這些目的及優點可這樣達到:即通過一種 法,在該方法中’利用光阻影像及圖案化硬質罩幕,調整 狀場效電晶體主動裝置區之寬度’隨後利用光阻影像及 刻,薄化該場效電晶體裝置區之厚度。該已調整的主動縛 場效電晶體裝置區即在其與該薄化場效電晶體裝置區垂 的方向被形成。而且,形成的該鰭狀場效電晶體|置區被 位為(11 0 )方位,而該薄化之場效電晶體裝置區則被定 為(100)方位。或者’該基材係(110)表面定位晶圓, 鰭狀場效電晶體具有(10 0)表面方位,而該平面單閘極 置則具有(π 0 )表面方位。 從廣義上來說,本發明之方法包含以下步驟: 提供一絕緣層上覆梦結構’包含至少一種位於埋入 絕緣層上之頂部半導體層,該頂部半導體層,具有至少一 位於結構之鰭狀場效電晶體區内之圖案化硬質罩幕,及至 一種位於結構之場效電晶體區内之圖案化硬質罩幕; 保護該場效電晶體區,並調整該鰭狀場效電晶體區 至少一種圖案化硬質罩幕; 蝕刻未用該硬質罩幕保護之頂部半導體層的暴露 分,該硬質罩幕係停留在該埋入式絕緣層之上’該蝕刻定 鰭狀場效電晶體主動裝置區及場效電晶體主動裝置區,該 狀場效電晶體主動裝置區與該場效電晶體主動裝置區垂:! 供 方 鰭 I虫 狀 直 定 位 該 裝 式 種 少 内 部 義 縛 6 1283018 保護該鰭狀場效電晶體主動裝置區及薄化該場效電晶 體主動裝置區,以使該場效電晶體裝置區之高度低於該轉狀 場效電晶體主動裝置區之高度; 在該鰭狀場效電晶體主動裝置區的每個暴露垂直表面 上’形成一閘極介電層,而在該場效電晶體裝置區的一暴露 水平表面上,形成一閘極介電層;及 在該閘極介電層的每個暴露表面上,形成一圖案化閘 電極。 本發明也係關於一種積體半導體電路。該積體半導體 電路包含至少一種P型鰭狀場效電晶體及至少一種η型場效 電晶體’位於一絕緣層上覆矽基材之埋入式絕緣層頂部。該 至少一種η型場效電晶體係位於絕緣層上覆矽基材之頂部 半導體層表面上,而該至少一種Ρ型鰭狀場效電晶體具有與 至少一種η型場效電晶體垂直之垂直通道。或者,該積體半 導體電路包含至少一種η型鰭狀場效電晶體及至少一種ρ型 場效電晶體,位於一絕緣層上覆矽基材之埋入式絕緣層頂 部。該至少一種ρ型場效電晶體係位於絕緣層上覆矽基材之 頂部半導體層表面上,而該至少一種η型鰭狀場效電晶體具 有與至少一種ρ型場效電晶體垂直之垂直通道。 廣義地說,本發明之積體半導體電路,係包含至少一 種鰭狀場效電晶體及至少一種平面單閘極場效電晶體,位於 一絕緣層上覆矽基材之埋入式絕緣層頂部。該至少一種平面 單閘極場效電晶體包含一主動裝置區,該主動裝置區包括一 絕緣層上覆矽基材之圖案化頂部半導體層及該至少一種鰭 7 1283018 狀%效電晶體具有與至少一種平面單閘極場 之垂直通道。 【實施方式】 本發明提供了混合平面;鰭狀場效電晶, 及一種形成該等裝置之方法。現在,將連同 起’參照所附圖詳細地進行說明。在所附圖中 應之裝置用相同的數字指代。必須指出,在 中,說明了單一 η型場效電晶體及單一 p型 體。儘管只說明了單一 η型場效電晶體及單一 電晶體,本發明在形成SOI基材上之各種類型 有效。此外,垂直裝置係n型鰭狀場效電晶體 係Ρ型場效電晶體,這樣的結構可被製備。 第1圖說明一可用於本發明之初始彳 (SOI)基材1〇。SOI基材10包括一埋入式 埋入式絕緣區1 4係位於底部半導體層1 2及 1 6之間。在本文中,該頂部半導體層1 6有時 SOI層。該SOI層係指該SOI基材之層,其中 型地製備在其上。 本文所用之“半導體”這個詞,用來說 體層12及該頂部半導體層16,表示任何半導 如 Si,Ge,SiGe,SiC,SiGeC,InAs,GaAs, III/V族化合物半導體。此處還考慮這些半導 一首選之實施例中,該SOI基材10的兩個半 底部半導體層1 2及該頂部半導體層1 6,係都 效電晶體垂直 It CMOS裝置 本發明應用一 ,相同或相對 以下說明及圖 鰭狀場效電晶 P型鰭狀場效 !裝置,均同等 ’與平面裝置 避緣層上覆石夕 絕緣區14,該 頂部半導體層 指SOI基材之 主動裝置係典 明該底部半導 體材料,包括 InP或其它如 體之多層。在 導體層,即該 由矽所組成。 1283018 曰、“里入式、、、邑緣層14可能係結晶或非結晶氧化物,或結 曰”戈非結晶氮化物。在本發明的一個首選之實施例中,該埋 入式絕緣g 14係—氧化物。該埋人式絕緣層14可以係連續 的’如圖所示,或者係非連續的。當為非連續埋入式絕緣區 時’該絕緣區為-被半導體材料包圍之孤島。Μ則基材 10可广係標100)定位晶圓,("ο)定位晶圓,或任 何其它表面方位。$ S()I基材之方向係以(i⑼)表面方位 為最佳。 該SΟI基材1 〇可以利用標準製程形成,包括如s〇χ (佈植氧加以分離)或鍵結形成。當利用鍵結形成時,在鍵 、、、"製程之後,可緊接一可選的薄化步驟。該可選薄化步驟可 降低該頂部半導體層之厚度,使成為一具有更符合需要厚度 之半導體層。 該SOI基材10之頂部半導體層16之厚度,係自1〇〇 至H)〇〇A左右,最適宜之厚度為500至700A左右。該SOI 基材10之埋入式絕緣層14之厚度,係自1〇至20〇〇 a左右, 最適宜之厚度為1000到1 500 A左右。該底部半導體層12 之厚度,對本發明來說是無關緊要的。 接下來’在該頂部半導體層16之暴露表面上部,形成 一氧化層18,即如第2圖所示之結構。明確地說,該氧化 層18,係由該SOI基材10之頂部半導體層16經過氧化製 程而形成。該氧化製程可使用一濕式或乾式熱氧化製程實 施。本發明此處應用之氧化製程,典型地在約1 000°c或更 高的溫度下實施。或者,該氧化層18通過沉積製程形成, 9 !283〇18 例如,通過化學氣相沉積法(CVD ),電漿輔助化學氣相沉 積法或化學溶液沉積法形成。得到的結構包括氧化層18, 如第2圖所示。
本發明於此處所形成之氧化層1 8,其厚度根據形成該 氡化層的條件而變化。但是,典型的氧化層1 8之厚度為200 至800A左右,最適宜之厚度為400至600 A左右。在本發 明中,該氧化層1 8既在隨後的矽蝕刻定義主動區期間,用 作硬質罩幕,又在閘疊層蝕刻及間隙壁蝕刻期間,用作保護 層保護該鰭狀場效電晶體。 在該SOI基材10上形成該氧化層18之後,由矽組成 之覆蓋層20,乃在該氧化層18之暴露表面上部沉積。經由 沉積該覆蓋層20後所形成的結構係如第3圖所示。該覆蓋 層20,通過沉積製程如濺鍍蝕刻製程形成,用於在該鰭狀 場效電晶體調整期間保護該氧化層1 8。典型的是,該覆蓋 層20比該氧化層丨8薄。明確地說,該覆蓋層2〇的厚度係 在10至500A左右,而厚度以50至100A左右為佳。 本發明於此處’利用微影技術,將該些p型鰭狀場效 電晶體主動裝置區及該n型場效電晶體主動裝置區光阻影 像圖案化,或者將該η型鰭狀場效電晶體及該p型場效電晶 體光阻影像圖案化。尤其,圖案化光阻影像22 (用以定義 該鰭狀場效電晶體主動裝置區)及圖案化光阻影像24 (用 以定義該場效電晶體主動裝置區),係形成於該覆蓋層20 之預定部分。該圖案化光阻影像22及24係這樣形成的:首 先在該覆蓋層20之整個表面應用光阻,然後暴露光阻至所 10 !283〇18 而的輻射圖案,接下來應用傳統光阻顯影機將圖案顯影至暴 路光阻。該結構包括如第4圖所示之圖案化光阻影像22及 24 〇 接著’不文該光阻影像22和24保護之覆蓋層20及氧 化層1 8,選擇性蝕刻該光阻影像,分別為該鰭狀場效電晶 體主動區及該場效電晶體主動區形成硬質罩幕圖案。本發明 此步驟所用之蝕刻,係一種定向反應性離子蝕刻製程或類似 於乾式蝕刻製程,能夠移除停留在該頂部半導體層丨6上部 表面之4覆蓋層20及該氧化層〗8。本發明實施此步驟之後 所形成的結構係如第5圖所示。緊接㈣刻步驟之後,採用 濕式溶劑剝離製程或標準灰化製程(此為熟悉該項技術之人 所熟知者),使移除該光阻影像22和24,以暴露硬質罩幕 圖案26及硬質罩幕圖案28。本發明中,硬質罩幕圖案% 係用於疋義該鰭狀場效電晶體主動區,而硬質罩幕圖案Μ 用於定義該平面單閘極場效電晶體主動區。然後,在此區内 形成一光阻罩I 30,並在其中形成該平面單閑極場效電晶 體’即如第6圖所示之結構。 如第6圖所示,該光阻罩幕30覆蓋該硬質罩幕28 以及該頂部半導趙層16與該硬f罩幕圖㈣相鄰的部分 第5圖所示結構應用光阻,形成罩幕3〇。然後利用微, 技術將該應用光阻圖案化。 η型)硬質罩幕 ’利用化學氧化 移除(COR)製 然後,對該鰭狀場效電晶體(p型或 圖案26,尤其是硬質罩幕圖案之氧化層 移除製私·,選擇性地進行調整。該化學氧化 1283018 程步驟包含:將此社燼 + 'σ構暴路於H F及氨的氣體·混合物中,壓 力為30mTorr (奎紅 代)左右或更低。最適宜的壓力為1亳托 至10愛托之間,彡田命 现度大約25 °C或稍高於室溫。氣體HF與 氣體氨之比為1:1〇5 ΊΛ1丄 至10:1左右,最適宜之比為2:1左右。 或者採用濕式餘刻製程,對該鰭狀場效電晶體硬質 罩幕圖案26進行胡軟 ^ 仃°周整,其中使用一種化學蝕刻劑,如氫氟 酸,選擇性地移除氧化物。 調t ν驟實知後形成的結構如第7圖所示。如圖所 丁 A硬質罩幕圖案26之氧化層18,比其上方的圖案化覆 蓋層20及硬質罩幕圖案28之氧化層薄。在調整步驟之後, 利用傳統剝離製程,移除封閉該場效電晶體裝置區之光阻 罩幕3 0。 本發明於此處,應用乾式蝕刻製程,如反應性離子蝕 刻’電漿ϋ刻’離子束㈣或f射蒸鍍等,㈣該鑛狀場效 電晶體或該場效電晶體主動區。尤其是,利用乾絲刻製程 移除未被調整的硬質罩幕圖案26或硬質罩幕圖案28保護之 該覆蓋層20及該頂部半導體層16。因此,本發明此處使用 的蝕刻步驟,自停留在埋入式絕緣層14上之結構,移除任 何未又保濩之矽(或半導體材料)。所得到的結構如第8圖 所示。 在第8圖中,參考數字32指的係該鰭狀場效電晶體主 動裝置區,而參考數字3 4指的係該平面單閘極場效電晶體 (P型或η型)主動裝置區。該鰭狀場效電晶體主動裝置區 之4刀,將用作該鑛狀場效電晶體(ρ型或11型)之通道區。 12 1283018 在一個實施例中’該p型鰭狀場效電晶體之通道區具有 (110)表面方位。或者,如果起始晶圓具有一(110)表面 方位,該鰭狀場效電晶體為具有(丨00)表面方位之n型鰭 狀場效電晶體’則平面單閘極裝置係為具有(n 0)表面方 位之P型場效電晶體。 採用標準微影技術製程,在該鰭狀場效電晶體區上將 另一光阻罩幕36圖案化。接著,利用蝕刻製程,選擇性地 移除該場效電晶體主動裝置區34上之圖案化硬質罩幕28的 氧化層18。自該場效電晶體主動裝置區34移除圖案化硬質 罩幕28之氧化層丨8所用之蝕刻製程,包括濕式化學蝕刻製 程或乾式蝕刻製程。形成光阻罩幕36,蝕刻該場效電晶體 主動凌置區3 4之圖案化氧化層丨8之後,所得到的結構如第 9圖所示。 由於光阻罩幕36已移除,可採用對si〇2具有高選擇 ί生的蝕刻製程,薄化該場效電晶體裝置區3 4。或者,在薄 化製:呈期間,可將該光阻罩幕留在原處。㈣化場效電晶體 主動凌置區34係如第10圖所示。在該場效電晶體裝置區 3 4薄化之後,利用傳統的光阻剝離製程,自此結構移除該 光,罩幕3 6。應該指出的是,本發明於此處,該鰭狀場效 電I體主動裝置區32的高度h係大於該場效電晶體主動裝 日品34的兩度h。本發明此時結構的另一特點是,該鰭狀 場效電晶體线裝置區與該場效電晶體主動裝置區垂直。因 為主動袭置區的構置,若該起始晶圓具有(1〇〇)表面方位, 則該鰭狀場效電晶體具有(110 )表面方位。若該起始晶圓 13 1283018 具有(11 〇 )表面方位,則該鰭狀場效電晶體具有(1 〇〇 )表 面方位。 實施一氧化製程,形成一犧牲氧化層(圖中未示出), 以自該鰭狀場效電晶體及該場效電晶體主動區移除任何受 損半導體層。本發明此處形成的犧牲氧化層之厚度·,根據氣 化製程本身的條件而變化。但是,該犧牲氧化層的典型厚度 為30至100A左右。本發明於此處,如有需要,一封閉罩幕 (未晝出),可在該場效電晶體區上圖案化,並實施離子佈 植製程’以植入該鰭狀場效電晶體通道區,設定裝置之臨界 電壓。可實施一類似的程序,設定場效電晶體裝置的臨界電 壓。然後’典型地實施傳統的退火製程,以激活摻雜物。 然後,採用濕式或乾式蝕刻製程,自結構移除該犧牲 氧化層 接者’在該縛狀場效電晶體主動裝置區32之暴露 垂直表面上及该場效電晶體主動裝置區34之暴露水平表面 上,形成閘極介電層40。該閘極介電層40可以包括一氧化 物’氮化物’氮氧化物或上述化合物之組合。該閘極介電層 40係以氧化物為佳,如si〇2,Al2〇3,舞鈦氧化物或其它氧 化物(但不僅限於此)。利用熱氧化,氮化,或氮氧化製程, 形成該閘極介電層40。該閘極介電層40的厚度為〇·5至 l〇nm左右,最適宜之厚度為〇.8至LOnm左右。 包括該閘極介電層40之結構係如第1 1圖所示。應注 意的是,該鰭狀場效電晶體主動裝置區32,有兩個閘極介 電層,形成於暴露的垂直表面之上,而該場效電晶體主動裝 置區34具有一單閘極介電層,形成於其中之暴露的水平表 14 1283018 面之上。 · 然後,在第11圖所示之整個結構上,形成一閘極導體 材料42,從而提供如第12圖所示之結構。利用傳統的沉積 製程,如化學氣相沉積法(CVD ),電漿輔助cVD,蒸鍍沉 積法,濺鍍沉積法,化學溶液沉積法或原子層沉積法等,形 成閘極導體材料42。該閘極導體材料42可由多晶矽;金屬 兀素如W (鎢);包含一種或多種金屬的合金;矽化物;或 上述物質的堆疊組合;例如,多晶矽/w (鎢)或矽化物組 成。 接著,利用一微影技術製程,在閘極導體材料上使光 阻影像圖案化。然後,利用一蝕刻製程,將閘極導體材料圖 案化,製成鰭狀場效電晶體及場效電晶體閘電極。第1 3圖 係與閘極垂直之剖面圖,在圖中,鰭狀場效電晶體之圖案化 閘電極標為44,而場效電晶體之圖案化閘電極標為46。 在某些實施例中,在閘疊層蝕刻之前,在閘電極區上 對硬質罩幕加以圖案化是有利的。利用微影技術罩幕,可封 閉鰭狀場效電晶體閘極之硬質罩幕。場效電晶體閘疊層可利 用微影技術罩幕,選擇性地加以蝕刻。重複此製程,蝕刻鰭 狀場效電晶體閘疊層(gate stack)。 本發明在此處,一光阻罩幕係圖案化於場效電晶體區 上(未畫出),而且一低能量離子佈植製程(等級(order ) 為2萬電子伏特或更低)係用來進行佈植,如有需要,鹵素 佈植(halo implant)及延伸佈植(extension implant)用於 鰭狀場效電晶體區。可選擇的鰭狀場效電晶體鹵素佈植之典 15 1283018 型佈植元素可為砷。若鰭狀場效電晶體類型為p型鰭狀場效 電晶體裝置,則鰭狀場效電晶體延伸之佈植的典型佈植元素 可為硼或BF2。光阻罩幕係利用溶劑剝離製程或氧氣灰化製 程來移除。另一光阻罩幕(未晝出)接著在鰭狀場效電晶體 區以及場效電晶體鹵素上被圖案化,如有需要,可使用硼或 銦來佈植場效電晶體延伸以作為可選擇的_素佈植,而當平 面單場效電晶體為η型場效電晶體時,則可使用砂作為場效 電晶體延伸。該光阻罩幕係利用傳統的光阻移除製程來移 除。 將介電材料如氧化物,氮化物,氧氮化物,或其化合 物沉積,並利用定向蝕刻製程形成源極/汲極間隙。在某些 實施例中,這是非常有利的首先沉積一薄的氧化物襯墊,厚 度約為35至ιοοΑ左右,接下來沉積SiN層,厚度約為1〇〇 至700 A左右。當形成鰭狀場效電晶體間隙48時,利用 光阻罩幕覆蓋场效電晶體,實施一獨立的間隙餘刻製程, 而田^/成場效電晶體間隙5 〇時,鰭狀場效電晶體由另一光 阻罩幕保護。結果得到的結構包括源極/汲極間隙以及間隙 50,如第14圖所示。 然後,利用傳統封閉罩幕及離子佈植法,形成鰭狀場 效電晶體及場效電晶體源極/汲極佈植(圖中未示出)。在 佈植之前’可在源極/汲極區形成一選擇性矽磊晶層,以降 低寄生電阻。然後,利用傳統的快速熱退火製程,以激活接 面。源極/汲極接面在經過激活之後,利用矽製程,產生低 電阻源極/沒極接觸區。可利用傳統的内連線製程經由線路 16 剖視圖),說明移除封閉罩 導體層之暴露表面,使形成 動裝置區後之結構。 1283018 末端後部繼續該製程。 雖然本發明已經特別說明,並用適當的實施例加 述,那些精通本領域的人們應該認識到,前述和形式上 它變化和細節’不會背離本發明的精神及範圍。因此 明不受本文所述及附圖說明的確切形式及細節的限制, 圍應為所附申請專利範圍之範圍。 【圖式簡單說明】 第1圖係一代表圖(剖視圖),說明本發明使用 始SOI基材。 第2圖係一代表圖(剖視圖),說明一種結構, 構包含一位於第1圖之SOI基材表面上之氧化層。 第3圖係一代表圖(剖視圖),說明-結構,該 包括一位於如第2圖中所示結構頂部之覆蓋層。 第4圖係-代表圖(剖視圖),說明一結構,該 在微影技術之後用於形成光阻影像,以定義主動裝置區 第5圖係—代表圖(剖視圖),說明-在覆蓋層 化層被#刻後之結構,該結構選擇用於光阻影像。 第6圖係一代表圖(剖視圖),說明一移除光„ 並形成-光阻影像封閉場效電晶體裝置區後之結構。 第7圖係一代矣園r w、 八表圖(剖視圖),說明該鰭狀場效 體硬質罩幕已經調整後之結構。 第8圖係一代表圖( 並餘刻該SOI基材之頂部半 場效電晶體及場效電晶體主 以表 的其 本發 其範 之開 該結 結構 結構 〇 及氧 Η象, 電晶 幕, 鰭狀 17 1283018 第9 ϊί係一代表圖(剖視圖),說明封閉該薦狀場效 電晶體主動 裝 置 區 及 自場 效電晶體裝置區移除該硬質罩幕 後之結構。 第10 圖 係 一 代 表圖 (剖視圖),說明該場效電晶體主 動裝置區已 經 薄 化 ,使其高度低於該鰭狀場效電晶體主動裝 置區之高度 後 之 結 構 〇 第11 圖 係 一 代 表圖 (剖視圖),說明在該鰭狀場效電 晶體主動裝 置 區 之 垂 直表 面及該場效電晶體主動裝置區之 水平表面上 5 形 成 一 閘極介電層後之結構。 第12 圖 係 一 代 表圖 (剖視圖),說明一包含沉積閘極 導體材料之 結 構 〇 第13 圖 係 一 代 表圖 (垂直閘極之剖視圖),說明一包 含圖案化閘 電 極 之 結 構。 第14 圖 係 一 代 表圖 (垂直閘極視圖之剖視圖),說明 本發明之最 後 結 構 〇 【主要元件 符 號 說 明 ] 10 絕緣 層 上 覆 矽 (SOI)基材 12 底部半導 體層 14 埋入 式 絕 緣 區 16 頂部半導體層 18 氧化 層 20 覆蓋層 22 圖案 化 光 阻 影 像(定義鰭狀場效電晶體主動裝置區) 24 圖案 化 光 阻 影 像( 定義場效電晶體主動裝置區) 26 硬質 罩 幕 圖 案 28 硬質罩幕圖案 30 光阻 罩 幕 32 鰭狀場效電 18 1283018 晶體主動裝置區 34 平面單閘極場效電晶體(p型或η型)主動裝置區 36 光阻罩幕 h! 鰭狀場效電晶體主動裝置區32的高度 h2 主動裝置區34的高度 40 閘極介電層 42 閘極導體材料
44 鰭狀場效電晶體之圖案化閘電極 46 場效電晶體之圖案化閘電極 48 鰭狀場效電 晶體間隙 50 場效電晶體間隙
19
Claims (1)
1283018 拾、申請專利範圍: 1 · 一種形成積體半導體電路之方法,包含以下步騍: 提供一絕緣層上覆矽結構,該結構包含位於一埋入式 絕緣層上方之至少一頂部半導體層,該頂部半導體層具有位 於該結構之一鰭狀場效電晶體區的至少一圖案化硬質罩 幕,及位於該結構之一場效電晶體區的至少一圖案化硬質罩 幕;
-' ,保護該場效電晶體區,並調整該鰭狀場效電晶體區内 之該至少一圖案化硬質罩幕; 鍅刻未受停留在該埋入式絕緣層上之硬質罩幕保護的 、頂半導體層之暴露部分,該钱刻定義一鑛狀場效電晶體 主動裝置區及一場效電晶體主動裝置區,該鰭狀場效電晶體 主動裝置區係垂直於該場效電晶體主動裝置區; 保護該鰭狀場效電晶體主動裝置區,並薄化該場效電 曰曰體主動裝置區’使得該場效電晶體主動裝置區的高度低於 〜轉狀場效電晶體主動裝置區的高度;
形成一閘極介電層於該鰭狀場效電晶體主動裝置區之 一暴露垂直表面上,同時形成一閘極介電層於該場效電晶 體主動裝置區之每一暴露水平表面上;及 在該閘極介電層之每一暴露表面上形成一圖案化閘電 极〇 Α如申請專利範圍第1項所述之方法,其係更包含形成與 4圖案化閘電極相鄰之間隙。 20 1283018 3. 如申請專利範圍第1項所述之方法,其中該圖案化硬質 罩幕通過以下步驟形成: 在該頂部半導體層表面上形成一氧化層; 在該氧化層上形成一覆蓋層; 在該覆蓋層之暴露表面使用一光阻; 以一圖案照射曝光該光阻; 將該圖案顯影至該光阻中;及 自該光阻轉移該圖案至該覆蓋層與該氧化層中。 4. 如申請專利範圍第1項所述之方法,其中該保護該場效 電晶體區係包含對該場效電晶體區應用一光阻罩幕。 5. 如申請專利範圍第1項所述之方法,其中該調整係包括 一化學氧化物移除製程或一濕式蝕刻製程。 6. 如申請專利範圍第1項所述之方法,其中該鰭狀場效電 晶體主動裝置區具有一(Π0)表面方位,而該場效電晶體 主動裝置區具有一(1〇〇)表面方位。 7. 如申請專利範圍第1項所述之方法,其中該保護該鰭狀 場效電晶體主動裝置區包含對該鰭狀場效電晶體主動裝置 區應用一光阻罩幕。 21 1283018 8·如申請專利範圍第1項所述之方法,其中該鰭狀場效電 晶體主動裝置區具有一(i 〇〇 )表面方位,而該場效電晶體 主動裝置區辱有一(110)表面方位。 9.如申請專利範圍第1項所述之方法,其中該薄化包括對 二氧化矽具有高度選擇性之一蝕刻製程。 10·如申請專利範圍第i項所述之方法,其中該閘極介電層 係由熱氧化製程所形成之一氧化物。 U.如申請專利範圍第1項所述之方法,其中該圖案化閘電 極的形成係經由: 沉積一閘極導體材料; 在該閘極導體材料之頂部形成一圖案化光阻;及 蝕刻該閘極導體材料不被圖案化光阻所保護之暴露部 分0 12· —種積體半導體電路,包含: 至少一鰭狀場效電晶體及至少一平面單閘極場效電 曰曰體,位於絕緣層上覆矽基材之一埋入式絕緣層的頂部, 該至少一平面單閘極場效電晶體包含一主動裝置區,該主動 裝置區包括該絕緣層上覆矽基材之一圖案化頂部半導體 層,及該至少一鰭狀場效電晶體具有一垂直通道,該通道係 垂直於該至少一平面單閘極場效電晶體。 22 1283018 1 3 •如申凊專利範圍第1 2項所述之積體半導體電路,其中 該頂部半導體層係由矽所組成。 1 4 ·如申請專利範圍第丨2項所述之積體半導體電路,其中 該埋入式絕緣層係由氧化物所組成。 15·如申請專利範圍第12項所述之積體半導體電路,其中 該垂直通道的高度係大於該至少一平面單閘極場效電晶體 之該圖案化頂部半導體層。 16·如申請專利範圍第12項所述之積體半導體電路,其中 該垂直通道具有一(11〇)表面方位,及該至少一平面單閘 極場效電晶體具有一(100)表面方位。 17·如申請專利範圍第12項所述之積體半導體電路,其中 該至少一鰭狀場效電晶體係為一雙閘極裝置。 18·如申請專利範圍第12項所述之積體半導體電路,其中 該垂直通道係具有一(1〇〇)表面方位,且該至少一平面單 閘極場效電晶體具有(11 〇 )表面方位。 23
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/604,097 US6911383B2 (en) | 2003-06-26 | 2003-06-26 | Hybrid planar and finFET CMOS devices |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200507079A TW200507079A (en) | 2005-02-16 |
TWI283018B true TWI283018B (en) | 2007-06-21 |
Family
ID=33539887
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW093117787A TWI283018B (en) | 2003-06-26 | 2004-06-18 | Hybrid planar and finFET CMOS devices |
Country Status (4)
Country | Link |
---|---|
US (2) | US6911383B2 (zh) |
JP (1) | JP4006419B2 (zh) |
CN (1) | CN1292473C (zh) |
TW (1) | TWI283018B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI506792B (zh) * | 2012-06-13 | 2015-11-01 | Synopsys Inc | 具有寬鬆之閘極間距的N通道及P通道端對端鰭式場效電晶體(FinFET)單元架構 |
Families Citing this family (219)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10220923B4 (de) * | 2002-05-10 | 2006-10-26 | Infineon Technologies Ag | Verfahren zur Herstellung eines nicht-flüchtigen Flash-Halbleiterspeichers |
CN100454499C (zh) * | 2003-06-04 | 2009-01-21 | 大见忠弘 | 半导体装置及其制造方法 |
US7456476B2 (en) | 2003-06-27 | 2008-11-25 | Intel Corporation | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
US7355253B2 (en) * | 2003-08-22 | 2008-04-08 | International Business Machines Corporation | Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates |
US7029958B2 (en) * | 2003-11-04 | 2006-04-18 | Advanced Micro Devices, Inc. | Self aligned damascene gate |
US7091566B2 (en) * | 2003-11-20 | 2006-08-15 | International Business Machines Corp. | Dual gate FinFet |
US7049662B2 (en) * | 2003-11-26 | 2006-05-23 | International Business Machines Corporation | Structure and method to fabricate FinFET devices |
US7018551B2 (en) * | 2003-12-09 | 2006-03-28 | International Business Machines Corporation | Pull-back method of forming fins in FinFets |
US7180134B2 (en) * | 2004-01-30 | 2007-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and structures for planar and multiple-gate transistors formed on SOI |
JP4852694B2 (ja) * | 2004-03-02 | 2012-01-11 | 独立行政法人産業技術総合研究所 | 半導体集積回路およびその製造方法 |
US7087471B2 (en) * | 2004-03-15 | 2006-08-08 | International Business Machines Corporation | Locally thinned fins |
JP4565097B2 (ja) * | 2004-04-08 | 2010-10-20 | 独立行政法人産業技術総合研究所 | 二重ゲートmosトランジスタおよび二重ゲートcmosトランジスタ、その製造方法 |
KR100618827B1 (ko) * | 2004-05-17 | 2006-09-08 | 삼성전자주식회사 | FinFET을 포함하는 반도체 소자 및 그 제조방법 |
DE102005022306B4 (de) * | 2004-05-17 | 2009-12-31 | Samsung Electronics Co., Ltd., Suwon | Verfahren zum Herstellen einer Halbleitervorrichtung mit einem Fin-Feldeffekttransistor (FinFET) |
US7291886B2 (en) * | 2004-06-21 | 2007-11-06 | International Business Machines Corporation | Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs |
US6960509B1 (en) * | 2004-06-30 | 2005-11-01 | Freescale Semiconductor, Inc. | Method of fabricating three dimensional gate structure using oxygen diffusion |
KR100612419B1 (ko) * | 2004-10-19 | 2006-08-16 | 삼성전자주식회사 | 핀 트랜지스터 및 평판 트랜지스터를 갖는 반도체 소자 및그 형성 방법 |
US20060086977A1 (en) | 2004-10-25 | 2006-04-27 | Uday Shah | Nonplanar device with thinned lower body portion and method of fabrication |
US20060177977A1 (en) * | 2005-02-08 | 2006-08-10 | The Hong Kong University Of Science And Technology | Method for patterning fins and gates in a FinFET device using trimmed hard-mask capped with imaging layer |
US7518196B2 (en) | 2005-02-23 | 2009-04-14 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
KR100610421B1 (ko) * | 2005-03-25 | 2006-08-08 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
US7521993B1 (en) * | 2005-05-13 | 2009-04-21 | Sun Microsystems, Inc. | Substrate stress signal amplifier |
JP4648096B2 (ja) * | 2005-06-03 | 2011-03-09 | 株式会社東芝 | 半導体装置の製造方法 |
US7858481B2 (en) | 2005-06-15 | 2010-12-28 | Intel Corporation | Method for fabricating transistor with thinned channel |
JP5128064B2 (ja) * | 2005-06-17 | 2013-01-23 | 国立大学法人東北大学 | 半導体装置 |
US7547637B2 (en) | 2005-06-21 | 2009-06-16 | Intel Corporation | Methods for patterning a semiconductor film |
US7279375B2 (en) | 2005-06-30 | 2007-10-09 | Intel Corporation | Block contact architectures for nanoscale channel transistors |
KR100725951B1 (ko) | 2005-08-23 | 2007-06-11 | 경북대학교 산학협력단 | 웰 구조를 갖는 cm os소자 |
US7352034B2 (en) * | 2005-08-25 | 2008-04-01 | International Business Machines Corporation | Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures |
US7737532B2 (en) * | 2005-09-06 | 2010-06-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid Schottky source-drain CMOS for high mobility and low barrier |
US7479421B2 (en) | 2005-09-28 | 2009-01-20 | Intel Corporation | Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby |
US20070090416A1 (en) | 2005-09-28 | 2007-04-26 | Doyle Brian S | CMOS devices with a single work function gate electrode and method of fabrication |
US7615806B2 (en) * | 2005-10-31 | 2009-11-10 | Freescale Semiconductor, Inc. | Method for forming a semiconductor structure and structure thereof |
US7575975B2 (en) * | 2005-10-31 | 2009-08-18 | Freescale Semiconductor, Inc. | Method for forming a planar and vertical semiconductor structure having a strained semiconductor layer |
US7547947B2 (en) * | 2005-11-15 | 2009-06-16 | International Business Machines Corporation | SRAM cell |
US7348633B2 (en) * | 2005-11-18 | 2008-03-25 | International Business Machines Corporation | Hybrid crystallographic surface orientation substrate having one or more SOI regions and/or bulk semiconductor regions |
KR100675290B1 (ko) * | 2005-11-24 | 2007-01-29 | 삼성전자주식회사 | 다중채널 전계효과트랜지스터 및 핀 전계효과트랜지스터를갖는 반도체소자의 제조방법 및 관련된 소자 |
CN101322240B (zh) | 2005-12-02 | 2011-12-14 | 国立大学法人东北大学 | 半导体装置 |
US7512017B2 (en) * | 2005-12-21 | 2009-03-31 | Intel Corporation | Integration of planar and tri-gate devices on the same substrate |
JP4490927B2 (ja) * | 2006-01-24 | 2010-06-30 | 株式会社東芝 | 半導体装置 |
JP4635897B2 (ja) * | 2006-02-15 | 2011-02-23 | 株式会社東芝 | 半導体装置及びその製造方法 |
US7473946B2 (en) * | 2006-02-22 | 2009-01-06 | International Business Machines Corporation | CMOS structure and method including multiple crystallographic planes |
US7419866B2 (en) * | 2006-03-15 | 2008-09-02 | Freescale Semiconductor, Inc. | Process of forming an electronic device including a semiconductor island over an insulating layer |
US7456055B2 (en) | 2006-03-15 | 2008-11-25 | Freescale Semiconductor, Inc. | Process for forming an electronic device including semiconductor fins |
JP2007258485A (ja) * | 2006-03-23 | 2007-10-04 | Toshiba Corp | 半導体装置及びその製造方法 |
US7288483B1 (en) * | 2006-03-28 | 2007-10-30 | Tokyo Electron Limited | Method and system for patterning a dielectric film |
KR100744137B1 (ko) | 2006-04-06 | 2007-08-01 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
US20090289304A1 (en) * | 2006-04-07 | 2009-11-26 | Koninklijke Philips Electronics Nv | Co-integration of multi-gate fet with other fet devices in cmos technology |
JP2007287728A (ja) * | 2006-04-12 | 2007-11-01 | Elpida Memory Inc | 半導体装置 |
US7407890B2 (en) * | 2006-04-21 | 2008-08-05 | International Business Machines Corporation | Patterning sub-lithographic features with variable widths |
JP5003013B2 (ja) * | 2006-04-25 | 2012-08-15 | 株式会社日立製作所 | シリコン発光ダイオード、シリコン光トランジスタ、シリコンレーザー及びそれらの製造方法。 |
US7436006B2 (en) * | 2006-05-19 | 2008-10-14 | International Business Machines Corporation | Hybrid strained orientated substrates and devices |
EP2237314A3 (en) * | 2006-07-13 | 2011-03-16 | National University Corporation Tohoku University | Semiconductor device |
EP2043159A4 (en) * | 2006-07-13 | 2011-05-18 | Univ Tohoku Nat Univ Corp | TRANSISTOR AND SEMICONDUCTOR DEVICE |
KR100801315B1 (ko) | 2006-09-29 | 2008-02-05 | 주식회사 하이닉스반도체 | 돌기형트랜지스터가 구비된 반도체소자의 제조 방법 |
US7592675B2 (en) * | 2006-10-02 | 2009-09-22 | Taiwan Semiconductor Manufacutring Company, Ltd. | Partial FinFET memory cell |
JP5137378B2 (ja) * | 2006-10-20 | 2013-02-06 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
JP2008124423A (ja) * | 2006-10-20 | 2008-05-29 | Oki Electric Ind Co Ltd | 半導体装置の製造方法及び半導体装置 |
US7649243B2 (en) * | 2006-11-06 | 2010-01-19 | International Business Machines Corporation | Semiconductor structures incorporating multiple crystallographic planes and methods for fabrication thereof |
US7544994B2 (en) * | 2006-11-06 | 2009-06-09 | International Business Machines Corporation | Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure |
US20080128797A1 (en) * | 2006-11-30 | 2008-06-05 | International Business Machines Corporation | Structure and method for multiple height finfet devices |
US7772656B2 (en) * | 2006-12-14 | 2010-08-10 | International Business Machines Corporation | Combination planar FET and FinFET device |
US20080157162A1 (en) * | 2006-12-27 | 2008-07-03 | Doyle Brian S | Method of combining floating body cell and logic transistors |
US8017463B2 (en) * | 2006-12-29 | 2011-09-13 | Intel Corporation | Expitaxial fabrication of fins for FinFET devices |
KR100875655B1 (ko) * | 2007-01-04 | 2008-12-26 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 |
US7781278B2 (en) * | 2007-01-18 | 2010-08-24 | International Business Machines Corporation | CMOS devices having channel regions with a V-shaped trench and hybrid channel orientations, and method for forming the same |
US7772048B2 (en) * | 2007-02-23 | 2010-08-10 | Freescale Semiconductor, Inc. | Forming semiconductor fins using a sacrificial fin |
US7923337B2 (en) | 2007-06-20 | 2011-04-12 | International Business Machines Corporation | Fin field effect transistor devices with self-aligned source and drain regions |
JP4459257B2 (ja) * | 2007-06-27 | 2010-04-28 | 株式会社東芝 | 半導体装置 |
US7732874B2 (en) * | 2007-08-30 | 2010-06-08 | International Business Machines Corporation | FinFET structure using differing gate dielectric materials and gate electrode materials |
US20090057846A1 (en) * | 2007-08-30 | 2009-03-05 | Doyle Brian S | Method to fabricate adjacent silicon fins of differing heights |
KR20090035775A (ko) * | 2007-10-08 | 2009-04-13 | 삼성전자주식회사 | 반도체 소자 및 이를 형성하는 방법 |
US7838913B2 (en) * | 2008-05-28 | 2010-11-23 | International Business Machines Corporation | Hybrid FET incorporating a finFET and a planar FET |
US8362566B2 (en) | 2008-06-23 | 2013-01-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US8241970B2 (en) | 2008-08-25 | 2012-08-14 | International Business Machines Corporation | CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins |
JP5003699B2 (ja) * | 2009-03-10 | 2012-08-15 | 株式会社日立製作所 | シリコン発光ダイオード、シリコン光トランジスタ、シリコンレーザー及びそれらの製造方法。 |
JP2010258124A (ja) | 2009-04-23 | 2010-11-11 | Renesas Electronics Corp | 半導体装置及び半導体装置の製造方法 |
US9337100B2 (en) * | 2009-06-03 | 2016-05-10 | Qualcomm Incorporated | Apparatus and method to fabricate an electronic device |
US9029132B2 (en) * | 2009-08-06 | 2015-05-12 | International Business Machines Corporation | Sensor for biomolecules |
JP5356970B2 (ja) * | 2009-10-01 | 2013-12-04 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体装置 |
US8125007B2 (en) * | 2009-11-20 | 2012-02-28 | International Business Machines Corporation | Integrated circuit including FinFET RF switch angled relative to planar MOSFET and related design structure |
US8455334B2 (en) * | 2009-12-04 | 2013-06-04 | International Business Machines Corporation | Planar and nanowire field effect transistors |
US9068935B2 (en) | 2010-04-08 | 2015-06-30 | International Business Machines Corporation | Dual FET sensor for sensing biomolecules and charged ions in an electrolyte |
CN102129982A (zh) * | 2010-12-29 | 2011-07-20 | 北京大学深圳研究生院 | 半导体精细图形及鳍形场效应管的fin体的制作方法 |
US8236634B1 (en) | 2011-03-17 | 2012-08-07 | International Business Machines Corporation | Integration of fin-based devices and ETSOI devices |
US8466502B2 (en) | 2011-03-24 | 2013-06-18 | United Microelectronics Corp. | Metal-gate CMOS device |
US8580664B2 (en) | 2011-03-31 | 2013-11-12 | Tokyo Electron Limited | Method for forming ultra-shallow boron doping regions by solid phase diffusion |
US8569158B2 (en) | 2011-03-31 | 2013-10-29 | Tokyo Electron Limited | Method for forming ultra-shallow doping regions by solid phase diffusion |
US8710596B2 (en) | 2011-05-13 | 2014-04-29 | United Microelectronics Corp. | Semiconductor device |
US8772860B2 (en) | 2011-05-26 | 2014-07-08 | United Microelectronics Corp. | FINFET transistor structure and method for making the same |
US8778744B2 (en) * | 2011-06-24 | 2014-07-15 | Institute of Microelectronics, Chinese Academy of Sciences | Method for manufacturing semiconductor field effect transistor |
US9184100B2 (en) | 2011-08-10 | 2015-11-10 | United Microelectronics Corp. | Semiconductor device having strained fin structure and method of making the same |
US9105660B2 (en) | 2011-08-17 | 2015-08-11 | United Microelectronics Corp. | Fin-FET and method of forming the same |
US8853013B2 (en) | 2011-08-19 | 2014-10-07 | United Microelectronics Corp. | Method for fabricating field effect transistor with fin structure |
US8674433B2 (en) | 2011-08-24 | 2014-03-18 | United Microelectronics Corp. | Semiconductor process |
US8759904B2 (en) * | 2011-08-24 | 2014-06-24 | GlobalFoundries, Inc. | Electronic device having plural FIN-FETs with different FIN heights and planar FETs on the same substrate |
US8691651B2 (en) | 2011-08-25 | 2014-04-08 | United Microelectronics Corp. | Method of forming non-planar FET |
US8477006B2 (en) | 2011-08-30 | 2013-07-02 | United Microelectronics Corp. | Resistor and manufacturing method thereof |
CN102969232B (zh) * | 2011-09-01 | 2015-01-14 | 中国科学院微电子研究所 | 后栅工艺中假栅的制造方法 |
US8441072B2 (en) | 2011-09-02 | 2013-05-14 | United Microelectronics Corp. | Non-planar semiconductor structure and fabrication method thereof |
CN102983073B (zh) * | 2011-09-05 | 2015-12-09 | 中国科学院微电子研究所 | 小尺寸鳍形结构的制造方法 |
US8507350B2 (en) | 2011-09-21 | 2013-08-13 | United Microelectronics Corporation | Fabricating method of semiconductor elements |
US8497198B2 (en) | 2011-09-23 | 2013-07-30 | United Microelectronics Corp. | Semiconductor process |
US8426277B2 (en) | 2011-09-23 | 2013-04-23 | United Microelectronics Corp. | Semiconductor process |
US8722501B2 (en) | 2011-10-18 | 2014-05-13 | United Microelectronics Corp. | Method for manufacturing multi-gate transistor device |
US8575708B2 (en) | 2011-10-26 | 2013-11-05 | United Microelectronics Corp. | Structure of field effect transistor with fin structure |
US8871575B2 (en) | 2011-10-31 | 2014-10-28 | United Microelectronics Corp. | Method of fabricating field effect transistor with fin structure |
US8278184B1 (en) | 2011-11-02 | 2012-10-02 | United Microelectronics Corp. | Fabrication method of a non-planar transistor |
US9006092B2 (en) | 2011-11-03 | 2015-04-14 | United Microelectronics Corp. | Semiconductor structure having fluoride metal layer and process thereof |
US8975672B2 (en) | 2011-11-09 | 2015-03-10 | United Microelectronics Corp. | Metal oxide semiconductor transistor and manufacturing method thereof |
US8426283B1 (en) | 2011-11-10 | 2013-04-23 | United Microelectronics Corp. | Method of fabricating a double-gate transistor and a tri-gate transistor on a common substrate |
US8440511B1 (en) | 2011-11-16 | 2013-05-14 | United Microelectronics Corp. | Method for manufacturing multi-gate transistor device |
US9406518B2 (en) * | 2011-11-18 | 2016-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | (110) surface orientation for reducing fermi-level-pinning between high-K dielectric and group III-V compound semiconductor substrate |
US8604548B2 (en) | 2011-11-23 | 2013-12-10 | United Microelectronics Corp. | Semiconductor device having ESD device |
US8921206B2 (en) | 2011-11-30 | 2014-12-30 | United Microelectronics Corp. | Semiconductor process |
US8803247B2 (en) | 2011-12-15 | 2014-08-12 | United Microelectronics Corporation | Fin-type field effect transistor |
US8709888B2 (en) | 2011-12-16 | 2014-04-29 | International Business Machines Corporation | Hybrid CMOS nanowire mesh device and PDSOI device |
US8563376B2 (en) | 2011-12-16 | 2013-10-22 | International Business Machines Corporation | Hybrid CMOS nanowire mesh device and bulk CMOS device |
US8722472B2 (en) | 2011-12-16 | 2014-05-13 | International Business Machines Corporation | Hybrid CMOS nanowire mesh device and FINFET device |
US8698199B2 (en) | 2012-01-11 | 2014-04-15 | United Microelectronics Corp. | FinFET structure |
US9698229B2 (en) | 2012-01-17 | 2017-07-04 | United Microelectronics Corp. | Semiconductor structure and process thereof |
US8946031B2 (en) | 2012-01-18 | 2015-02-03 | United Microelectronics Corp. | Method for fabricating MOS device |
US8587068B2 (en) * | 2012-01-26 | 2013-11-19 | International Business Machines Corporation | SRAM with hybrid FinFET and planar transistors |
US8987096B2 (en) | 2012-02-07 | 2015-03-24 | United Microelectronics Corp. | Semiconductor process |
US8664060B2 (en) | 2012-02-07 | 2014-03-04 | United Microelectronics Corp. | Semiconductor structure and method of fabricating the same |
US8536072B2 (en) | 2012-02-07 | 2013-09-17 | United Microelectronics Corp. | Semiconductor process |
US8822284B2 (en) | 2012-02-09 | 2014-09-02 | United Microelectronics Corp. | Method for fabricating FinFETs and semiconductor structure fabricated using the method |
US9159809B2 (en) | 2012-02-29 | 2015-10-13 | United Microelectronics Corp. | Multi-gate transistor device |
US9006107B2 (en) | 2012-03-11 | 2015-04-14 | United Microelectronics Corp. | Patterned structure of semiconductor device and fabricating method thereof |
US9159626B2 (en) | 2012-03-13 | 2015-10-13 | United Microelectronics Corp. | FinFET and fabricating method thereof |
US8946078B2 (en) | 2012-03-22 | 2015-02-03 | United Microelectronics Corp. | Method of forming trench in semiconductor substrate |
US8692291B2 (en) | 2012-03-27 | 2014-04-08 | International Business Machines Corporation | Passive devices for FinFET integrated circuit technologies |
US9559189B2 (en) | 2012-04-16 | 2017-01-31 | United Microelectronics Corp. | Non-planar FET |
US9142649B2 (en) | 2012-04-23 | 2015-09-22 | United Microelectronics Corp. | Semiconductor structure with metal gate and method of fabricating the same |
US8766319B2 (en) | 2012-04-26 | 2014-07-01 | United Microelectronics Corp. | Semiconductor device with ultra thin silicide layer |
US8709910B2 (en) | 2012-04-30 | 2014-04-29 | United Microelectronics Corp. | Semiconductor process |
US8691652B2 (en) | 2012-05-03 | 2014-04-08 | United Microelectronics Corp. | Semiconductor process |
US8877623B2 (en) | 2012-05-14 | 2014-11-04 | United Microelectronics Corp. | Method of forming semiconductor device |
US8470714B1 (en) | 2012-05-22 | 2013-06-25 | United Microelectronics Corp. | Method of forming fin structures in integrated circuits |
KR20130133559A (ko) * | 2012-05-29 | 2013-12-09 | 에스케이하이닉스 주식회사 | 반도체 소자의 형성방법 |
US9012975B2 (en) | 2012-06-14 | 2015-04-21 | United Microelectronics Corp. | Field effect transistor and manufacturing method thereof |
US8796695B2 (en) | 2012-06-22 | 2014-08-05 | United Microelectronics Corp. | Multi-gate field-effect transistor and process thereof |
US8501636B1 (en) | 2012-07-24 | 2013-08-06 | United Microelectronics Corp. | Method for fabricating silicon dioxide layer |
US8872280B2 (en) | 2012-07-31 | 2014-10-28 | United Microelectronics Corp. | Non-planar FET and manufacturing method thereof |
US9318567B2 (en) | 2012-09-05 | 2016-04-19 | United Microelectronics Corp. | Fabrication method for semiconductor devices |
US8815656B2 (en) | 2012-09-19 | 2014-08-26 | International Business Machines Corporation | Semiconductor device and method with greater epitaxial growth on 110 crystal plane |
US9064931B2 (en) | 2012-10-11 | 2015-06-23 | United Microelectronics Corp. | Semiconductor structure having contact plug and metal gate transistor and method of making the same |
US9159831B2 (en) | 2012-10-29 | 2015-10-13 | United Microelectronics Corp. | Multigate field effect transistor and process thereof |
US8927388B2 (en) | 2012-11-15 | 2015-01-06 | United Microelectronics Corp. | Method of fabricating dielectric layer and shallow trench isolation |
US8946063B2 (en) * | 2012-11-30 | 2015-02-03 | International Business Machines Corporation | Semiconductor device having SSOI substrate with relaxed tensile stress |
US8883621B2 (en) | 2012-12-27 | 2014-11-11 | United Microelectronics Corp. | Semiconductor structure and method of fabricating MOS device |
US9536792B2 (en) | 2013-01-10 | 2017-01-03 | United Microelectronics Corp. | Complementary metal oxide semiconductor field effect transistor, metal oxide semiconductor field effect transistor and manufacturing method thereof |
US9076870B2 (en) | 2013-02-21 | 2015-07-07 | United Microelectronics Corp. | Method for forming fin-shaped structure |
US9196352B2 (en) | 2013-02-25 | 2015-11-24 | United Microelectronics Corp. | Static random access memory unit cell structure and static random access memory unit cell layout structure |
US8841197B1 (en) | 2013-03-06 | 2014-09-23 | United Microelectronics Corp. | Method for forming fin-shaped structures |
TWI570812B (zh) * | 2013-03-06 | 2017-02-11 | 聯華電子股份有限公司 | 形成鰭狀結構的方法 |
US8753902B1 (en) | 2013-03-13 | 2014-06-17 | United Microelectronics Corp. | Method of controlling etching process for forming epitaxial structure |
US9214395B2 (en) | 2013-03-13 | 2015-12-15 | United Microelectronics Corp. | Method of manufacturing semiconductor devices |
US9093285B2 (en) | 2013-03-22 | 2015-07-28 | United Microelectronics Corp. | Semiconductor structure and process thereof |
US9196500B2 (en) | 2013-04-09 | 2015-11-24 | United Microelectronics Corp. | Method for manufacturing semiconductor structures |
US9711368B2 (en) | 2013-04-15 | 2017-07-18 | United Microelectronics Corp. | Sidewall image transfer process |
US8853015B1 (en) | 2013-04-16 | 2014-10-07 | United Microelectronics Corp. | Method of forming a FinFET structure |
US8709901B1 (en) | 2013-04-17 | 2014-04-29 | United Microelectronics Corp. | Method of forming an isolation structure |
US9147747B2 (en) | 2013-05-02 | 2015-09-29 | United Microelectronics Corp. | Semiconductor structure with hard mask disposed on the gate structure |
CN104143514B (zh) * | 2013-05-09 | 2017-09-26 | 中芯国际集成电路制造(上海)有限公司 | 多栅极场效应晶体管的形成方法 |
US9000483B2 (en) | 2013-05-16 | 2015-04-07 | United Microelectronics Corp. | Semiconductor device with fin structure and fabrication method thereof |
US9230812B2 (en) | 2013-05-22 | 2016-01-05 | United Microelectronics Corp. | Method for forming semiconductor structure having opening |
US8993433B2 (en) | 2013-05-27 | 2015-03-31 | United Microelectronics Corp. | Manufacturing method for forming a self aligned contact |
US9349812B2 (en) | 2013-05-27 | 2016-05-24 | United Microelectronics Corp. | Semiconductor device with self-aligned contact and method of manufacturing the same |
US9263287B2 (en) | 2013-05-27 | 2016-02-16 | United Microelectronics Corp. | Method of forming fin-shaped structure |
US8802521B1 (en) | 2013-06-04 | 2014-08-12 | United Microelectronics Corp. | Semiconductor fin-shaped structure and manufacturing process thereof |
US9006804B2 (en) | 2013-06-06 | 2015-04-14 | United Microelectronics Corp. | Semiconductor device and fabrication method thereof |
WO2014197891A2 (en) | 2013-06-07 | 2014-12-11 | Cornell University | Floating gate based sensor apparatus and related floating gate based sensor applications |
US9070710B2 (en) | 2013-06-07 | 2015-06-30 | United Microelectronics Corp. | Semiconductor process |
US8993384B2 (en) | 2013-06-09 | 2015-03-31 | United Microelectronics Corp. | Semiconductor device and fabrication method thereof |
US9263282B2 (en) | 2013-06-13 | 2016-02-16 | United Microelectronics Corporation | Method of fabricating semiconductor patterns |
TWI566273B (zh) * | 2013-06-13 | 2017-01-11 | 聯華電子股份有限公司 | 半導體圖案之製造方法 |
US9401429B2 (en) | 2013-06-13 | 2016-07-26 | United Microelectronics Corp. | Semiconductor structure and process thereof |
US9123810B2 (en) | 2013-06-18 | 2015-09-01 | United Microelectronics Corp. | Semiconductor integrated device including FinFET device and protecting structure |
US9048246B2 (en) | 2013-06-18 | 2015-06-02 | United Microelectronics Corp. | Die seal ring and method of forming the same |
US9064814B2 (en) | 2013-06-19 | 2015-06-23 | United Microelectronics Corp. | Semiconductor structure having metal gate and manufacturing method thereof |
US9190291B2 (en) | 2013-07-03 | 2015-11-17 | United Microelectronics Corp. | Fin-shaped structure forming process |
US9105685B2 (en) | 2013-07-12 | 2015-08-11 | United Microelectronics Corp. | Method of forming shallow trench isolation structure |
US9093565B2 (en) | 2013-07-15 | 2015-07-28 | United Microelectronics Corp. | Fin diode structure |
US9019672B2 (en) | 2013-07-17 | 2015-04-28 | United Microelectronics Corporation | Chip with electrostatic discharge protection function |
US8981487B2 (en) | 2013-07-31 | 2015-03-17 | United Microelectronics Corp. | Fin-shaped field-effect transistor (FinFET) |
US9006805B2 (en) | 2013-08-07 | 2015-04-14 | United Microelectronics Corp. | Semiconductor device |
KR102069609B1 (ko) | 2013-08-12 | 2020-01-23 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
US9105582B2 (en) | 2013-08-15 | 2015-08-11 | United Microelectronics Corporation | Spatial semiconductor structure and method of fabricating the same |
US9385048B2 (en) | 2013-09-05 | 2016-07-05 | United Microelectronics Corp. | Method of forming Fin-FET |
US9373719B2 (en) | 2013-09-16 | 2016-06-21 | United Microelectronics Corp. | Semiconductor device |
US9018066B2 (en) | 2013-09-30 | 2015-04-28 | United Microelectronics Corp. | Method of fabricating semiconductor device structure |
US9166024B2 (en) | 2013-09-30 | 2015-10-20 | United Microelectronics Corp. | FinFET structure with cavities and semiconductor compound portions extending laterally over sidewall spacers |
US9306032B2 (en) | 2013-10-25 | 2016-04-05 | United Microelectronics Corp. | Method of forming self-aligned metal gate structure in a replacement gate process using tapered interlayer dielectric |
US8980701B1 (en) | 2013-11-05 | 2015-03-17 | United Microelectronics Corp. | Method of forming semiconductor device |
US9299843B2 (en) | 2013-11-13 | 2016-03-29 | United Microelectronics Corp. | Semiconductor structure and manufacturing method thereof |
US8951884B1 (en) | 2013-11-14 | 2015-02-10 | United Microelectronics Corp. | Method for forming a FinFET structure |
US9059020B1 (en) | 2013-12-02 | 2015-06-16 | International Business Machins Corporation | Implementing buried FET below and beside FinFET on bulk substrate |
CN103943484B (zh) * | 2014-04-28 | 2016-08-17 | 上海华力微电子有限公司 | 自对准的栅极分离方法 |
US9281303B2 (en) | 2014-05-28 | 2016-03-08 | International Business Machines Corporation | Electrostatic discharge devices and methods of manufacture |
KR102347185B1 (ko) | 2015-02-03 | 2022-01-04 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
US9899224B2 (en) | 2015-03-03 | 2018-02-20 | Tokyo Electron Limited | Method of controlling solid phase diffusion of boron dopants to form ultra-shallow doping regions |
US20160268256A1 (en) * | 2015-03-13 | 2016-09-15 | Qualcomm Incorporated | Complementary metal-oxide semiconductor (cmos) transistor and tunnel field-effect transistor (tfet) on a single substrate |
US9419015B1 (en) * | 2015-03-13 | 2016-08-16 | Globalfoundries Inc. | Method for integrating thin-film transistors on an isolation region in an integrated circuit and resulting device |
CN104966672B (zh) * | 2015-06-30 | 2019-01-25 | 上海华力微电子有限公司 | 鳍式场效应管基体制备方法 |
US9666581B2 (en) * | 2015-08-21 | 2017-05-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET with source/drain structure and method of fabrication thereof |
US9978748B2 (en) * | 2015-12-09 | 2018-05-22 | International Business Machines Corporation | Method of cutting fins to create diffusion breaks for finFETs |
US10026653B2 (en) * | 2015-12-16 | 2018-07-17 | International Business Machines Corporation | Variable gate lengths for vertical transistors |
US11018254B2 (en) | 2016-03-31 | 2021-05-25 | International Business Machines Corporation | Fabrication of vertical fin transistor with multiple threshold voltages |
CN105655410B (zh) * | 2016-04-13 | 2019-07-30 | 京东方科技集团股份有限公司 | 非遮光型薄膜晶体管、阵列基板及显示装置 |
US9793271B1 (en) * | 2016-04-29 | 2017-10-17 | International Business Machines Corporation | Semiconductor device with different fin pitches |
US9916978B2 (en) | 2016-06-02 | 2018-03-13 | United Microelectronics Corporation | Method for fabricating a Fin field effect transistor (FinFET) |
US10049944B2 (en) | 2016-10-05 | 2018-08-14 | Globalfoundries Inc. | Method of manufacturing selective nanostructures into finFET process flow |
US10517179B2 (en) * | 2016-12-15 | 2019-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Material composition and methods thereof |
US9870952B1 (en) | 2017-02-07 | 2018-01-16 | International Business Machines Corporation | Formation of VFET and finFET |
US10090410B1 (en) | 2017-03-17 | 2018-10-02 | International Business Machines Corporation | Forming a combination of long channel devices and vertical transport fin field effect transistors on the same substrate |
US10679992B1 (en) | 2018-11-16 | 2020-06-09 | International Business Machines Corporation | Integrated device with vertical field-effect transistors and hybrid channels |
DE102021121138B3 (de) | 2021-08-13 | 2023-02-02 | Infineon Technologies Ag | Halbleitervorrichtungen und verfahren zum herstellen einer halbleitervorrichtung |
US11908743B2 (en) | 2021-09-27 | 2024-02-20 | International Business Machines Corporation | Planar devices with consistent base dielectric |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6292361A (ja) | 1985-10-17 | 1987-04-27 | Toshiba Corp | 相補型半導体装置 |
DE3851486T2 (de) | 1987-07-14 | 1995-02-23 | Agfa Gevaert Nv | Verfahren zum Herstellen von gekräuseltem photographischem Film. |
JPH07183488A (ja) | 1993-12-24 | 1995-07-21 | Nissan Motor Co Ltd | Mos制御形サイリスタおよびその製造方法 |
JP2924763B2 (ja) * | 1996-02-28 | 1999-07-26 | 日本電気株式会社 | 半導体装置の製造方法 |
US6245615B1 (en) | 1999-08-31 | 2001-06-12 | Micron Technology, Inc. | Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction |
JP4397491B2 (ja) | 1999-11-30 | 2010-01-13 | 財団法人国際科学振興財団 | 111面方位を表面に有するシリコンを用いた半導体装置およびその形成方法 |
US6252284B1 (en) * | 1999-12-09 | 2001-06-26 | International Business Machines Corporation | Planarized silicon fin device |
US6413802B1 (en) * | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
US7312485B2 (en) | 2000-11-29 | 2007-12-25 | Intel Corporation | CMOS fabrication process utilizing special transistor orientation |
US6300182B1 (en) * | 2000-12-11 | 2001-10-09 | Advanced Micro Devices, Inc. | Field effect transistor having dual gates with asymmetrical doping for reduced threshold voltage |
JP2002359293A (ja) | 2001-05-31 | 2002-12-13 | Toshiba Corp | 半導体装置 |
US6657259B2 (en) * | 2001-12-04 | 2003-12-02 | International Business Machines Corporation | Multiple-plane FinFET CMOS |
US7358121B2 (en) * | 2002-08-23 | 2008-04-15 | Intel Corporation | Tri-gate devices and methods of fabrication |
US7163851B2 (en) * | 2002-08-26 | 2007-01-16 | International Business Machines Corporation | Concurrent Fin-FET and thick-body device fabrication |
-
2003
- 2003-06-26 US US10/604,097 patent/US6911383B2/en not_active Expired - Fee Related
-
2004
- 2004-06-18 TW TW093117787A patent/TWI283018B/zh not_active IP Right Cessation
- 2004-06-22 JP JP2004183756A patent/JP4006419B2/ja not_active Expired - Fee Related
- 2004-06-25 CN CN200410060055.8A patent/CN1292473C/zh not_active Expired - Fee Related
-
2005
- 2005-05-04 US US11/122,193 patent/US7250658B2/en not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI506792B (zh) * | 2012-06-13 | 2015-11-01 | Synopsys Inc | 具有寬鬆之閘極間距的N通道及P通道端對端鰭式場效電晶體(FinFET)單元架構 |
US9257429B2 (en) | 2012-06-13 | 2016-02-09 | Synopsys, Inc. | N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch |
Also Published As
Publication number | Publication date |
---|---|
CN1591838A (zh) | 2005-03-09 |
US7250658B2 (en) | 2007-07-31 |
TW200507079A (en) | 2005-02-16 |
CN1292473C (zh) | 2006-12-27 |
US6911383B2 (en) | 2005-06-28 |
JP4006419B2 (ja) | 2007-11-14 |
JP2005019996A (ja) | 2005-01-20 |
US20040266076A1 (en) | 2004-12-30 |
US20050263831A1 (en) | 2005-12-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI283018B (en) | Hybrid planar and finFET CMOS devices | |
US8169024B2 (en) | Method of forming extremely thin semiconductor on insulator (ETSOI) device without ion implantation | |
US9245903B2 (en) | High voltage metal oxide semiconductor field effect transistor integrated into extremely thin semiconductor on insulator process | |
US8890255B2 (en) | Structure and method for stress latching in non-planar semiconductor devices | |
US8617956B2 (en) | Method and structure for forming high-K/metal gate extremely thin semiconductor on insulator device | |
TWI339406B (en) | Locally thinned fins | |
TWI485848B (zh) | 半導體裝置及其製造方法 | |
TW200425425A (en) | Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device | |
US20110127608A1 (en) | Extremely thin semiconductor on insulator semiconductor device with suppressed dopant segregation | |
US8227316B2 (en) | Method for manufacturing double gate finFET with asymmetric halo | |
JP2003017710A (ja) | 2重ゲート/2重チャネルmosfet | |
JP2003204068A (ja) | インプランテッド非対称ドープト・ポリシリコン・ゲートFinFET | |
US9472463B2 (en) | Patterning process for Fin implantation | |
US10121852B2 (en) | Structure and process to tuck fin tips self-aligned to gates | |
US20110115022A1 (en) | Implant free extremely thin semiconductor devices | |
US9472406B2 (en) | Metal semiconductor alloy contact resistance improvement | |
US10090165B2 (en) | Method to improve finFET cut overlay | |
US9478468B1 (en) | Dual metal contact scheme for CMOS devices | |
US7863143B2 (en) | High performance schottky-barrier-source asymmetric MOSFETs | |
JP5719381B2 (ja) | 低寄生容量ボディ・コンタクト・トランジスタ | |
US7105391B2 (en) | Planar pedestal multi gate device | |
JP2004207726A (ja) | 二重ゲート型電界効果トランジスタおよびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |