CN1292473C - 混合平面和FinFET CMOS器件 - Google Patents

混合平面和FinFET CMOS器件 Download PDF

Info

Publication number
CN1292473C
CN1292473C CN200410060055.8A CN200410060055A CN1292473C CN 1292473 C CN1292473 C CN 1292473C CN 200410060055 A CN200410060055 A CN 200410060055A CN 1292473 C CN1292473 C CN 1292473C
Authority
CN
China
Prior art keywords
fet
finfet
device region
active device
composition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN200410060055.8A
Other languages
English (en)
Other versions
CN1591838A (zh
Inventor
布鲁斯·B·多丽丝
黛安·C·博伊德
杨美基
托马斯·S·卡纳斯基
加库博·T·克泽尔斯基
杨敏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN1591838A publication Critical patent/CN1591838A/zh
Application granted granted Critical
Publication of CN1292473C publication Critical patent/CN1292473C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

本发明提供一种含有位于同一个SOI衬底上的平面单栅极FET和FinFET的集成半导体电路。具体地，该集成半导体电路包括位于绝缘体上硅衬底的埋置绝缘层顶上的FinFET和平面单栅极FET，平面单栅极FET位于绝缘体上硅衬底的构图的顶部半导体层的表面上，并且，FinFET具有垂直于该平面单栅极FET的垂直沟道。还提供形成这种集成电路的方法。在该方法中，在修整FinFET有源器件区的宽度中使用抗蚀剂成象和构图的硬掩模，并且随后在使FET器件区的厚度减薄中使用抗蚀剂成象和蚀刻。形成修整的有源FinFET器件区使其垂直于减薄的平面单栅极FET器件区。

Description

混合平面和FinFET CMOS器件
技术领域
本发明涉及集成半导体器件，更具体地，涉及在同一个半导体衬底上制造的包括平面单栅极互补金属氧化物半导体(CMOS)器件和双栅极器件，即FinFET的集成半导体电路。在一个例子中，平面单栅极CMOS器件是在绝缘体上硅(SOI)层上形成的nFET，而FinFET是具有表面取向在(110)方向上的垂直沟道的pFinFET结构。或者，平面单栅极CMOS器件为在具有(110)表面取向的薄SOI层上形成的pFET，而FinFET为具有(100)表面取向的垂直沟道的nFinFET。本发明还提供制造本发明的集成半导体电路的方法。
背景技术
在目前的半导体技术中，通常沿一个表面取向的方向在半导体晶片上制造互补金属氧化物半导体(CMOS)器件，例如，nFET和pFET。具体地，大多数半导体器件在Si衬底上制造，从而具有(100)表面取向。
已知电子对于(100)Si表面取向具有高迁移率，而空穴对于(110)表面取向具有高迁移率。即，在(100)Si上空穴迁移率的值比该晶体取向相应的电子空穴迁移率低大约2×-4×。为了补偿该差异，通常设计pFET具有更大的宽度，以便使上拉电流与nFET的下拉电流平衡，并且实现一致的电路切换；不希望nFET具有较大的宽度，因为它们会占用大量的芯片面积。另一方面，在(110)Si上的空穴迁移率比(100)Si上高2×；因此，在(110)表面上形成的pFET将比在(100)表面上形成的pFET表现出高得多的驱动电流。不幸的是，在(110)Si表面上的电子迁移率与在(100)Si表面相比显著降低。
常规pFET和nFET为平面单栅极器件，与双栅极器件相比，由于非常短的沟道长度，一般子域值电压特性和驱动电流较差。双栅极结构与常规平面器件相比，提供改善的子域值特性和驱动电流。特别重要的一种双栅极器件是FinFET。FinFET是包括高并且薄的垂直沟道区的双栅极器件。
由于垂直沟道结构，具有(100)表面取向的晶片可以用来制造具有(110)沟道表面取向的FinFET。在这种情况下，pFinFET相对于在具有(100)表面取向的晶片上制造的常规CMOS器件表现出提高的迁移率。但是，在(100)表面取向上制造的nFinFET与在(100)表面沟道取向上制造的常规nFET相比表现出迁移率退化。
虽然在半导体晶片上形成不同类型的平面单栅极器件或不同类型的双栅极器件是已知的，但是存在按照增强每个器件性能的表面取向形成器件的方式在同一个晶片上集成平面和FinFET器件的需求。具体地，需要提供包括至少一个作为平面CMOS器件的nFET和至少一个作为另一个器件的pFinFET的集成半导体电路。pFinFET应当以表面沟道沿(110)方向取向的结构制造。或者，需要提供由在晶片上制造的具有(110)表面取向的nFinFET(从而nFinFET具有(100)表面取向)和具有(110)表面取向的平面pFET器件构成的电路。
发明内容
本发明的一个目的是提供一种在同一个半导体衬底上包括至少一个FinFET器件和至少一个平面单栅极FET器件的集成半导体电路。
本发明的另一个目的是提供一种包括按照每个器件沿增强器件性能的方向取向的方式在同一个半导体衬底上制造的至少一个FinFET器件和至少一个平面单栅极FET器件的集成半导体电路。
本发明的再一个目的是提供一种包括nFET和pFinFET的集成半导体电路，其中pFinFET结构具有(110)表面取向，而nFET具有(100)表面取向。
本发明的又一个目的是提供一种包括pFET和nFinFET的集成半导体电路，其中pFET结构具有(110)表面取向。
本发明的另一个目的是提供一种提供混合平面和FinFET CMOS器件的简单而容易的方法。
通过在修整FinFET有源器件区的宽度中使用抗蚀剂成象和构图的硬掩模，并且随后在使FET器件区的厚度减薄中使用抗蚀剂成象和蚀刻，在本发明中实现这些和其它目的和优点。形成修整的有源FinFET器件区使其垂直于减薄的FET器件区。此外，形成FinFET器件区，从而其取向在(110)方向，而减薄的FET器件区的取向在(100)方向。或者，衬底是(110)表面取向的晶片，FinFET具有(100)表面取向，而平面单栅极器件具有(110)表面取向。
从广义上讲，本发明的方法包括以下步骤：
提供包括位于埋置绝缘层上的至少顶部半导体层的绝缘体上硅结构，所述顶部半导体层具有至少一个位于该结构的FinFET区中的构图的硬掩模和至少一个位于该结构的FET区中的构图的硬掩模；
保护FET区，并且修整在所述FinFET区中的所述至少一个构图的硬掩模；
蚀刻没有被所述硬掩模保护的顶部半导体的暴露部分，停止在所述埋置绝缘层上，所述蚀刻限定了FinFET有源器件区和FET有源器件区，所述FinFET有源器件区垂直于FET有源器件区；
保护FinFET有源器件区，并且使FET有源器件区减薄，从而FET器件区的高度小于FinFET有源器件区的高度；
在FinFET有源器件区的每个暴露的垂直表面上形成栅极介质，同时在FET器件区的暴露的水平表面上形成栅极介质；以及
在栅极介质的每个暴露表面上形成构图的栅极电极。
本发明还涉及包括位于绝缘体上硅衬底的埋置绝缘层顶上的至少一个pFinFET和至少一个nFET的集成半导体电路，所述至少一个nFET位于绝缘体上硅衬底的顶部半导体层的表面上，所述至少一个pFinFET具有垂直于所述至少一个nFET的垂直沟道。或者，集成半导体电路包括位于绝缘体上硅衬底的埋置绝缘层顶上的至少一个nFinFET和至少一个pFET，所述至少一个pFET位于绝缘体上硅衬底的顶部半导体层的表面上，所述至少一个nFinFET具有垂直于所述至少一个pFET的垂直沟道。
广义上讲，本发明的集成半导体电路包括位于绝缘体上硅衬底的埋置绝缘层顶上的至少一个FinFET和至少一个平面单栅极FET，所述至少一个平面单栅极FET包括有源区，该有源区包括绝缘体上硅衬底的构图的顶部半导体层，所述至少一个FinFET具有垂直于所述至少一个平面单栅极FET的垂直沟道。
附图说明
图1示出了在本发明中采用的初始SOI衬底的示意图(剖面图)。
图2示出了在图1的SOI衬底的上表面上含有氧化物层的结构的示意图(剖面图)。
图3示出了在图2所示的结构上面含有帽盖层的结构的示意图(剖面图)。
图4示出了在使用光刻形成用于限定有源器件区的抗蚀剂图形之后的结构的示意图(剖面图)。
图5示出了在相对于抗蚀剂图形选择性地蚀刻帽盖层和氧化物层之后的结构的示意图(剖面图)。
图6示出了在去掉抗蚀剂图形并且形成阻挡FET器件区的抗蚀剂图形之后的结构的示意图(剖面图)。
图7示出了在修整FinFET硬掩模之后结构的示意图(剖面图)。
图8示出了在去掉阻挡掩模并且蚀刻SOI衬底的顶部半导体层的暴露表面形成FinFET和FET有源器件区之后结构的示意图(剖面图)。
图9示出了在阻挡FinFET有源器件区并且从FET器件区去掉硬掩模之后结构的示意图(剖面图)。
图10示出了在使FET有源器件区减薄到高度小于FinFET有源器件区的高度之后结构的示意图(剖面图)。
图11示出了在FinFET有源器件区的垂直表面上和FET有源器件区的水平表面上形成栅极介质之后结构的示意图(剖面图)。
图12示出了含有淀积的栅极导体材料的结构的示意图(剖面图)。
图13示出了含有构图的栅极电极的结构的示意图(垂直于栅极的剖面图)。
图14示出了本发明的最终结构的的示意图(垂直于栅极视图的剖面图)。
具体实施方式
现在通过参考本申请的附图详细描述提供混合平面和FinFETCMOS器件及其形成方法的本发明。在附图中，相似的和相对应的元件用相似的数字表示。应当注意，在下面的介绍和附图中示出了单个nFET和单个pFinFET。虽然在附图中仅提供了单个nFET和单个pFinFET，但是本发明同样适用于在SOI衬底上对于每种形成多个器件。另外，所制造的结构中垂直器件为nFinFET，平面器件为pFET。
图1示出了可以用在本发明中的初始绝缘体上硅(SOI)衬底10。SOI衬底10包括在底部半导体层12和顶部半导体层16之间的埋置的绝缘区14。顶部半导体层16在本领域中有时称作SOI衬底的SOI层。SOI层是SOI衬底中通常形成有源器件的层。
这里所用来描述底部半导体层12和顶部半导体层16的术语“半导体”表示任何半导体材料，包括，例如，Si、Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP或者其它III/V化合物半导体。这里还希望包括这些半导体构成的多层。在优选实施例中，两个半导体层，即，SOI衬底10的底部半导体层12和顶部半导体层16都由Si构成。
埋置绝缘层14可以是晶体或非晶体氧化物或氮化物。在本发明的优选实施例中，埋置绝缘层14是氧化物。埋置绝缘层14可以是连续的，如图所示，或者是非连续的。当采用非连续的埋置绝缘区时，绝缘区作为被半导体材料环绕的分隔开的岛存在。SOI衬底10可以是标准(100)取向的晶片、(110)取向的晶片或者任何其它表面取向。SOI衬底的优选取向为(100)表面取向。
可以利用标准工艺形成SOI衬底10，包括，例如，SIMOX(由氧离子注入分开)或粘结。当采用粘结时，可以在粘结工艺之后进行可选的减薄步骤。可选的减薄步骤将顶部半导体层的厚度减小的更希望的厚度。
SOI衬底10的顶部半导体层16的厚度从大约100到大约1000，更优选厚度从大约500到大约700。SOI衬底10的埋置绝缘层14的厚度从大约10到大约2000，更优选厚度从大约1000到大约1500。底部半导体层12的厚度对本发明是不重要的。
接下来，在顶部半导体层16的上暴露表面上形成氧化物层18，提供例如在图2中所示的结构。具体地，通过使SOI衬底10的顶部半导体层16经过氧化工艺形成氧化物层18。可以使用湿或干热氧化工艺进行氧化工艺。通常在大约1000℃或更高的温度下进行本发明此时所使用的氧化工艺。或者，通过淀积工艺形成氧化物层18，包括例如化学气相淀积(CVD)、等离子体辅助CVD或者化学溶液淀积。例如在图2中示出了所得到的包括氧化物层18的结构。
本发明此时形成的氧化物层18的厚度可以根据其所采用的形成条件而变化。但是，通常氧化物层18的厚度从大约200到大约800，更优选厚度从大约400到大约600。在本发明中采用氧化物层18作为随后Si蚀刻期间的硬掩模，以限定有源区，并且在栅极堆叠蚀刻以及隔离物蚀刻期间作为保护FinFET的保护层。
在SOI衬底10上形成氧化物层18之后，在氧化物层18的暴露的上表面上淀积由硅构成的帽盖层20。例如在图3中示出了在淀积帽盖层20之后形成的结构。通过如溅射蚀刻工艺等淀积工艺形成的帽盖层20用来在FinFET修整工艺期间保护氧化物层18。帽盖层20通常比氧化物层18薄。具体地，帽盖层20的厚度从大约10到大约500，更优选厚度从大约50到大约100。
本发明此时使用光刻来构图pFinFET有源器件区和nFET有源器件区、或者nFinFET和pFET的抗蚀剂图形。具体地，在帽盖层20的预定部分上形成构图的抗蚀剂图形22(限定FinFET有源器件区)和构图的抗蚀剂图形24(限定FET有源器件区)。通过首先在整个帽盖层20的表面涂覆光致抗蚀剂，然后用所希望的辐射图形曝光光致抗蚀剂，并且随后利用常规抗蚀剂显影剂显影曝光的光致抗蚀剂的图形，形成构图的抗蚀剂图形22和24。例如在图4中示出了包括构图的抗蚀剂图形22和24的结构。
接着，相对于抗蚀剂图形选择性地蚀刻没有被抗蚀剂图形22和24保护的帽盖层20和氧化物层18，以分别形成FinFET有源区和FET有源区的硬掩模图形。在本发明的该步骤中使用的蚀刻为定向反应离子蚀刻工艺，或者能够去掉帽盖层20和氧化物层18、停止在顶部半导体层16的上表面上的类似的干蚀刻工艺。在例如图5中示出了在进行本发明的该步骤之后所得到的结构。在蚀刻步骤之后，使用本领域的技术人员公知的湿溶解剥离工艺或者标准灰化工艺去掉抗蚀剂图形22和24，从而暴露出硬掩模图形26和硬掩模图形28。在本发明中用硬掩模图形26限定FinFET的有源区，用硬掩模图形28限定平面单栅极FET的有源区。然后在要形成平面单栅极FET的区域中形成抗蚀剂掩模30，以提供图6所示的结构。
如图6所示，抗蚀剂掩模30覆盖硬掩模图形28以及与硬掩模图形28相邻的一部分顶部半导体层16。通过对图5所示的结构涂覆光致抗蚀剂，随后使用光刻工艺构图涂覆的光致抗蚀刻形成抗蚀剂掩模30。
然后，使用化学氧化物去除工艺选择性地修整FinFET(p或n)的硬掩模图形26，特别是硬掩模图形的氧化物层18。化学氧化去除(COR)工艺步骤包括在大约30毫托或更低的压力下和大约25℃或稍稍高于室温的温度下将结构暴露在HF和氨的气体混合物中，更优选的压力在大约1毫托到大约10毫托。气体HF与气体氨的比例从大约1∶10到大约10∶1，更优选的比例为大约2∶1。
或者，使用湿蚀刻工艺修整FinFET的硬掩模图形26，其中使用化学蚀刻剂，例如，氢氟酸，选择性地去掉氧化物。
例如在图7中示出了经过修整步骤之后所得到的结构。如图所示，硬掩模图形26的氧化物层18比上面的构图的帽盖层20以及硬掩模图形28的氧化物层要细小。在修整步骤之后，利用常规剥离工艺去掉阻挡FET器件区的抗蚀剂掩模30。
本发明此时采用如反应离子蚀刻、等离子体蚀刻、离子束蚀刻或激光消融等干蚀刻工艺蚀刻FinFET和FET的有源区。具体地，采用干蚀刻工艺去掉帽盖层20以及没有被修整的硬掩模图形26或硬掩模图形28保护的顶部半导体层16。由此，本发明此时采用的蚀刻步骤从结构中去掉任何没有被保护的硅(或半导体材料)，停止在埋置绝缘层14上。在图8中示出了所得到的结构。
在图8中，参考数字32表示FinFET的有源器件区，而参考数字34表示平面单栅极FET(p或n)的有源器件区。FinFET有源器件区的一部分用作FinFET(p或n)沟道区的。在一个实施例中，pFinFET的沟道区具有(110)表面取向。或者，如果初始晶片具有(110)表面取向，则FinFET为具有(100)表面取向的nFinFET，而平面单栅极器件为具有(110)表面取向的pFET。
使用标准的光刻工艺在FinFET区上构图另一个抗蚀剂掩模36。接着，使用蚀刻工艺选择性地去掉在FET有源器件区34上的构图的硬掩模28的氧化物层18。用来从FET有源器件区34上去掉构图的硬掩模28的氧化物层18的蚀刻工艺包括湿化学蚀刻工艺或干蚀刻工艺。例如在图9中示出了在形成抗蚀剂掩模36并且从FET器件区34蚀刻掉构图的氧化物层18之后得到的结构。
随着抗蚀剂掩模36被去掉，可以使用对SiO2具有高选择性的蚀刻工艺使FET器件区34减薄。或者，在减薄工艺期间，抗蚀剂掩模可以留在原地。在图10中示出了减薄的FET有源器件区34。在FET器件区34减薄之后，利用常规抗蚀剂剥离工艺从结构中去掉抗蚀剂掩模36。注意，本发明在此时FinFET有源器件区32的高度h1大于FET有源器件区34的高度h2。本发明在此时结构的另一个特征是FinFET有源器件区垂直于FET有源器件区。由于有源器件区的结构，如果初始晶片具有(100)表面取向，则FinFET具有(110)表面取向。如果初始晶片具有(110)表面取向，则FinFET具有(100)表面取向。
进行氧化工艺，形成牺牲氧化物层(未在图中示出)，以便从FinFET和FET的有源区中去掉任何损坏的半导体层。本发明此时形成的牺牲氧化物层的厚度可以根据氧化工艺本身的条件变化。但是，通常牺牲氧化物层的厚度从大约30到大约100。如果需要，在本发明的这个阶段，可以在FET区上构图阻档掩模(未示出)，并且进行离子注入工艺，以注入FinFET沟道区，从而设置器件的阈值电压。可以进行类似的过程设置FET器件的阈值电压。然后通常进行常规退火工艺，激活掺杂剂。
然后使用湿或干蚀刻工艺从结构中去掉牺牲氧化物层。接着，在FinFET有源器件区32的暴露的垂直表面上和FET有源器件区34的暴露的水平表面上形成栅极介质40。栅极介质40包括氧化物、氮化物、氮氧化物或者其任意组合。最好，栅极介质40为氧化物，例如但不限于：SiO2、Al2O2、钙钛矿氧化物或者其它类似的氧化物。利用热氧化、氮化或氮氧化工艺形成栅极介质40。栅极介质40的厚度从大约0.5nm到大约10nm，更优选从大约0.8nm到大约1.0nm。
例如在图11中示出了包括栅极介质40的结构。注意，FinFET有源器件区32具有在暴露的垂直表面上形成的两个栅极介质，而FET有源器件区34具有在其暴露的水平表面上形成的单个栅极介质。
然后，在图11所示的整个结构上形成栅极导体材料42，提供例如在图12中所示的结构。利用常规淀积工艺，例如，化学气相淀积(CVD)、等离子体辅助CVD、蒸发、溅射、化学溶液淀积或者原子层淀积，形成栅极导体材料42。栅极导体材料42包括多晶硅(poly-Si)；元素金属，如W；含有一种或多种元素金属的合金；硅化物；或者其叠层组合物，如，多晶硅/W或硅化物。
接着，使用光刻工艺在栅极导体材料上构图抗蚀剂图形。然后使用蚀刻工艺将栅极导体材料构图为FinFET和FET的栅极电极。在作为垂直于栅极的剖面图的图13中，FinFET的构图的栅极电极被标记为44，而FET的构图的栅极电极被标记为46。
在某些实施例中，在栅极叠层蚀刻之前在栅极电极区上构图硬掩模可能是有利的。可以使用光刻掩模阻挡用于FinFET栅极的硬掩模，并且相对于光刻掩模选择性地蚀刻FET栅极叠层。可以重复该工艺蚀刻FinFET的栅极叠层。
本发明在此时构图FET区上的抗蚀剂掩模(未在图中示出)，并且使用低能量离子注入工艺(20KeV数量级或更低)注入，如果需要的话，对FinFET区进行晕轮注入(halo implants)和扩展注入(extension implants)。可选的FinFET晕轮注入的典型注入物为砷。如果FinFET为p型器件，则FinFET扩展的典型注入物为硼或BF2。使用溶解剥离工艺或氧灰化工艺去掉抗蚀剂掩模。接着，如果需要的话，在FinFET区和FET晕轮上构图另一个抗蚀剂掩模(未示出)，并且对于可选的晕轮注入采用硼或铟，以及在平面单栅极FET为nFET的情况下对于FET扩展采用砷，注入FET扩展。使用常规抗蚀剂去除工艺去掉抗蚀剂掩模。
淀积例如氧化物、氮化物、氮氧化物或者其任意组合的介质材料，并且使用定向蚀刻工艺形成源极/漏极隔离物。在某些实施例中，首先淀积厚度从大约35到大约100的薄氧化物衬里，然后淀积厚度从大约100到大约700的SiN层可能是有利的。当形成FinFET隔离物48时，通过使用抗蚀剂掩模覆盖FET进行独立的隔离物蚀刻工艺，并且当形成FET隔离物50时，通过另一个抗蚀剂掩模保护FinFET。例如在图14中示出了包括源极/漏极隔离物48和50的结构。
然后使用常规阻挡掩膜和离子注入为FinFET和FET形成源极/漏极注入(未在图中示出)。在注入之前在源极/漏极区上生长选择性外延的Si层，以降低寄生电阻。然后使用常规快速热退火工艺激活结。在源极/漏极结激活之后，采用硅化工艺产生低阻的源极/漏极接触区。可以使用常规互连工艺以继续穿过线的后端的工艺。
尽管结合优选实施例具体示出并介绍了本发明，但是本领域的技术人员应当理解，可以不脱离本发明的精神和范围在形式和细节上作出上述和其它变化。因此本发明并不限于所介绍和示出的精确形式和细节，而是在权利要求书的范围内。

Claims (18)

1.一种形成集成半导体电路的方法，包括以下步骤：
提供包括位于埋置绝缘层上的至少一个顶部半导体层的绝缘体上硅结构，所述顶部半导体层具有位于该结构的FinFET区中的至少一个构图的硬掩模和位于该结构的FET区中的至少一个构图的硬掩模；
保护FET区，并且修整在所述FinFET区中的至少一个构图的硬掩模；
蚀刻没有被所述硬掩模保护的顶部半导体层的暴露部分，在所述埋置绝缘层上停止，所述蚀刻限定了FinFET有源器件区和FET有源器件区，所述FinFET有源器件区垂直于FET有源器件区；
保护FinFET有源器件区，并且使FET有源器件区减薄，从而FET器件区的高度小于FinFET有源器件区的高度；
在FinFET有源器件区的每个暴露的垂直表面上形成栅极介质，同时在FET器件区的暴露的水平表面上形成栅极介质；以及
在栅极介质的各暴露表面上形成构图的栅极电极。
2.根据权利要求1的方法，还包括形成与所述构图的栅极电极邻接的隔离物。
3.根据权利要求1的方法，其中通过以下步骤形成所述构图的硬掩模：
在所述顶部半导体层的表面上形成氧化物层；在氧化物层上形成帽盖层；在帽盖层的暴露的表面上涂覆光致抗蚀剂；用辐射图形曝光光致抗蚀剂；在光致抗蚀剂中显影图形；以及将所述图形从光致抗蚀剂转移到帽盖层和氧化物层中。
4.根据权利要求1的方法，其中所述保护FET区包括在所述FET区涂覆抗蚀剂掩模。
5.根据权利要求1的方法，其中所述修整包括化学氧化物去除工艺或湿蚀刻工艺。
6.根据权利要求1的方法，其中所述FinFET有源器件区具有(110)表面取向，所述FET具有源器件区具有(100)表面取向。
7.根据权利要求1的方法，其中所述保护FinFET有源器件区包括在FinFET有源器件区上涂覆抗蚀剂掩模。
8.根据权利要求1的方法，其中所述FinFET有源器件区具有(100)表面取向，所述FET有源器件区具有(110)表面取向。
9.根据权利要求1的方法，其中所述减薄包括对SiO2具有高选择性的蚀刻工艺。
10.根据权利要求1的方法，其中所述栅极介质为通过热氧化工艺形成的氧化物。
11.根据权利要求1的方法，其中通过淀积栅极导体材料形成所述构图的栅极电极；在栅极导体材料上面形成构图的抗蚀剂；以及蚀刻没有被构图的抗蚀剂保护的栅极导体的暴露部分。
12.一种集成半导体电路，包括：
位于绝缘体上硅衬底的埋置绝缘层顶上的至少一个FinFET和至少一个平面单栅极FET，所述至少一个平面单栅极FET包括有源器件区，该有源器件区包括绝缘体上硅衬底的构图的顶部半导体层，并且所述至少一个FinFET具有垂直于所述至少一个平面单栅极FET的垂直沟道。
13.根据权利要求12的集成半导体电路，其中所述顶部半导体层由Si构成。
14.根据权利要求12的集成半导体电路，其中所述埋置绝缘层由氧化物构成。
15.根据权利要求12的集成半导体电路，其中所述垂直沟道的高度大于所述至少一个平面单栅极FET的所述构图的顶部半导体层。
16.根据权利要求12的集成半导体电路，其中所述垂直沟道具有(110)表面取向，并且所述至少一个平面单栅极FET具有(100)表面取向。
17.根据权利要求12的集成半导体电路，其中所述至少一个FinFET是双栅极器件。
18.根据权利要求12的集成半导体电路，其中所述垂直沟道具有(100)表面取向，并且所述至少一个平面单栅极FET具有(110)表面取向。
CN200410060055.8A 2003-06-26 2004-06-25 混合平面和FinFET CMOS器件 Expired - Fee Related CN1292473C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/604,097 2003-06-26
US10/604,097 US6911383B2 (en) 2003-06-26 2003-06-26 Hybrid planar and finFET CMOS devices

Publications (2)

Publication Number Publication Date
CN1591838A CN1591838A (zh) 2005-03-09
CN1292473C true CN1292473C (zh) 2006-12-27

Family

ID=33539887

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200410060055.8A Expired - Fee Related CN1292473C (zh) 2003-06-26 2004-06-25 混合平面和FinFET CMOS器件

Country Status (4)

Country Link
US (2) US6911383B2 (zh)
JP (1) JP4006419B2 (zh)
CN (1) CN1292473C (zh)
TW (1) TWI283018B (zh)

Families Citing this family (220)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10220923B4 (de) * 2002-05-10 2006-10-26 Infineon Technologies Ag Verfahren zur Herstellung eines nicht-flüchtigen Flash-Halbleiterspeichers
CN100454499C (zh) * 2003-06-04 2009-01-21 大见忠弘 半导体装置及其制造方法
US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US7355253B2 (en) * 2003-08-22 2008-04-08 International Business Machines Corporation Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates
US7029958B2 (en) * 2003-11-04 2006-04-18 Advanced Micro Devices, Inc. Self aligned damascene gate
US7091566B2 (en) * 2003-11-20 2006-08-15 International Business Machines Corp. Dual gate FinFet
US7049662B2 (en) * 2003-11-26 2006-05-23 International Business Machines Corporation Structure and method to fabricate FinFET devices
US7018551B2 (en) * 2003-12-09 2006-03-28 International Business Machines Corporation Pull-back method of forming fins in FinFets
US7180134B2 (en) * 2004-01-30 2007-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and structures for planar and multiple-gate transistors formed on SOI
JP4852694B2 (ja) * 2004-03-02 2012-01-11 独立行政法人産業技術総合研究所 半導体集積回路およびその製造方法
US7087471B2 (en) * 2004-03-15 2006-08-08 International Business Machines Corporation Locally thinned fins
JP4565097B2 (ja) * 2004-04-08 2010-10-20 独立行政法人産業技術総合研究所 二重ゲートｍｏｓトランジスタおよび二重ゲートｃｍｏｓトランジスタ、その製造方法
KR100618827B1 (ko) * 2004-05-17 2006-09-08 삼성전자주식회사 ＦｉｎＦＥＴ을 포함하는 반도체 소자 및 그 제조방법
DE102005022306B4 (de) * 2004-05-17 2009-12-31 Samsung Electronics Co., Ltd., Suwon Verfahren zum Herstellen einer Halbleitervorrichtung mit einem Fin-Feldeffekttransistor (FinFET)
US7291886B2 (en) * 2004-06-21 2007-11-06 International Business Machines Corporation Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs
US6960509B1 (en) * 2004-06-30 2005-11-01 Freescale Semiconductor, Inc. Method of fabricating three dimensional gate structure using oxygen diffusion
KR100612419B1 (ko) * 2004-10-19 2006-08-16 삼성전자주식회사 핀 트랜지스터 및 평판 트랜지스터를 갖는 반도체 소자 및그 형성 방법
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US20060177977A1 (en) * 2005-02-08 2006-08-10 The Hong Kong University Of Science And Technology Method for patterning fins and gates in a FinFET device using trimmed hard-mask capped with imaging layer
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
KR100610421B1 (ko) * 2005-03-25 2006-08-08 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US7521993B1 (en) * 2005-05-13 2009-04-21 Sun Microsystems, Inc. Substrate stress signal amplifier
JP4648096B2 (ja) * 2005-06-03 2011-03-09 株式会社東芝 半導体装置の製造方法
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
JP5128064B2 (ja) * 2005-06-17 2013-01-23 国立大学法人東北大学 半導体装置
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7279375B2 (en) 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
KR100725951B1 (ko) 2005-08-23 2007-06-11 경북대학교 산학협력단 웰 구조를 갖는 ｃｍ ｏｓ소자
US7352034B2 (en) * 2005-08-25 2008-04-01 International Business Machines Corporation Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures
US7737532B2 (en) * 2005-09-06 2010-06-15 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid Schottky source-drain CMOS for high mobility and low barrier
US7479421B2 (en) 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US20070090416A1 (en) 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US7615806B2 (en) * 2005-10-31 2009-11-10 Freescale Semiconductor, Inc. Method for forming a semiconductor structure and structure thereof
US7575975B2 (en) * 2005-10-31 2009-08-18 Freescale Semiconductor, Inc. Method for forming a planar and vertical semiconductor structure having a strained semiconductor layer
US7547947B2 (en) * 2005-11-15 2009-06-16 International Business Machines Corporation SRAM cell
US7348633B2 (en) * 2005-11-18 2008-03-25 International Business Machines Corporation Hybrid crystallographic surface orientation substrate having one or more SOI regions and/or bulk semiconductor regions
KR100675290B1 (ko) * 2005-11-24 2007-01-29 삼성전자주식회사 다중채널 전계효과트랜지스터 및 핀 전계효과트랜지스터를갖는 반도체소자의 제조방법 및 관련된 소자
CN101322240B (zh) 2005-12-02 2011-12-14 国立大学法人东北大学 半导体装置
US7512017B2 (en) * 2005-12-21 2009-03-31 Intel Corporation Integration of planar and tri-gate devices on the same substrate
JP4490927B2 (ja) * 2006-01-24 2010-06-30 株式会社東芝 半導体装置
JP4635897B2 (ja) * 2006-02-15 2011-02-23 株式会社東芝 半導体装置及びその製造方法
US7473946B2 (en) * 2006-02-22 2009-01-06 International Business Machines Corporation CMOS structure and method including multiple crystallographic planes
US7419866B2 (en) * 2006-03-15 2008-09-02 Freescale Semiconductor, Inc. Process of forming an electronic device including a semiconductor island over an insulating layer
US7456055B2 (en) 2006-03-15 2008-11-25 Freescale Semiconductor, Inc. Process for forming an electronic device including semiconductor fins
JP2007258485A (ja) * 2006-03-23 2007-10-04 Toshiba Corp 半導体装置及びその製造方法
US7288483B1 (en) * 2006-03-28 2007-10-30 Tokyo Electron Limited Method and system for patterning a dielectric film
KR100744137B1 (ko) 2006-04-06 2007-08-01 삼성전자주식회사 반도체 소자 및 그 제조 방법
US20090289304A1 (en) * 2006-04-07 2009-11-26 Koninklijke Philips Electronics Nv Co-integration of multi-gate fet with other fet devices in cmos technology
JP2007287728A (ja) * 2006-04-12 2007-11-01 Elpida Memory Inc 半導体装置
US7407890B2 (en) * 2006-04-21 2008-08-05 International Business Machines Corporation Patterning sub-lithographic features with variable widths
JP5003013B2 (ja) * 2006-04-25 2012-08-15 株式会社日立製作所 シリコン発光ダイオード、シリコン光トランジスタ、シリコンレーザー及びそれらの製造方法。
US7436006B2 (en) * 2006-05-19 2008-10-14 International Business Machines Corporation Hybrid strained orientated substrates and devices
EP2237314A3 (en) * 2006-07-13 2011-03-16 National University Corporation Tohoku University Semiconductor device
EP2043159A4 (en) * 2006-07-13 2011-05-18 Univ Tohoku Nat Univ Corp TRANSISTOR AND SEMICONDUCTOR DEVICE
KR100801315B1 (ko) 2006-09-29 2008-02-05 주식회사 하이닉스반도체 돌기형트랜지스터가 구비된 반도체소자의 제조 방법
US7592675B2 (en) * 2006-10-02 2009-09-22 Taiwan Semiconductor Manufacutring Company, Ltd. Partial FinFET memory cell
JP5137378B2 (ja) * 2006-10-20 2013-02-06 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
JP2008124423A (ja) * 2006-10-20 2008-05-29 Oki Electric Ind Co Ltd 半導体装置の製造方法及び半導体装置
US7649243B2 (en) * 2006-11-06 2010-01-19 International Business Machines Corporation Semiconductor structures incorporating multiple crystallographic planes and methods for fabrication thereof
US7544994B2 (en) * 2006-11-06 2009-06-09 International Business Machines Corporation Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure
US20080128797A1 (en) * 2006-11-30 2008-06-05 International Business Machines Corporation Structure and method for multiple height finfet devices
US7772656B2 (en) * 2006-12-14 2010-08-10 International Business Machines Corporation Combination planar FET and FinFET device
US20080157162A1 (en) * 2006-12-27 2008-07-03 Doyle Brian S Method of combining floating body cell and logic transistors
US8017463B2 (en) * 2006-12-29 2011-09-13 Intel Corporation Expitaxial fabrication of fins for FinFET devices
KR100875655B1 (ko) * 2007-01-04 2008-12-26 주식회사 하이닉스반도체 반도체 소자의 제조방법
US7781278B2 (en) * 2007-01-18 2010-08-24 International Business Machines Corporation CMOS devices having channel regions with a V-shaped trench and hybrid channel orientations, and method for forming the same
US7772048B2 (en) * 2007-02-23 2010-08-10 Freescale Semiconductor, Inc. Forming semiconductor fins using a sacrificial fin
US7923337B2 (en) 2007-06-20 2011-04-12 International Business Machines Corporation Fin field effect transistor devices with self-aligned source and drain regions
JP4459257B2 (ja) * 2007-06-27 2010-04-28 株式会社東芝 半導体装置
US7732874B2 (en) * 2007-08-30 2010-06-08 International Business Machines Corporation FinFET structure using differing gate dielectric materials and gate electrode materials
US20090057846A1 (en) * 2007-08-30 2009-03-05 Doyle Brian S Method to fabricate adjacent silicon fins of differing heights
KR20090035775A (ko) * 2007-10-08 2009-04-13 삼성전자주식회사 반도체 소자 및 이를 형성하는 방법
US7838913B2 (en) * 2008-05-28 2010-11-23 International Business Machines Corporation Hybrid FET incorporating a finFET and a planar FET
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US8241970B2 (en) 2008-08-25 2012-08-14 International Business Machines Corporation CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins
JP5003699B2 (ja) * 2009-03-10 2012-08-15 株式会社日立製作所 シリコン発光ダイオード、シリコン光トランジスタ、シリコンレーザー及びそれらの製造方法。
JP2010258124A (ja) 2009-04-23 2010-11-11 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
US9337100B2 (en) * 2009-06-03 2016-05-10 Qualcomm Incorporated Apparatus and method to fabricate an electronic device
US9029132B2 (en) * 2009-08-06 2015-05-12 International Business Machines Corporation Sensor for biomolecules
JP5356970B2 (ja) * 2009-10-01 2013-12-04 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置
US8125007B2 (en) * 2009-11-20 2012-02-28 International Business Machines Corporation Integrated circuit including FinFET RF switch angled relative to planar MOSFET and related design structure
US8455334B2 (en) * 2009-12-04 2013-06-04 International Business Machines Corporation Planar and nanowire field effect transistors
US9068935B2 (en) 2010-04-08 2015-06-30 International Business Machines Corporation Dual FET sensor for sensing biomolecules and charged ions in an electrolyte
CN102129982A (zh) * 2010-12-29 2011-07-20 北京大学深圳研究生院 半导体精细图形及鳍形场效应管的fin体的制作方法
US8236634B1 (en) 2011-03-17 2012-08-07 International Business Machines Corporation Integration of fin-based devices and ETSOI devices
US8466502B2 (en) 2011-03-24 2013-06-18 United Microelectronics Corp. Metal-gate CMOS device
US8580664B2 (en) 2011-03-31 2013-11-12 Tokyo Electron Limited Method for forming ultra-shallow boron doping regions by solid phase diffusion
US8569158B2 (en) 2011-03-31 2013-10-29 Tokyo Electron Limited Method for forming ultra-shallow doping regions by solid phase diffusion
US8710596B2 (en) 2011-05-13 2014-04-29 United Microelectronics Corp. Semiconductor device
US8772860B2 (en) 2011-05-26 2014-07-08 United Microelectronics Corp. FINFET transistor structure and method for making the same
US8778744B2 (en) * 2011-06-24 2014-07-15 Institute of Microelectronics, Chinese Academy of Sciences Method for manufacturing semiconductor field effect transistor
US9184100B2 (en) 2011-08-10 2015-11-10 United Microelectronics Corp. Semiconductor device having strained fin structure and method of making the same
US9105660B2 (en) 2011-08-17 2015-08-11 United Microelectronics Corp. Fin-FET and method of forming the same
US8853013B2 (en) 2011-08-19 2014-10-07 United Microelectronics Corp. Method for fabricating field effect transistor with fin structure
US8674433B2 (en) 2011-08-24 2014-03-18 United Microelectronics Corp. Semiconductor process
US8759904B2 (en) * 2011-08-24 2014-06-24 GlobalFoundries, Inc. Electronic device having plural FIN-FETs with different FIN heights and planar FETs on the same substrate
US8691651B2 (en) 2011-08-25 2014-04-08 United Microelectronics Corp. Method of forming non-planar FET
US8477006B2 (en) 2011-08-30 2013-07-02 United Microelectronics Corp. Resistor and manufacturing method thereof
CN102969232B (zh) * 2011-09-01 2015-01-14 中国科学院微电子研究所 后栅工艺中假栅的制造方法
US8441072B2 (en) 2011-09-02 2013-05-14 United Microelectronics Corp. Non-planar semiconductor structure and fabrication method thereof
CN102983073B (zh) * 2011-09-05 2015-12-09 中国科学院微电子研究所 小尺寸鳍形结构的制造方法
US8507350B2 (en) 2011-09-21 2013-08-13 United Microelectronics Corporation Fabricating method of semiconductor elements
US8497198B2 (en) 2011-09-23 2013-07-30 United Microelectronics Corp. Semiconductor process
US8426277B2 (en) 2011-09-23 2013-04-23 United Microelectronics Corp. Semiconductor process
US8722501B2 (en) 2011-10-18 2014-05-13 United Microelectronics Corp. Method for manufacturing multi-gate transistor device
US8575708B2 (en) 2011-10-26 2013-11-05 United Microelectronics Corp. Structure of field effect transistor with fin structure
US8871575B2 (en) 2011-10-31 2014-10-28 United Microelectronics Corp. Method of fabricating field effect transistor with fin structure
US8278184B1 (en) 2011-11-02 2012-10-02 United Microelectronics Corp. Fabrication method of a non-planar transistor
US9006092B2 (en) 2011-11-03 2015-04-14 United Microelectronics Corp. Semiconductor structure having fluoride metal layer and process thereof
US8975672B2 (en) 2011-11-09 2015-03-10 United Microelectronics Corp. Metal oxide semiconductor transistor and manufacturing method thereof
US8426283B1 (en) 2011-11-10 2013-04-23 United Microelectronics Corp. Method of fabricating a double-gate transistor and a tri-gate transistor on a common substrate
US8440511B1 (en) 2011-11-16 2013-05-14 United Microelectronics Corp. Method for manufacturing multi-gate transistor device
US9406518B2 (en) * 2011-11-18 2016-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. (110) surface orientation for reducing fermi-level-pinning between high-K dielectric and group III-V compound semiconductor substrate
US8604548B2 (en) 2011-11-23 2013-12-10 United Microelectronics Corp. Semiconductor device having ESD device
US8921206B2 (en) 2011-11-30 2014-12-30 United Microelectronics Corp. Semiconductor process
US8803247B2 (en) 2011-12-15 2014-08-12 United Microelectronics Corporation Fin-type field effect transistor
US8709888B2 (en) 2011-12-16 2014-04-29 International Business Machines Corporation Hybrid CMOS nanowire mesh device and PDSOI device
US8563376B2 (en) 2011-12-16 2013-10-22 International Business Machines Corporation Hybrid CMOS nanowire mesh device and bulk CMOS device
US8722472B2 (en) 2011-12-16 2014-05-13 International Business Machines Corporation Hybrid CMOS nanowire mesh device and FINFET device
US8698199B2 (en) 2012-01-11 2014-04-15 United Microelectronics Corp. FinFET structure
US9698229B2 (en) 2012-01-17 2017-07-04 United Microelectronics Corp. Semiconductor structure and process thereof
US8946031B2 (en) 2012-01-18 2015-02-03 United Microelectronics Corp. Method for fabricating MOS device
US8587068B2 (en) * 2012-01-26 2013-11-19 International Business Machines Corporation SRAM with hybrid FinFET and planar transistors
US8987096B2 (en) 2012-02-07 2015-03-24 United Microelectronics Corp. Semiconductor process
US8664060B2 (en) 2012-02-07 2014-03-04 United Microelectronics Corp. Semiconductor structure and method of fabricating the same
US8536072B2 (en) 2012-02-07 2013-09-17 United Microelectronics Corp. Semiconductor process
US8822284B2 (en) 2012-02-09 2014-09-02 United Microelectronics Corp. Method for fabricating FinFETs and semiconductor structure fabricated using the method
US9159809B2 (en) 2012-02-29 2015-10-13 United Microelectronics Corp. Multi-gate transistor device
US9006107B2 (en) 2012-03-11 2015-04-14 United Microelectronics Corp. Patterned structure of semiconductor device and fabricating method thereof
US9159626B2 (en) 2012-03-13 2015-10-13 United Microelectronics Corp. FinFET and fabricating method thereof
US8946078B2 (en) 2012-03-22 2015-02-03 United Microelectronics Corp. Method of forming trench in semiconductor substrate
US8692291B2 (en) 2012-03-27 2014-04-08 International Business Machines Corporation Passive devices for FinFET integrated circuit technologies
US9559189B2 (en) 2012-04-16 2017-01-31 United Microelectronics Corp. Non-planar FET
US9142649B2 (en) 2012-04-23 2015-09-22 United Microelectronics Corp. Semiconductor structure with metal gate and method of fabricating the same
US8766319B2 (en) 2012-04-26 2014-07-01 United Microelectronics Corp. Semiconductor device with ultra thin silicide layer
US8709910B2 (en) 2012-04-30 2014-04-29 United Microelectronics Corp. Semiconductor process
US8691652B2 (en) 2012-05-03 2014-04-08 United Microelectronics Corp. Semiconductor process
US8877623B2 (en) 2012-05-14 2014-11-04 United Microelectronics Corp. Method of forming semiconductor device
US8470714B1 (en) 2012-05-22 2013-06-25 United Microelectronics Corp. Method of forming fin structures in integrated circuits
KR20130133559A (ko) * 2012-05-29 2013-12-09 에스케이하이닉스 주식회사 반도체 소자의 형성방법
US8723268B2 (en) * 2012-06-13 2014-05-13 Synopsys, Inc. N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch
US9012975B2 (en) 2012-06-14 2015-04-21 United Microelectronics Corp. Field effect transistor and manufacturing method thereof
US8796695B2 (en) 2012-06-22 2014-08-05 United Microelectronics Corp. Multi-gate field-effect transistor and process thereof
US8501636B1 (en) 2012-07-24 2013-08-06 United Microelectronics Corp. Method for fabricating silicon dioxide layer
US8872280B2 (en) 2012-07-31 2014-10-28 United Microelectronics Corp. Non-planar FET and manufacturing method thereof
US9318567B2 (en) 2012-09-05 2016-04-19 United Microelectronics Corp. Fabrication method for semiconductor devices
US8815656B2 (en) 2012-09-19 2014-08-26 International Business Machines Corporation Semiconductor device and method with greater epitaxial growth on 110 crystal plane
US9064931B2 (en) 2012-10-11 2015-06-23 United Microelectronics Corp. Semiconductor structure having contact plug and metal gate transistor and method of making the same
US9159831B2 (en) 2012-10-29 2015-10-13 United Microelectronics Corp. Multigate field effect transistor and process thereof
US8927388B2 (en) 2012-11-15 2015-01-06 United Microelectronics Corp. Method of fabricating dielectric layer and shallow trench isolation
US8946063B2 (en) * 2012-11-30 2015-02-03 International Business Machines Corporation Semiconductor device having SSOI substrate with relaxed tensile stress
US8883621B2 (en) 2012-12-27 2014-11-11 United Microelectronics Corp. Semiconductor structure and method of fabricating MOS device
US9536792B2 (en) 2013-01-10 2017-01-03 United Microelectronics Corp. Complementary metal oxide semiconductor field effect transistor, metal oxide semiconductor field effect transistor and manufacturing method thereof
US9076870B2 (en) 2013-02-21 2015-07-07 United Microelectronics Corp. Method for forming fin-shaped structure
US9196352B2 (en) 2013-02-25 2015-11-24 United Microelectronics Corp. Static random access memory unit cell structure and static random access memory unit cell layout structure
US8841197B1 (en) 2013-03-06 2014-09-23 United Microelectronics Corp. Method for forming fin-shaped structures
TWI570812B (zh) * 2013-03-06 2017-02-11 聯華電子股份有限公司 形成鰭狀結構的方法
US8753902B1 (en) 2013-03-13 2014-06-17 United Microelectronics Corp. Method of controlling etching process for forming epitaxial structure
US9214395B2 (en) 2013-03-13 2015-12-15 United Microelectronics Corp. Method of manufacturing semiconductor devices
US9093285B2 (en) 2013-03-22 2015-07-28 United Microelectronics Corp. Semiconductor structure and process thereof
US9196500B2 (en) 2013-04-09 2015-11-24 United Microelectronics Corp. Method for manufacturing semiconductor structures
US9711368B2 (en) 2013-04-15 2017-07-18 United Microelectronics Corp. Sidewall image transfer process
US8853015B1 (en) 2013-04-16 2014-10-07 United Microelectronics Corp. Method of forming a FinFET structure
US8709901B1 (en) 2013-04-17 2014-04-29 United Microelectronics Corp. Method of forming an isolation structure
US9147747B2 (en) 2013-05-02 2015-09-29 United Microelectronics Corp. Semiconductor structure with hard mask disposed on the gate structure
CN104143514B (zh) * 2013-05-09 2017-09-26 中芯国际集成电路制造(上海)有限公司 多栅极场效应晶体管的形成方法
US9000483B2 (en) 2013-05-16 2015-04-07 United Microelectronics Corp. Semiconductor device with fin structure and fabrication method thereof
US9230812B2 (en) 2013-05-22 2016-01-05 United Microelectronics Corp. Method for forming semiconductor structure having opening
US8993433B2 (en) 2013-05-27 2015-03-31 United Microelectronics Corp. Manufacturing method for forming a self aligned contact
US9349812B2 (en) 2013-05-27 2016-05-24 United Microelectronics Corp. Semiconductor device with self-aligned contact and method of manufacturing the same
US9263287B2 (en) 2013-05-27 2016-02-16 United Microelectronics Corp. Method of forming fin-shaped structure
US8802521B1 (en) 2013-06-04 2014-08-12 United Microelectronics Corp. Semiconductor fin-shaped structure and manufacturing process thereof
US9006804B2 (en) 2013-06-06 2015-04-14 United Microelectronics Corp. Semiconductor device and fabrication method thereof
WO2014197891A2 (en) 2013-06-07 2014-12-11 Cornell University Floating gate based sensor apparatus and related floating gate based sensor applications
US9070710B2 (en) 2013-06-07 2015-06-30 United Microelectronics Corp. Semiconductor process
US8993384B2 (en) 2013-06-09 2015-03-31 United Microelectronics Corp. Semiconductor device and fabrication method thereof
US9263282B2 (en) 2013-06-13 2016-02-16 United Microelectronics Corporation Method of fabricating semiconductor patterns
TWI566273B (zh) * 2013-06-13 2017-01-11 聯華電子股份有限公司 半導體圖案之製造方法
US9401429B2 (en) 2013-06-13 2016-07-26 United Microelectronics Corp. Semiconductor structure and process thereof
US9123810B2 (en) 2013-06-18 2015-09-01 United Microelectronics Corp. Semiconductor integrated device including FinFET device and protecting structure
US9048246B2 (en) 2013-06-18 2015-06-02 United Microelectronics Corp. Die seal ring and method of forming the same
US9064814B2 (en) 2013-06-19 2015-06-23 United Microelectronics Corp. Semiconductor structure having metal gate and manufacturing method thereof
US9190291B2 (en) 2013-07-03 2015-11-17 United Microelectronics Corp. Fin-shaped structure forming process
US9105685B2 (en) 2013-07-12 2015-08-11 United Microelectronics Corp. Method of forming shallow trench isolation structure
US9093565B2 (en) 2013-07-15 2015-07-28 United Microelectronics Corp. Fin diode structure
US9019672B2 (en) 2013-07-17 2015-04-28 United Microelectronics Corporation Chip with electrostatic discharge protection function
US8981487B2 (en) 2013-07-31 2015-03-17 United Microelectronics Corp. Fin-shaped field-effect transistor (FinFET)
US9006805B2 (en) 2013-08-07 2015-04-14 United Microelectronics Corp. Semiconductor device
KR102069609B1 (ko) 2013-08-12 2020-01-23 삼성전자주식회사 반도체 소자 및 그 제조 방법
US9105582B2 (en) 2013-08-15 2015-08-11 United Microelectronics Corporation Spatial semiconductor structure and method of fabricating the same
US9385048B2 (en) 2013-09-05 2016-07-05 United Microelectronics Corp. Method of forming Fin-FET
US9373719B2 (en) 2013-09-16 2016-06-21 United Microelectronics Corp. Semiconductor device
US9018066B2 (en) 2013-09-30 2015-04-28 United Microelectronics Corp. Method of fabricating semiconductor device structure
US9166024B2 (en) 2013-09-30 2015-10-20 United Microelectronics Corp. FinFET structure with cavities and semiconductor compound portions extending laterally over sidewall spacers
US9306032B2 (en) 2013-10-25 2016-04-05 United Microelectronics Corp. Method of forming self-aligned metal gate structure in a replacement gate process using tapered interlayer dielectric
US8980701B1 (en) 2013-11-05 2015-03-17 United Microelectronics Corp. Method of forming semiconductor device
US9299843B2 (en) 2013-11-13 2016-03-29 United Microelectronics Corp. Semiconductor structure and manufacturing method thereof
US8951884B1 (en) 2013-11-14 2015-02-10 United Microelectronics Corp. Method for forming a FinFET structure
US9059020B1 (en) 2013-12-02 2015-06-16 International Business Machins Corporation Implementing buried FET below and beside FinFET on bulk substrate
CN103943484B (zh) * 2014-04-28 2016-08-17 上海华力微电子有限公司 自对准的栅极分离方法
US9281303B2 (en) 2014-05-28 2016-03-08 International Business Machines Corporation Electrostatic discharge devices and methods of manufacture
KR102347185B1 (ko) 2015-02-03 2022-01-04 삼성전자주식회사 반도체 소자 및 그 제조 방법
US9899224B2 (en) 2015-03-03 2018-02-20 Tokyo Electron Limited Method of controlling solid phase diffusion of boron dopants to form ultra-shallow doping regions
US20160268256A1 (en) * 2015-03-13 2016-09-15 Qualcomm Incorporated Complementary metal-oxide semiconductor (cmos) transistor and tunnel field-effect transistor (tfet) on a single substrate
US9419015B1 (en) * 2015-03-13 2016-08-16 Globalfoundries Inc. Method for integrating thin-film transistors on an isolation region in an integrated circuit and resulting device
CN104966672B (zh) * 2015-06-30 2019-01-25 上海华力微电子有限公司 鳍式场效应管基体制备方法
US9666581B2 (en) * 2015-08-21 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with source/drain structure and method of fabrication thereof
US9978748B2 (en) * 2015-12-09 2018-05-22 International Business Machines Corporation Method of cutting fins to create diffusion breaks for finFETs
US10026653B2 (en) * 2015-12-16 2018-07-17 International Business Machines Corporation Variable gate lengths for vertical transistors
US11018254B2 (en) 2016-03-31 2021-05-25 International Business Machines Corporation Fabrication of vertical fin transistor with multiple threshold voltages
CN105655410B (zh) * 2016-04-13 2019-07-30 京东方科技集团股份有限公司 非遮光型薄膜晶体管、阵列基板及显示装置
US9793271B1 (en) * 2016-04-29 2017-10-17 International Business Machines Corporation Semiconductor device with different fin pitches
US9916978B2 (en) 2016-06-02 2018-03-13 United Microelectronics Corporation Method for fabricating a Fin field effect transistor (FinFET)
US10049944B2 (en) 2016-10-05 2018-08-14 Globalfoundries Inc. Method of manufacturing selective nanostructures into finFET process flow
US10517179B2 (en) * 2016-12-15 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Material composition and methods thereof
US9870952B1 (en) 2017-02-07 2018-01-16 International Business Machines Corporation Formation of VFET and finFET
US10090410B1 (en) 2017-03-17 2018-10-02 International Business Machines Corporation Forming a combination of long channel devices and vertical transport fin field effect transistors on the same substrate
US10679992B1 (en) 2018-11-16 2020-06-09 International Business Machines Corporation Integrated device with vertical field-effect transistors and hybrid channels
DE102021121138B3 (de) 2021-08-13 2023-02-02 Infineon Technologies Ag Halbleitervorrichtungen und verfahren zum herstellen einer halbleitervorrichtung
US11908743B2 (en) 2021-09-27 2024-02-20 International Business Machines Corporation Planar devices with consistent base dielectric

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6292361A (ja) 1985-10-17 1987-04-27 Toshiba Corp 相補型半導体装置
DE3851486T2 (de) 1987-07-14 1995-02-23 Agfa Gevaert Nv Verfahren zum Herstellen von gekräuseltem photographischem Film.
JPH07183488A (ja) 1993-12-24 1995-07-21 Nissan Motor Co Ltd Ｍｏｓ制御形サイリスタおよびその製造方法
JP2924763B2 (ja) * 1996-02-28 1999-07-26 日本電気株式会社 半導体装置の製造方法
US6245615B1 (en) 1999-08-31 2001-06-12 Micron Technology, Inc. Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction
JP4397491B2 (ja) 1999-11-30 2010-01-13 財団法人国際科学振興財団 １１１面方位を表面に有するシリコンを用いた半導体装置およびその形成方法
US6252284B1 (en) * 1999-12-09 2001-06-26 International Business Machines Corporation Planarized silicon fin device
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US7312485B2 (en) 2000-11-29 2007-12-25 Intel Corporation CMOS fabrication process utilizing special transistor orientation
US6300182B1 (en) * 2000-12-11 2001-10-09 Advanced Micro Devices, Inc. Field effect transistor having dual gates with asymmetrical doping for reduced threshold voltage
JP2002359293A (ja) 2001-05-31 2002-12-13 Toshiba Corp 半導体装置
US6657259B2 (en) * 2001-12-04 2003-12-02 International Business Machines Corporation Multiple-plane FinFET CMOS
US7358121B2 (en) * 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US7163851B2 (en) * 2002-08-26 2007-01-16 International Business Machines Corporation Concurrent Fin-FET and thick-body device fabrication

Also Published As

Publication number Publication date
CN1591838A (zh) 2005-03-09
TWI283018B (en) 2007-06-21
US7250658B2 (en) 2007-07-31
TW200507079A (en) 2005-02-16
US6911383B2 (en) 2005-06-28
JP4006419B2 (ja) 2007-11-14
JP2005019996A (ja) 2005-01-20
US20040266076A1 (en) 2004-12-30
US20050263831A1 (en) 2005-12-01

Similar Documents

Publication Publication Date Title
CN1292473C (zh) 混合平面和FinFET CMOS器件
US10755985B2 (en) Gate metal patterning for tight pitch applications
EP1565931B1 (en) Strained finfet cmos device structures
US7952142B2 (en) Variable width offset spacers for mixed signal and system on chip devices
CN103165674B (zh) 具有多阈值电压的FinFET
US7659561B2 (en) Methods of fabricating semiconductor devices and structures thereof
CN1282233C (zh) 双栅极场效应晶体管及其制造方法
CN1838417A (zh) 半导体结构及其形成方法
KR20150050338A (ko) Ｆⅰｎｆｅｔ 디바이스를 형성하기 위한 메커니즘들
KR20080058341A (ko) 낮은 밀러 용량 및 향상된 구동 전류를 위한 단일 게이트상의 다중 저유전율 및 고유전율 게이트 산화막
US20050093105A1 (en) Semiconductor-on-insulator chip with&lt;100&gt;-oriented transistors
JP5224769B2 (ja) 立体的形状の活性領域を含むｃｍｏｓ構造体
US7981784B2 (en) Methods of manufacturing a semiconductor device
CN101055851A (zh) 互补金属氧化物半导体及其形成方法
US6664146B1 (en) Integration of fully depleted and partially depleted field effect transistors formed in SOI technology
JP2007103456A (ja) 半導体装置及びその製造方法
EP1593155A1 (en) Method of manufacturing a semiconductor device and semiconductor device obtained by means of such a method
KR102598765B1 (ko) 반도체 디바이스 및 제조 방법
US7229885B2 (en) Formation of a disposable spacer to post dope a gate conductor
KR100314151B1 (ko) 반도체소자의 트랜지스터 형성방법
CN115332172A (zh) 集成电路的制造方法
CN114664944A (zh) 半导体结构及其形成方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20170109

Address after: The Cayman Islands (British) Grand Cayman

Patentee after: INTERNATIONAL BUSINESS MACHINES Corp.

Address before: American New York

Patentee before: Globalfoundries second U.S. Semiconductor Co.,Ltd.

Effective date of registration: 20170109

Address after: American New York

Patentee after: Globalfoundries second U.S. Semiconductor Co.,Ltd.

Address before: American New York

Patentee before: International Business Machines Corp.

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20180328

Address after: Ontario, Canada

Patentee after: International Business Machines Corp.

Address before: The Cayman Islands (British) Grand Cayman

Patentee before: INTERNATIONAL BUSINESS MACHINES Corp.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20061227

Termination date: 20210625