JP3825862B2 - 同期型ダイナミック型半導体記憶装置 - Google Patents

同期型ダイナミック型半導体記憶装置 Download PDF

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Publication number
JP3825862B2
JP3825862B2 JP04388897A JP4388897A JP3825862B2 JP 3825862 B2 JP3825862 B2 JP 3825862B2 JP 04388897 A JP04388897 A JP 04388897A JP 4388897 A JP4388897 A JP 4388897A JP 3825862 B2 JP3825862 B2 JP 3825862B2
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JP
Japan
Prior art keywords
signal
clock signal
wiring
data
external
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Expired - Fee Related
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JP04388897A
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English (en)
Japanese (ja)
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JPH10241363A5 (enExample
JPH10241363A (ja
Inventor
正樹 築出
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Renesas Technology Corp
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Renesas Technology Corp
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Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP04388897A priority Critical patent/JP3825862B2/ja
Priority to KR1019970037180A priority patent/KR100261640B1/ko
Priority to US08/912,200 priority patent/US5812490A/en
Publication of JPH10241363A publication Critical patent/JPH10241363A/ja
Publication of JPH10241363A5 publication Critical patent/JPH10241363A5/ja
Application granted granted Critical
Publication of JP3825862B2 publication Critical patent/JP3825862B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
JP04388897A 1997-02-27 1997-02-27 同期型ダイナミック型半導体記憶装置 Expired - Fee Related JP3825862B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP04388897A JP3825862B2 (ja) 1997-02-27 1997-02-27 同期型ダイナミック型半導体記憶装置
KR1019970037180A KR100261640B1 (ko) 1997-02-27 1997-08-04 동기형 다이나믹형 반도체 기억 장치
US08/912,200 US5812490A (en) 1997-02-27 1997-08-18 Synchronous dynamic semiconductor memory device capable of restricting delay of data output timing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP04388897A JP3825862B2 (ja) 1997-02-27 1997-02-27 同期型ダイナミック型半導体記憶装置

Publications (3)

Publication Number Publication Date
JPH10241363A JPH10241363A (ja) 1998-09-11
JPH10241363A5 JPH10241363A5 (enExample) 2005-01-20
JP3825862B2 true JP3825862B2 (ja) 2006-09-27

Family

ID=12676251

Family Applications (1)

Application Number Title Priority Date Filing Date
JP04388897A Expired - Fee Related JP3825862B2 (ja) 1997-02-27 1997-02-27 同期型ダイナミック型半導体記憶装置

Country Status (3)

Country Link
US (1) US5812490A (enExample)
JP (1) JP3825862B2 (enExample)
KR (1) KR100261640B1 (enExample)

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JP3099931B2 (ja) * 1993-09-29 2000-10-16 株式会社東芝 半導体装置
KR0158762B1 (ko) * 1994-02-17 1998-12-01 세키자와 다다시 반도체 장치
JP3421441B2 (ja) * 1994-09-22 2003-06-30 東芝マイクロエレクトロニクス株式会社 ダイナミック型メモリ
US6525971B2 (en) 1995-06-30 2003-02-25 Micron Technology, Inc. Distributed write data drivers for burst access memories
US6804760B2 (en) 1994-12-23 2004-10-12 Micron Technology, Inc. Method for determining a type of memory present in a system
US5526320A (en) 1994-12-23 1996-06-11 Micron Technology Inc. Burst EDO memory device
US5610864A (en) 1994-12-23 1997-03-11 Micron Technology, Inc. Burst EDO memory device with maximized write cycle timing
US6401186B1 (en) 1996-07-03 2002-06-04 Micron Technology, Inc. Continuous burst memory which anticipates a next requested start address
US6981126B1 (en) 1996-07-03 2005-12-27 Micron Technology, Inc. Continuous interleave burst access
JP4090088B2 (ja) * 1996-09-17 2008-05-28 富士通株式会社 半導体装置システム及び半導体装置
US5959937A (en) * 1997-03-07 1999-09-28 Mitsubishi Semiconductor America, Inc. Dual clocking scheme in a multi-port RAM
US6072743A (en) 1998-01-13 2000-06-06 Mitsubishi Denki Kabushiki Kaisha High speed operable semiconductor memory device with memory blocks arranged about the center
US6151257A (en) * 1998-01-26 2000-11-21 Intel Corporation Apparatus for receiving/transmitting signals in an input/output pad buffer cell
JPH11219598A (ja) * 1998-02-03 1999-08-10 Mitsubishi Electric Corp 半導体記憶装置
US5936877A (en) 1998-02-13 1999-08-10 Micron Technology, Inc. Die architecture accommodating high-speed semiconductor devices
KR100306881B1 (ko) * 1998-04-02 2001-10-29 박종섭 동기 반도체 메모리를 위한 인터페이스
JP3125749B2 (ja) * 1998-06-11 2001-01-22 日本電気株式会社 同期型半導体メモリ
JP4540137B2 (ja) * 1998-07-24 2010-09-08 ルネサスエレクトロニクス株式会社 同期型半導体記憶装置
US6081477A (en) * 1998-12-03 2000-06-27 Micron Technology, Inc. Write scheme for a double data rate SDRAM
JP3557114B2 (ja) * 1998-12-22 2004-08-25 株式会社東芝 半導体記憶装置
JP2000207900A (ja) * 1999-01-12 2000-07-28 Mitsubishi Electric Corp 同期型半導体記憶装置
US6356981B1 (en) * 1999-02-12 2002-03-12 International Business Machines Corporation Method and apparatus for preserving data coherency in a double data rate SRAM
US6088254A (en) * 1999-02-12 2000-07-11 Lucent Technologies Inc. Uniform mesh clock distribution system
KR100358121B1 (ko) 1999-05-13 2002-10-25 주식회사 하이닉스반도체 반도체장치의 신호 입력회로
KR100324821B1 (ko) 1999-06-29 2002-02-28 박종섭 반도체 메모리 소자의 자동 리프레쉬 방법 및 장치
KR100299187B1 (ko) * 1999-07-15 2001-11-01 윤종용 반도체 메모리 장치 및 이 장치의 데이터 리드 방법
DE19933540C2 (de) * 1999-07-16 2001-10-04 Infineon Technologies Ag Synchroner integrierter Speicher
JP3668064B2 (ja) 1999-08-27 2005-07-06 株式会社東芝 半導体記憶装置
JP2001067866A (ja) 1999-08-30 2001-03-16 Mitsubishi Electric Corp 同期型半導体記憶装置
JP4353324B2 (ja) * 1999-08-31 2009-10-28 エルピーダメモリ株式会社 半導体装置
JP2001084762A (ja) * 1999-09-16 2001-03-30 Matsushita Electric Ind Co Ltd 半導体メモリ装置
KR100374638B1 (ko) 2000-10-25 2003-03-04 삼성전자주식회사 입출력데이타의 전파경로 및 전파경로들 간의 차이를최소화하는 회로를 구비하는 반도체 메모리장치
KR100382739B1 (ko) * 2001-04-13 2003-05-09 삼성전자주식회사 비대칭 데이터 경로를 갖는 반도체 메모리 장치
KR100463202B1 (ko) * 2002-07-02 2004-12-23 삼성전자주식회사 반도체 메모리 장치의 패드 및 주변 회로 레이아웃
US7006402B2 (en) * 2003-08-29 2006-02-28 Hynix Semiconductor Inc Multi-port memory device
KR100550643B1 (ko) * 2004-09-06 2006-02-09 주식회사 하이닉스반도체 반도체메모리소자
US7382591B2 (en) * 2005-05-20 2008-06-03 Intel Corporation Cascode protected negative voltage switching
US7369453B2 (en) * 2006-02-28 2008-05-06 Samsung Electronics Co., Ltd. Multi-port memory device and method of controlling the same
JP4267006B2 (ja) * 2006-07-24 2009-05-27 エルピーダメモリ株式会社 半導体記憶装置
US20090109772A1 (en) * 2007-10-24 2009-04-30 Esin Terzioglu Ram with independent local clock
KR100940838B1 (ko) * 2008-06-04 2010-02-04 주식회사 하이닉스반도체 반도체 집적회로의 클럭 신호 발생 장치 및 방법
JP5695895B2 (ja) * 2010-12-16 2015-04-08 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置
KR102167609B1 (ko) * 2014-05-13 2020-10-20 삼성전자주식회사 비휘발성 메모리 장치 및 그것의 프로그램 방법
JP2020047325A (ja) 2018-09-18 2020-03-26 キオクシア株式会社 半導体記憶装置
US10811057B1 (en) 2019-03-26 2020-10-20 Micron Technology, Inc. Centralized placement of command and address in memory devices
US10978117B2 (en) 2019-03-26 2021-04-13 Micron Technology, Inc. Centralized placement of command and address swapping in memory devices
US10811059B1 (en) 2019-03-27 2020-10-20 Micron Technology, Inc. Routing for power signals including a redistribution layer
US11031335B2 (en) 2019-04-03 2021-06-08 Micron Technology, Inc. Semiconductor devices including redistribution layers
JP6734962B1 (ja) * 2019-04-17 2020-08-05 ウィンボンド エレクトロニクス コーポレーション 半導体装置
US11527280B2 (en) * 2020-08-25 2022-12-13 Microsoft Technology Licensing, Llc Monitoring and mitigation of row disturbance in memory
CN114121083B (zh) * 2020-08-26 2025-03-28 长鑫存储技术(上海)有限公司 接口电路、数据传输电路以及存储器
KR102789857B1 (ko) * 2020-08-31 2025-04-03 에스케이하이닉스 주식회사 저장 장치 및 그 동작 방법
US12272427B2 (en) * 2021-07-29 2025-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including first and second clock generators

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02194545A (ja) * 1989-01-23 1990-08-01 Nec Corp 半導体集積回路
JPH0722511A (ja) * 1993-07-05 1995-01-24 Mitsubishi Electric Corp 半導体装置
US5604710A (en) * 1994-05-20 1997-02-18 Mitsubishi Denki Kabushiki Kaisha Arrangement of power supply and data input/output pads in semiconductor memory device
JP2697634B2 (ja) * 1994-09-30 1998-01-14 日本電気株式会社 同期型半導体記憶装置
JP3252678B2 (ja) * 1995-10-20 2002-02-04 日本電気株式会社 同期式半導体メモリ

Also Published As

Publication number Publication date
US5812490A (en) 1998-09-22
JPH10241363A (ja) 1998-09-11
KR19980069874A (ko) 1998-10-26
KR100261640B1 (ko) 2000-07-15

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