JP3623804B2 - イオンが注入された構造体および形成方法 - Google Patents

イオンが注入された構造体および形成方法 Download PDF

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Publication number
JP3623804B2
JP3623804B2 JP53986698A JP53986698A JP3623804B2 JP 3623804 B2 JP3623804 B2 JP 3623804B2 JP 53986698 A JP53986698 A JP 53986698A JP 53986698 A JP53986698 A JP 53986698A JP 3623804 B2 JP3623804 B2 JP 3623804B2
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Prior art keywords
silicon
semiconductor substrate
ions
implanted
containing material
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Expired - Fee Related
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JP53986698A
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Japanese (ja)
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JP2001517364A (ja
Inventor
ウー，ジキアン
リ，リ
フィグラ，トーマス・エイ
パレク，クナル・アール
パン，パイ−フン
レインバーグ，アラン・アール
マ，キン・エフ
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Micron Technology Inc
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Micron Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/2815—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
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    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/022—Manufacture or treatment of FETs having insulated gates [IGFET] having lightly-doped source or drain extensions selectively formed at the sides of the gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Weting (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
JP53986698A 1997-03-14 1998-03-13 イオンが注入された構造体および形成方法 Expired - Fee Related JP3623804B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/818,660 US6309975B1 (en) 1997-03-14 1997-03-14 Methods of making implanted structures
US08/818,660 1997-03-14
PCT/US1998/005001 WO1998040909A2 (en) 1997-03-14 1998-03-13 Method of forming etched structures comprising implantation steps

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2003331791A Division JP2004072122A (ja) 1997-03-14 2003-09-24 電気的素子

Publications (2)

Publication Number Publication Date
JP2001517364A JP2001517364A (ja) 2001-10-02
JP3623804B2 true JP3623804B2 (ja) 2005-02-23

Family

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Application Number Title Priority Date Filing Date
JP53986698A Expired - Fee Related JP3623804B2 (ja) 1997-03-14 1998-03-13 イオンが注入された構造体および形成方法
JP2003331791A Pending JP2004072122A (ja) 1997-03-14 2003-09-24 電気的素子

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2003331791A Pending JP2004072122A (ja) 1997-03-14 2003-09-24 電気的素子

Country Status (7)

Country Link
US (6) US6309975B1 (enExample)
EP (1) EP0968526A2 (enExample)
JP (2) JP3623804B2 (enExample)
KR (2) KR100485995B1 (enExample)
AU (1) AU6555198A (enExample)
TW (1) TW419742B (enExample)
WO (1) WO1998040909A2 (enExample)

Families Citing this family (210)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6309975B1 (en) * 1997-03-14 2001-10-30 Micron Technology, Inc. Methods of making implanted structures
US20030075778A1 (en) * 1997-10-01 2003-04-24 Patrick Klersy Programmable resistance memory element and method for making same
JPH11186524A (ja) * 1997-12-24 1999-07-09 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6632718B1 (en) * 1998-07-15 2003-10-14 Texas Instruments Incorporated Disposable spacer technology for reduced cost CMOS processing
US7064070B2 (en) 1998-09-28 2006-06-20 Tokyo Electron Limited Removal of CMP and post-CMP residue from semiconductors using supercritical carbon dioxide process
US20020063263A1 (en) * 2000-11-30 2002-05-30 Scott David B. Metal oxide semiconductor transistor with self-aligned channel implant
JP2001166456A (ja) * 1999-12-07 2001-06-22 Mitsubishi Electric Corp ウェハパターン誤差の要因解析方法および写真製版用マスクの製造装置
US6890853B2 (en) 2000-04-25 2005-05-10 Tokyo Electron Limited Method of depositing metal film and metal deposition cluster tool including supercritical drying/cleaning module
US6306775B1 (en) * 2000-06-21 2001-10-23 Micron Technology, Inc. Methods of selectively etching polysilicon relative to at least one of deposited oxide, thermally grown oxide and nitride, and methods of selectively etching polysilicon relative to BPSG
US6573137B1 (en) * 2000-06-23 2003-06-03 International Business Machines Corporation Single sided buried strap
US6535413B1 (en) * 2000-08-31 2003-03-18 Micron Technology, Inc. Method of selectively forming local interconnects using design rules
US7087509B1 (en) * 2000-09-28 2006-08-08 Advanced Micro Devices, Inc. Method of forming a gate electrode on a semiconductor device and a device incorporating same
US6383937B1 (en) * 2000-11-17 2002-05-07 Vanguard International Semiconductor Corp. Method of fabricating a silicon island
US6498061B2 (en) * 2000-12-06 2002-12-24 International Business Machines Corporation Negative ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formation
US6936527B1 (en) 2000-12-19 2005-08-30 Xilinx, Inc. Low voltage non-volatile memory cell
US6496416B1 (en) * 2000-12-19 2002-12-17 Xilinx, Inc. Low voltage non-volatile memory cell
DE10101270A1 (de) * 2001-01-12 2002-07-25 Infineon Technologies Ag Verfahren zur Herstellung von eingebetteten nichtflüchtigen Halbleiterspeicherzellen
US6482688B2 (en) * 2001-03-30 2002-11-19 Texas Instruments Incorporated Utilizing amorphorization of polycrystalline structures to achieve T-shaped MOSFET gate
DE10126294C1 (de) 2001-05-30 2002-11-28 Infineon Technologies Ag Herstellungsverfahren für eine integrierte Schaltung
US6583060B2 (en) * 2001-07-13 2003-06-24 Micron Technology, Inc. Dual depth trench isolation
EP1415330B1 (en) * 2001-07-18 2012-02-01 Infineon Technologies AG Selective base etching
US6818528B2 (en) 2001-10-24 2004-11-16 International Business Machines Corporation Method for multi-depth trench isolation
DE10157627A1 (de) * 2001-11-26 2003-06-12 Forschungszentrum Juelich Gmbh Verfahren zur Herstellung einer Schicht auf einem Substrat
US6806151B2 (en) * 2001-12-14 2004-10-19 Texas Instruments Incorporated Methods and apparatus for inducing stress in a semiconductor device
US6924086B1 (en) 2002-02-15 2005-08-02 Tokyo Electron Limited Developing photoresist with supercritical fluid and developer
WO2003070846A2 (en) 2002-02-15 2003-08-28 Supercritical Systems Inc. Drying resist with a solvent bath and supercritical co2
JP4246640B2 (ja) 2002-03-04 2009-04-02 東京エレクトロン株式会社 ウェハ処理において低誘電率材料を不動態化する方法
US7387868B2 (en) 2002-03-04 2008-06-17 Tokyo Electron Limited Treatment of a dielectric layer using supercritical CO2
DE10212610C1 (de) * 2002-03-21 2003-11-06 Infineon Technologies Ag Verfahren zur Erzeugung einer horizontalen Isolationsschicht auf einem leitenden Material in einem Graben
US6821848B2 (en) * 2002-04-02 2004-11-23 Hewlett-Packard Development Company, L.P. Tunnel-junction structures and methods
US7169540B2 (en) 2002-04-12 2007-01-30 Tokyo Electron Limited Method of treatment of porous dielectric films to reduce damage during cleaning
US6847077B2 (en) * 2002-06-25 2005-01-25 Agere Systems, Inc. Capacitor for a semiconductor device and method for fabrication therefor
DE10230252B4 (de) * 2002-07-04 2013-10-17 Robert Bosch Gmbh Verfahren zur Herstellung integrierter Mikrosysteme
US7473947B2 (en) * 2002-07-12 2009-01-06 Intel Corporation Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby
FR2842944A1 (fr) * 2002-07-23 2004-01-30 St Microelectronics Sa Procede de formation d'ouvertures de contact sur un circuit integre mos
KR100493025B1 (ko) * 2002-08-07 2005-06-07 삼성전자주식회사 반도체 메모리 장치의 제조 방법
US7494894B2 (en) * 2002-08-29 2009-02-24 Micron Technology, Inc. Protection in integrated circuits
US6583014B1 (en) * 2002-09-18 2003-06-24 Taiwan Semiconductor Manufacturing Company Horizontal surrounding gate MOSFETS
US6746967B2 (en) * 2002-09-30 2004-06-08 Intel Corporation Etching metal using sonication
US6930920B1 (en) 2002-10-29 2005-08-16 Xilinx, Inc. Low voltage non-volatile memory cell
US7388259B2 (en) * 2002-11-25 2008-06-17 International Business Machines Corporation Strained finFET CMOS device structures
US6787423B1 (en) * 2002-12-09 2004-09-07 Advanced Micro Devices, Inc. Strained-silicon semiconductor device
US6867425B2 (en) * 2002-12-13 2005-03-15 Intel Corporation Lateral phase change memory and method therefor
KR100510510B1 (ko) * 2002-12-28 2005-08-26 삼성전자주식회사 센싱속도 저하를 방지할 수 있는 비트라인 커플링 스킴을갖는 반도체 메모리장치
KR100493060B1 (ko) * 2003-05-01 2005-06-02 삼성전자주식회사 배선 및 연결 콘택을 포함하는 반도체 소자를 제조하는 방법
US6887798B2 (en) * 2003-05-30 2005-05-03 International Business Machines Corporation STI stress modification by nitrogen plasma treatment for improving performance in small width devices
US7329923B2 (en) * 2003-06-17 2008-02-12 International Business Machines Corporation High-performance CMOS devices on hybrid crystal oriented substrates
US6780736B1 (en) * 2003-06-20 2004-08-24 International Business Machines Corporation Method for image reversal of implant resist using a single photolithography exposure and structures formed thereby
US7279746B2 (en) * 2003-06-30 2007-10-09 International Business Machines Corporation High performance CMOS device structures and method of manufacture
KR100531461B1 (ko) 2003-06-30 2005-11-28 주식회사 하이닉스반도체 엠피에스 공정을 이용한 캐패시터의 제조 방법
US6905975B2 (en) * 2003-07-03 2005-06-14 Micron Technology, Inc. Methods of forming patterned compositions
KR100618691B1 (ko) * 2003-07-10 2006-09-05 주식회사 하이닉스반도체 반도체소자의 캐패시터 제조방법
US7163380B2 (en) 2003-07-29 2007-01-16 Tokyo Electron Limited Control of fluid flow in the processing of an object with a fluid
DE10341321B4 (de) * 2003-09-08 2009-11-26 Qimonda Ag Verfahren zur Bildung eines Grabens in einer Schicht oder einem Schichtstapel auf einem Halbleiterwafer
US7410846B2 (en) * 2003-09-09 2008-08-12 International Business Machines Corporation Method for reduced N+ diffusion in strained Si on SiGe substrate
US6890808B2 (en) * 2003-09-10 2005-05-10 International Business Machines Corporation Method and structure for improved MOSFETs using poly/silicide gate height control
US6887751B2 (en) * 2003-09-12 2005-05-03 International Business Machines Corporation MOSFET performance improvement using deformation in SOI structure
US7170126B2 (en) * 2003-09-16 2007-01-30 International Business Machines Corporation Structure of vertical strained silicon devices
US6869866B1 (en) 2003-09-22 2005-03-22 International Business Machines Corporation Silicide proximity structures for CMOS device performance improvements
US7144767B2 (en) * 2003-09-23 2006-12-05 International Business Machines Corporation NFETs using gate induced stress modulation
US6872641B1 (en) * 2003-09-23 2005-03-29 International Business Machines Corporation Strained silicon on relaxed sige film with uniform misfit dislocation density
US7119403B2 (en) 2003-10-16 2006-10-10 International Business Machines Corporation High performance strained CMOS devices
US7303949B2 (en) 2003-10-20 2007-12-04 International Business Machines Corporation High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
US7037770B2 (en) * 2003-10-20 2006-05-02 International Business Machines Corporation Method of manufacturing strained dislocation-free channels for CMOS
US7129126B2 (en) * 2003-11-05 2006-10-31 International Business Machines Corporation Method and structure for forming strained Si for CMOS devices
US7015082B2 (en) * 2003-11-06 2006-03-21 International Business Machines Corporation High mobility CMOS circuits
US7029964B2 (en) * 2003-11-13 2006-04-18 International Business Machines Corporation Method of manufacturing a strained silicon on a SiGe on SOI substrate
US7122849B2 (en) * 2003-11-14 2006-10-17 International Business Machines Corporation Stressed semiconductor device structures having granular semiconductor material
US7115509B2 (en) * 2003-11-17 2006-10-03 Micron Technology, Inc. Method for forming polysilicon local interconnects
US7247534B2 (en) * 2003-11-19 2007-07-24 International Business Machines Corporation Silicon device on Si:C-OI and SGOI and method of manufacture
US7198995B2 (en) * 2003-12-12 2007-04-03 International Business Machines Corporation Strained finFETs and method of manufacture
KR20050062289A (ko) * 2003-12-20 2005-06-23 삼성전기주식회사 마이크로 렌즈 제조방법
US20050136648A1 (en) * 2003-12-23 2005-06-23 Mariah Sharma Method and system for forming a contact in a thin-film device
US7045407B2 (en) * 2003-12-30 2006-05-16 Intel Corporation Amorphous etch stop for the anisotropic etching of substrates
US7247578B2 (en) 2003-12-30 2007-07-24 Intel Corporation Method of varying etch selectivities of a film
US7247912B2 (en) * 2004-01-05 2007-07-24 International Business Machines Corporation Structures and methods for making strained MOSFETs
US7202132B2 (en) 2004-01-16 2007-04-10 International Business Machines Corporation Protecting silicon germanium sidewall with silicon for strained silicon/silicon germanium MOSFETs
US7118999B2 (en) * 2004-01-16 2006-10-10 International Business Machines Corporation Method and apparatus to increase strain effect in a transistor channel
US7381609B2 (en) 2004-01-16 2008-06-03 International Business Machines Corporation Method and structure for controlling stress in a transistor channel
US7923782B2 (en) 2004-02-27 2011-04-12 International Business Machines Corporation Hybrid SOI/bulk semiconductor transistors
US7205206B2 (en) 2004-03-03 2007-04-17 International Business Machines Corporation Method of fabricating mobility enhanced CMOS devices
US7226834B2 (en) 2004-04-19 2007-06-05 Texas Instruments Incorporated PMD liner nitride films and fabrication methods for improved NMOS performance
US7504693B2 (en) * 2004-04-23 2009-03-17 International Business Machines Corporation Dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering
US7086291B2 (en) * 2004-04-29 2006-08-08 International Business Machines Corporation Overstress indication
US7098105B2 (en) 2004-05-26 2006-08-29 Micron Technology, Inc. Methods for forming semiconductor structures
US7223994B2 (en) * 2004-06-03 2007-05-29 International Business Machines Corporation Strained Si on multiple materials for bulk or SOI substrates
DE102004027356B4 (de) * 2004-06-04 2007-08-16 Infineon Technologies Ag Verfahren zur Herstellung eines integrierten Schaltkreises
US7037794B2 (en) * 2004-06-09 2006-05-02 International Business Machines Corporation Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain
US7227205B2 (en) * 2004-06-24 2007-06-05 International Business Machines Corporation Strained-silicon CMOS device and method
JP4837902B2 (ja) 2004-06-24 2011-12-14 富士通セミコンダクター株式会社 半導体装置
TWI463526B (zh) * 2004-06-24 2014-12-01 Ibm 改良具應力矽之ｃｍｏｓ元件的方法及以該方法製備而成的元件
US7288443B2 (en) * 2004-06-29 2007-10-30 International Business Machines Corporation Structures and methods for manufacturing p-type MOSFET with graded embedded silicon-germanium source-drain and/or extension
US20060003154A1 (en) * 2004-06-30 2006-01-05 Snowden Hue S Extruded thermoplastic articles with enhanced surface segregation of internal melt additive
US7217949B2 (en) 2004-07-01 2007-05-15 International Business Machines Corporation Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
US6991998B2 (en) * 2004-07-02 2006-01-31 International Business Machines Corporation Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer
US7384829B2 (en) * 2004-07-23 2008-06-10 International Business Machines Corporation Patterned strained semiconductor substrate and device
US7217626B2 (en) * 2004-07-26 2007-05-15 Texas Instruments Incorporated Transistor fabrication methods using dual sidewall spacers
US7012028B2 (en) * 2004-07-26 2006-03-14 Texas Instruments Incorporated Transistor fabrication methods using reduced width sidewall spacers
US7442976B2 (en) * 2004-09-01 2008-10-28 Micron Technology, Inc. DRAM cells with vertical transistors
US7312146B2 (en) * 2004-09-21 2007-12-25 Applied Materials, Inc. Semiconductor device interconnect fabricating techniques
US7129127B2 (en) * 2004-09-24 2006-10-31 Texas Instruments Incorporated Integration scheme to improve NMOS with poly cap while mitigating PMOS degradation
US7172936B2 (en) * 2004-09-24 2007-02-06 Texas Instruments Incorporated Method to selectively strain NMOS devices using a cap poly layer
US7307019B2 (en) 2004-09-29 2007-12-11 Tokyo Electron Limited Method for supercritical carbon dioxide processing of fluoro-carbon films
US7129177B2 (en) * 2004-10-29 2006-10-31 Hitachi Global Storage Technologies Netherlands B.V. Write head fabrication by inverting order of process steps
US7172973B1 (en) * 2004-11-02 2007-02-06 National Semiconductor Corporation System and method for selectively modifying a wet etch rate in a large area
US7491036B2 (en) 2004-11-12 2009-02-17 Tokyo Electron Limited Method and system for cooling a pump
US7193254B2 (en) * 2004-11-30 2007-03-20 International Business Machines Corporation Structure and method of applying stresses to PFET and NFET transistor channels for improved performance
US7238565B2 (en) 2004-12-08 2007-07-03 International Business Machines Corporation Methodology for recovery of hot carrier induced degradation in bipolar devices
US7262087B2 (en) * 2004-12-14 2007-08-28 International Business Machines Corporation Dual stressed SOI substrates
US7173312B2 (en) * 2004-12-15 2007-02-06 International Business Machines Corporation Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification
US6972429B1 (en) * 2004-12-16 2005-12-06 Macronix International Co, Ltd. Chalcogenide random access memory and method of fabricating the same
US7274084B2 (en) * 2005-01-12 2007-09-25 International Business Machines Corporation Enhanced PFET using shear stress
US20060160317A1 (en) * 2005-01-18 2006-07-20 International Business Machines Corporation Structure and method to enhance stress in a channel of cmos devices using a thin gate
US7432553B2 (en) * 2005-01-19 2008-10-07 International Business Machines Corporation Structure and method to optimize strain in CMOSFETs
US7220626B2 (en) * 2005-01-28 2007-05-22 International Business Machines Corporation Structure and method for manufacturing planar strained Si/SiGe substrate with multiple orientations and different stress levels
US7256081B2 (en) * 2005-02-01 2007-08-14 International Business Machines Corporation Structure and method to induce strain in a semiconductor device channel with stressed film under the gate
US7521804B2 (en) 2005-02-03 2009-04-21 Samsung Electronics Co., Ltd. Semiconductor device preventing electrical short and method of manufacturing the same
US7224033B2 (en) * 2005-02-15 2007-05-29 International Business Machines Corporation Structure and method for manufacturing strained FINFET
US7291565B2 (en) 2005-02-15 2007-11-06 Tokyo Electron Limited Method and system for treating a substrate with a high pressure fluid using fluorosilicic acid
US7550075B2 (en) 2005-03-23 2009-06-23 Tokyo Electron Ltd. Removal of contaminants from a fluid
US7399708B2 (en) 2005-03-30 2008-07-15 Tokyo Electron Limited Method of treating a composite spin-on glass/anti-reflective material prior to cleaning
US7442636B2 (en) 2005-03-30 2008-10-28 Tokyo Electron Limited Method of inhibiting copper corrosion during supercritical CO2 cleaning
US7545004B2 (en) * 2005-04-12 2009-06-09 International Business Machines Corporation Method and structure for forming strained devices
TWI261462B (en) * 2005-04-21 2006-09-01 Optoma Corp Optical projection apparatus
US7789971B2 (en) 2005-05-13 2010-09-07 Tokyo Electron Limited Treatment of substrate using functionalizing agent in supercritical carbon dioxide
US7544577B2 (en) * 2005-08-26 2009-06-09 International Business Machines Corporation Mobility enhancement in SiGe heterojunction bipolar transistors
US7202513B1 (en) * 2005-09-29 2007-04-10 International Business Machines Corporation Stress engineering using dual pad nitride with selective SOI device architecture
US20070096170A1 (en) * 2005-11-02 2007-05-03 International Business Machines Corporation Low modulus spacers for channel stress enhancement
US20070099360A1 (en) * 2005-11-03 2007-05-03 International Business Machines Corporation Integrated circuits having strained channel field effect transistors and methods of making
US7655511B2 (en) 2005-11-03 2010-02-02 International Business Machines Corporation Gate electrode stress control for finFET performance enhancement
US7268080B2 (en) * 2005-11-09 2007-09-11 Infineon Technologies Ag Method for printing contacts on a substrate
US7785950B2 (en) * 2005-11-10 2010-08-31 International Business Machines Corporation Dual stress memory technique method and related structure
US7709317B2 (en) * 2005-11-14 2010-05-04 International Business Machines Corporation Method to increase strain enhancement with spacerless FET and dual liner process
US7348638B2 (en) * 2005-11-14 2008-03-25 International Business Machines Corporation Rotational shear stress for charge carrier mobility modification
DE102005056364B3 (de) * 2005-11-25 2007-08-16 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Bipolarer Trägerwafer und mobile, bipolare, elektrostatische Waferanordnung
US7564081B2 (en) * 2005-11-30 2009-07-21 International Business Machines Corporation finFET structure with multiply stressed gate electrode
US7776695B2 (en) * 2006-01-09 2010-08-17 International Business Machines Corporation Semiconductor device structure having low and high performance devices of same conductive type on same substrate
US7863197B2 (en) * 2006-01-09 2011-01-04 International Business Machines Corporation Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification
US7635620B2 (en) * 2006-01-10 2009-12-22 International Business Machines Corporation Semiconductor device structure having enhanced performance FET device
US20070158743A1 (en) * 2006-01-11 2007-07-12 International Business Machines Corporation Thin silicon single diffusion field effect transistor for enhanced drive performance with stress film liners
JP2007214268A (ja) * 2006-02-08 2007-08-23 Seiko Instruments Inc 半導体装置の製造方法
US7691698B2 (en) 2006-02-21 2010-04-06 International Business Machines Corporation Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain
US8461009B2 (en) * 2006-02-28 2013-06-11 International Business Machines Corporation Spacer and process to enhance the strain in the channel with stress liner
US7476933B2 (en) 2006-03-02 2009-01-13 Micron Technology, Inc. Vertical gated access transistor
KR100703984B1 (ko) * 2006-03-22 2007-04-09 삼성전자주식회사 반도체 집적 회로 장치의 제조 방법 및 그 구조
US7608489B2 (en) * 2006-04-28 2009-10-27 International Business Machines Corporation High performance stress-enhance MOSFET and method of manufacture
US7615418B2 (en) * 2006-04-28 2009-11-10 International Business Machines Corporation High performance stress-enhance MOSFET and method of manufacture
US7521307B2 (en) * 2006-04-28 2009-04-21 International Business Machines Corporation CMOS structures and methods using self-aligned dual stressed layers
US8153502B2 (en) * 2006-05-16 2012-04-10 Micron Technology, Inc. Methods for filling trenches in a semiconductor material
US8853746B2 (en) * 2006-06-29 2014-10-07 International Business Machines Corporation CMOS devices with stressed channel regions, and methods for fabricating the same
KR100772836B1 (ko) * 2006-07-21 2007-11-01 동부일렉트로닉스 주식회사 반도체소자의 제조 방법
TWI306288B (en) * 2006-08-18 2009-02-11 Promos Technologies Inc Memory structure and method for preparing the same
TWI306303B (en) * 2006-08-23 2009-02-11 Promos Technologies Inc Method for preparing memory structure
US7790540B2 (en) 2006-08-25 2010-09-07 International Business Machines Corporation Structure and method to use low k stress liner to reduce parasitic capacitance
US7462522B2 (en) * 2006-08-30 2008-12-09 International Business Machines Corporation Method and structure for improving device performance variation in dual stress liner technology
US8754446B2 (en) * 2006-08-30 2014-06-17 International Business Machines Corporation Semiconductor structure having undercut-gate-oxide gate stack enclosed by protective barrier material
CA2671766A1 (en) * 2006-12-22 2008-07-03 Encysive Pharmaceuticals, Inc. Modulators of c3a receptor and methods of use thereof
US7772048B2 (en) * 2007-02-23 2010-08-10 Freescale Semiconductor, Inc. Forming semiconductor fins using a sacrificial fin
KR100891247B1 (ko) * 2007-05-14 2009-04-01 주식회사 하이닉스반도체 반도체 소자의 패턴 형성 방법
KR100877256B1 (ko) * 2007-05-21 2009-01-09 주식회사 동부하이텍 반도체 소자의 게이트 전극 형성 방법
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US8617069B2 (en) * 2007-06-21 2013-12-31 Abbott Diabetes Care Inc. Health monitor
US7825031B2 (en) * 2007-09-14 2010-11-02 Qimonda Ag Method of fabricating a semiconductor device
US7781332B2 (en) * 2007-09-19 2010-08-24 International Business Machines Corporation Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacer
US8481423B2 (en) 2007-09-19 2013-07-09 International Business Machines Corporation Methods to mitigate plasma damage in organosilicate dielectrics
US8115254B2 (en) 2007-09-25 2012-02-14 International Business Machines Corporation Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same
US8492846B2 (en) 2007-11-15 2013-07-23 International Business Machines Corporation Stress-generating shallow trench isolation structure having dual composition
US7910418B2 (en) * 2008-01-30 2011-03-22 International Business Machines Corporation Complementary metal gate dense interconnect and method of manufacturing
US7767583B2 (en) * 2008-03-04 2010-08-03 Varian Semiconductor Equipment Associates, Inc. Method to improve uniformity of chemical mechanical polishing planarization
JP2009295785A (ja) * 2008-06-05 2009-12-17 Toshiba Corp 半導体装置の製造方法
US8101497B2 (en) 2008-09-11 2012-01-24 Micron Technology, Inc. Self-aligned trench formation
KR20100035777A (ko) * 2008-09-29 2010-04-07 삼성전자주식회사 반도체 소자 및 그 제조 방법
US8058126B2 (en) * 2009-02-04 2011-11-15 Micron Technology, Inc. Semiconductor devices and structures including at least partially formed container capacitors and methods of forming the same
US8222154B2 (en) * 2009-02-10 2012-07-17 International Business Machines Corporation Fin and finFET formation by angled ion implantation
US8216946B2 (en) * 2009-06-23 2012-07-10 Nanya Technology Corporation Patterning method
US9018024B2 (en) * 2009-10-22 2015-04-28 International Business Machines Corporation Creating extremely thin semiconductor-on-insulator (ETSOI) having substantially uniform thickness
US8110483B2 (en) * 2009-10-22 2012-02-07 International Business Machines Corporation Forming an extremely thin semiconductor-on-insulator (ETSOI) layer
US8124427B2 (en) 2009-10-22 2012-02-28 International Business Machines Corporation Method of creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness
EP2539491B1 (de) * 2009-12-29 2014-03-05 Werner Suedes Verfahren zur herstellung eines verbundkörpers mit einer freitragenden fläche
US8598006B2 (en) * 2010-03-16 2013-12-03 International Business Machines Corporation Strain preserving ion implantation methods
US20120021577A1 (en) * 2010-07-21 2012-01-26 Purtell Robert J Gate trench conductor fill
US9304130B2 (en) * 2010-12-16 2016-04-05 International Business Machines Corporation Trenched sample assembly for detection of analytes with electromagnetic read-write heads
US8993451B2 (en) * 2011-04-15 2015-03-31 Freescale Semiconductor, Inc. Etching trenches in a substrate
US9040311B2 (en) 2011-05-03 2015-05-26 International Business Machines Corporation Calibration assembly for aide in detection of analytes with electromagnetic read-write heads
US8855957B2 (en) 2011-05-03 2014-10-07 International Business Machines Corporation Method for calibrating read sensors of electromagnetic read-write heads
CN102931064B (zh) * 2011-08-12 2015-04-29 中芯国际集成电路制造(上海)有限公司 金属栅极的形成方法
US8772183B2 (en) * 2011-10-20 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming an integrated circuit
US9111861B2 (en) 2012-02-06 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a semiconductor structure with ion-implanted conductive layer
US8822295B2 (en) * 2012-04-03 2014-09-02 International Business Machines Corporation Low extension dose implants in SRAM fabrication
US8889562B2 (en) 2012-07-23 2014-11-18 International Business Machines Corporation Double patterning method
US9435800B2 (en) 2012-09-14 2016-09-06 International Business Machines Corporation Sample assembly with an electromagnetic field to accelerate the bonding of target antigens and nanoparticles
EP2917930A4 (en) * 2012-11-08 2016-06-29 Commissariat à l'énergie atomique et aux énergies alternatives METHOD FOR PRODUCING MICROELECTRONIC DEVICES WITH PARTIAL INSULATION GAMES SHAPED UNDER ACTIVE AREAS
KR101950349B1 (ko) * 2012-12-26 2019-02-20 에스케이하이닉스 주식회사 보이드 프리 폴리실리콘 갭필 방법 및 그를 이용한 반도체장치 제조 방법
EP2782144B1 (en) * 2013-03-19 2019-05-15 IMEC vzw Method for fabricating heterojunction interdigitated back contact photovoltaic cells
US8999791B2 (en) * 2013-05-03 2015-04-07 International Business Machines Corporation Formation of semiconductor structures with variable gate lengths
FR2998090A1 (fr) * 2013-06-26 2014-05-16 Commissariat Energie Atomique Procede de structuration de surface par modification locale de selectivite a la gravure
US20150001631A1 (en) * 2013-06-28 2015-01-01 Qualcomm Incorporated Cmos technology integration
JP6228873B2 (ja) * 2014-03-19 2017-11-08 株式会社日立製作所 半導体光素子の製造方法
CN105097537B (zh) * 2014-05-12 2019-09-27 中芯国际集成电路制造(上海)有限公司 鳍式场效应管的形成方法
CN105502277A (zh) * 2014-09-24 2016-04-20 中芯国际集成电路制造(上海)有限公司 一种mems麦克风及其制作方法和电子装置
US9997592B2 (en) * 2015-12-01 2018-06-12 Micron Technology, Inc. Capacitor, array of capacitors, and device comprising an electrode
US9934982B2 (en) * 2015-12-21 2018-04-03 Varian Semiconductor Equipment Associates, Inc. Etch rate modulation through ion implantation
CN106024893B (zh) * 2016-05-30 2019-03-19 上海华力微电子有限公司 高k金属栅器件及其制备方法
EP3252873B1 (en) * 2016-06-02 2019-07-24 TE Connectivity Germany GmbH Lubricated contact element and method for production thereof
CN111725138B (zh) * 2019-03-22 2023-05-02 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
CN111912880B (zh) * 2020-07-15 2022-04-15 中国核动力研究设计院 一种窄矩形通道全场瞬态空泡份额测量系统及方法
US11189357B1 (en) * 2020-08-10 2021-11-30 Nanya Technology Corporation Programmable memory device
US11784229B2 (en) * 2020-10-16 2023-10-10 Applied Materials, Inc. Profile shaping for control gate recesses
CN114765127B (zh) * 2021-01-15 2024-12-24 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
CN112928019B (zh) * 2021-01-25 2024-06-25 杰华特微电子股份有限公司 用于半导体器件的漂移区的制造方法

Family Cites Families (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4124933A (en) 1974-05-21 1978-11-14 U.S. Philips Corporation Methods of manufacturing semiconductor devices
JPS52128066A (en) 1976-04-20 1977-10-27 Matsushita Electronics Corp Manufacture of semiconductor device
SE7800261L (sv) 1977-02-28 1978-08-29 Rca Corp Sett att tillverka en halvledaranordning
US4093503A (en) 1977-03-07 1978-06-06 International Business Machines Corporation Method for fabricating ultra-narrow metallic lines
CA1129118A (en) 1978-07-19 1982-08-03 Tetsushi Sakai Semiconductor devices and method of manufacturing the same
US4343675A (en) 1980-09-30 1982-08-10 The United States Of America As Represented By The United States Department Of Energy Method of manufacturing hollow members having uniform wall thickness through use of ablation
US4438556A (en) 1981-01-12 1984-03-27 Tokyo Shibaura Denki Kabushiki Kaisha Method of forming doped polycrystalline silicon pattern by selective implantation and plasma etching of undoped regions
JPS5893343A (ja) 1981-11-30 1983-06-03 Toshiba Corp 半導体集積回路の分離領域形成方法
US4450041A (en) * 1982-06-21 1984-05-22 The United States Of America As Represented By The Secretary Of The Navy Chemical etching of transformed structures
GB2131748B (en) 1982-12-15 1986-05-21 Secr Defence Silicon etch process
NL8301262A (nl) 1983-04-11 1984-11-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij met behulp van ionenimplantatie patronen worden aangebracht in een laag siliciumnitride.
JPS60121765A (ja) 1983-12-06 1985-06-29 Toshiba Corp Ｍｉｓ型半導体装置の製造方法
JPS60128622A (ja) 1983-12-16 1985-07-09 Hitachi Ltd エツチング法
JPS60176265A (ja) 1984-02-22 1985-09-10 Nec Corp 半導体記憶装置
US4601778A (en) 1985-02-25 1986-07-22 Motorola, Inc. Maskless etching of polysilicon
US4571817A (en) 1985-03-15 1986-02-25 Motorola, Inc. Method of making closely spaced contacts to PN-junction using stacked polysilicon layers, differential etching and ion implantations
JPS6229160A (ja) 1985-07-31 1987-02-07 Hitachi Ltd 半導体装置の製造方法
US4952446A (en) 1986-02-10 1990-08-28 Cornell Research Foundation, Inc. Ultra-thin semiconductor membranes
JPS6328067A (ja) 1986-07-22 1988-02-05 Sony Corp 半導体装置の製造方法
DE3809218C2 (de) 1987-03-20 1994-09-01 Mitsubishi Electric Corp Halbleitereinrichtung mit einem Graben und Verfahren zum Herstellen einer solchen Halbleitereinrichtung
NL8800157A (nl) 1988-01-25 1989-08-16 Philips Nv Halfgeleiderinrichting en werkwijze ter vervaardiging daarvan.
US5136344A (en) * 1988-11-02 1992-08-04 Universal Energy Systems, Inc. High energy ion implanted silicon on insulator structure
GB2230134A (en) 1989-04-05 1990-10-10 Philips Nv A method of manufacturing a semiconductor device
US5224826A (en) 1989-07-26 1993-07-06 Massachusetts Institute Of Technology Piezoelectric helicopter blade flap actuator
US5092957A (en) 1989-11-24 1992-03-03 The United States Of America As Represented By The United States Department Of Energy Carrier-lifetime-controlled selective etching process for semiconductors using photochemical etching
US5026437A (en) 1990-01-22 1991-06-25 Tencor Instruments Cantilevered microtip manufacturing by ion implantation and etching
JP2619101B2 (ja) 1990-03-07 1997-06-11 三菱電機株式会社 半導体装置の製造方法
CN1018844B (zh) 1990-06-02 1992-10-28 中国科学院兰州化学物理研究所 防锈干膜润滑剂
JPH0445584A (ja) 1990-06-13 1992-02-14 Casio Comput Co Ltd 相転移型メモリ素子およびその製造方法
US5236547A (en) 1990-09-25 1993-08-17 Kabushiki Kaisha Toshiba Method of forming a pattern in semiconductor device manufacturing process
US5358908A (en) 1992-02-14 1994-10-25 Micron Technology, Inc. Method of creating sharp points and other features on the surface of a semiconductor substrate
JP2910382B2 (ja) 1992-03-09 1999-06-23 日本電気株式会社 半導体装置の製造方法
US5244826A (en) 1992-04-16 1993-09-14 Micron Technology, Inc. Method of forming an array of finned memory cell capacitors on a semiconductor substrate
EP0567815B1 (de) 1992-04-29 1998-07-15 Siemens Aktiengesellschaft Verfahren zur Herstellung eines Kontaktlochs zu einem dotierten Bereich
US5401851A (en) 1992-06-03 1995-03-28 Eli Lilly And Company Angiotensin II antagonists
JPH0637275A (ja) 1992-07-13 1994-02-10 Toshiba Corp 半導体記憶装置及びその製造方法
US5431777A (en) 1992-09-17 1995-07-11 International Business Machines Corporation Methods and compositions for the selective etching of silicon
US5448011A (en) 1993-04-08 1995-09-05 Erico International Corporation Low voltage mounting plate and method of installation
DE4337355C2 (de) 1993-11-02 1997-08-21 Siemens Ag Verfahren zur Herstellung eines Kontaktlochs zu einem dotierten Bereich
JP3601847B2 (ja) 1994-03-30 2004-12-15 沖電気工業株式会社 キャパシタ絶縁膜の形成方法、半導体記憶装置の形成方法
US5484740A (en) 1994-06-06 1996-01-16 Motorola, Inc. Method of manufacturing a III-V semiconductor gate structure
DE19530944A1 (de) 1994-10-07 1996-04-11 At & T Corp Mikrobearbeitung von Silizium
US5600174A (en) 1994-10-11 1997-02-04 The Board Of Trustees Of The Leeland Stanford Junior University Suspended single crystal silicon structures and method of making same
US5488011A (en) 1994-11-08 1996-01-30 Micron Technology, Inc. Method of forming contact areas between vertical conductors
JPH08279612A (ja) 1995-04-07 1996-10-22 Sony Corp イオン注入方法
US5580811A (en) 1995-05-03 1996-12-03 Hyundai Electronics Industries Co., Ltd. Method for the fabrication of a semiconductor memory device having a capacitor
US5599736A (en) 1995-06-28 1997-02-04 Vanguard International Semiconductor Corporation Fabrication method for polysilicon contact plugs
DE19527023C1 (de) 1995-07-24 1997-02-27 Siemens Ag Verfahren zur Herstellung eines Kondensators in einer Halbleiteranordnung
US5661064A (en) 1995-11-13 1997-08-26 Micron Technology, Inc. Method of forming a capacitor having container members
US5817580A (en) 1996-02-08 1998-10-06 Micron Technology, Inc. Method of etching silicon dioxide
US6309975B1 (en) * 1997-03-14 2001-10-30 Micron Technology, Inc. Methods of making implanted structures

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US20020182816A1 (en) 2002-12-05
KR100485995B1 (ko) 2005-05-03
JP2001517364A (ja) 2001-10-02
WO1998040909A3 (en) 1999-06-17
US6309975B1 (en) 2001-10-30
TW419742B (en) 2001-01-21
JP2004072122A (ja) 2004-03-04
KR100531001B1 (ko) 2005-11-29
KR20000076261A (ko) 2000-12-26
US20020001960A1 (en) 2002-01-03
US6596648B2 (en) 2003-07-22
EP0968526A2 (en) 2000-01-05
KR20050004896A (ko) 2005-01-12
US20020182872A1 (en) 2002-12-05
WO1998040909A2 (en) 1998-09-17
AU6555198A (en) 1998-09-29
US6596642B2 (en) 2003-07-22
US20020187648A1 (en) 2002-12-12
US6599840B2 (en) 2003-07-29
US6461967B2 (en) 2002-10-08
US6261964B1 (en) 2001-07-17

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