JP2017224837A - 半導体素子の製造方法 - Google Patents
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Abstract
Description
本発明は、酸素含有半導体ウェハの処理方法に関する。
本発明は、半導体素子の形成に役立ち、ウェハの表面付近の領域内において酸素析出物を防ぎ、好ましくは上記表面付近の領域に向かい合うウェハ領域内に高濃度の酸素析出物を有するゾーンが形成される、酸素含有ウェハの処理方法を提示することを目的としている。
本発明の典型的な実施形態について、図面を参照しながらより詳細に説明する。
これらの図では、別段の記載がない限り、同一の参照符号は、同一の意味を有する同一のウェハ領域または素子領域を示している。
チョクラルスキー法に従って形成されていると共に酸素析出物の低い半導体ゾーン(103)を有する半導体基板(100')を備えた半導体基材と、
上記素子がオフ状態において駆動された際に逆電圧に耐え得るように設計されており、且つ、少なくとも部分的には、酸素析出物の低い上記半導体ゾーン(103)内に配置されており、且つ、水素誘起ドナーによって形成されたn型基本ドーピングを有している、素子ゾーン(23;32)とを有している、垂直パワー半導体素子としてもよい。
上記半導体基材は、上記半導体基板に付着されたエピタキシャル層(200)を有しており、上記逆電圧に耐え得る上記ゾーンは、部分的には上記エピタキシャル層(200)内に配置されている、半導体素子としてもよい。
上記逆電圧に耐え得る上記ゾーンを形成するドリフトゾーン(23)を有するMOSFETまたはIGBTとして構成されている、半導体素子としてもよい。
上記逆電圧に耐え得る上記ゾーンを形成するn型ベースを有するサイリスタまたはダイオードとして形成されている、半導体素子としてもよい。
12 空孔
21 ソースゾーン
22 基材ゾーン
23 ドリフトゾーン
24 ドレインゾーン、エミッタゾーン
25 ソース電極
26 ドレイン電極、エミッタ電極
27 ゲート電極
28 ゲート絶縁膜
31 p型エミッタ
32 ベース
33 n型エミッタ
34 端子電極
35 端子電極
100 半導体ウェハ
100' ウェハ除去後のウェハ区域
101 半導体ウェハの前面
102 半導体ウェハの背面
103 ウェハの低析出物半導体ゾーン
103' ウェハの第1の半導体領域
104 酸素凝集体を含むウェハの半導体ゾーン
104' ウェハの第2の半導体領域
104'' 空孔濃度が高められた半導体ウェハの領域
110 トレンチ
111 除去された半導体ウェハの背面、半導体基材の背面
200 エピタキシャル層
201 エピタキシャル層の前面、半導体基材の前面
A アノード端子
D ドレイン端子
E エミッタ端子
G ゲート端子
K カソード端子
S ソース端子
Claims (5)
- 垂直パワー半導体素子の製造方法であって、
垂直パワー半導体素子は、
半導体ゾーン(103)を有する半導体基板(100')を備えた半導体基材と、
上記素子がオフ状態において駆動された際に逆電圧に耐え得るように設計されており、且つ、少なくとも部分的には、上記半導体ゾーン(103)内に配置されており、且つ、水素誘起ドナーによって形成されたn型基本ドーピングを有している、素子ゾーン(23;32)とを有している、垂直パワー半導体素子であり、
上記製造方法は、
チョクラルスキー法に従ってウェハ(100)を形成するステップであって、上記ウェハは、第1の面(101)、第1の面(101)と反対側の面の第2の面(102)、第1の面(101)に隣接する第1の半導体領域(103)、および、第2の面(102)に隣接する第2の半導体領域(104)を有する、ステップと、
第2の半導体領域(104')に空孔を形成するように上記ウェハ(100)の第2の面(102)に粒子を照射するステップと、
第2の半導体領域(104)の酸素析出物濃度が第1の半導体領域(103)の酸素析出物濃度よりも高くなるように第2の半導体領域(104)に酸素析出物を形成するように上記ウェハ(100)を第1の熱プロセスで加熱するステップと、
上記第1の半導体領域(103)に結晶欠陥を生じさせるように上記第1の面(101)を介して上記ウェハにプロトンを注入するステップと、
n型ドープされた半導体ゾーン(105)を上記第1の半導体領域(103)に生じさせるように上記プロトンおよび結晶欠陥から水素誘起ドナーを生じさせるように他の熱プロセスを実施するステップと、を含み、
上記素子ゾーン(23;32)は、少なくとも部分的には、上記n型ドープされた半導体ゾーン(105)内に配置されている、
垂直パワー半導体素子の製造方法。 - さらに、上記第1の面(101)にエピタキシャル層(200)を形成するステップを含み、
上記逆電圧に耐え得る上記素子ゾーンは、部分的には上記エピタキシャル層(200)内に配置されている、請求項1に記載の製造方法。 - 上記垂直パワー半導体素子は、上記逆電圧に耐え得る上記素子ゾーンを形成するドリフトゾーン(23)を有するMOSFETまたはIGBTである、請求項1または2に記載の製造方法。
- 上記垂直パワー半導体素子は、上記逆電圧に耐え得る上記素子ゾーンを形成するn型ベースを有するサイリスタまたはダイオードである、請求項1または2に記載の製造方法。
- さらに、上記第2の半導体領域(104)を少なくとも部分的に除去するステップを含む、請求項1または2に記載の製造方法。
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US20110042791A1 (en) | 2011-02-24 |
JP5358189B2 (ja) | 2013-12-04 |
EP1979934A1 (de) | 2008-10-15 |
EP2058846A1 (de) | 2009-05-13 |
JP2013153183A (ja) | 2013-08-08 |
ATE465510T1 (de) | 2010-05-15 |
EP1979934B1 (de) | 2010-04-21 |
JP2009524227A (ja) | 2009-06-25 |
DE502007003501D1 (de) | 2010-06-02 |
WO2007085387A1 (de) | 2007-08-02 |
JP2015122521A (ja) | 2015-07-02 |
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ATE522927T1 (de) | 2011-09-15 |
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