JP2013153183A - 酸素含有半導体ウェハの処理方法、および半導体素子 - Google Patents
酸素含有半導体ウェハの処理方法、および半導体素子 Download PDFInfo
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Abstract
【解決手段】垂直パワー半導体素子は、チョクラルスキー法に従って形成されていると共に酸素析出物の低い半導体ゾーン103を有する半導体基板100'を備えた半導体基材と、上記素子がオフ状態において駆動された際に逆電圧に耐え得るように設計されており、且つ、少なくとも部分的には、酸素析出物の低い上記半導体ゾーン103内に配置されており、且つ、水素誘起ドナーによって形成されたn型基本ドーピングを有している、素子ゾーン23とを有している。
【選択図】図5
Description
本発明は、酸素含有半導体ウェハの処理方法に関する。
本発明は、半導体素子の形成に役立ち、ウェハの表面付近の領域内において酸素析出物を防ぎ、好ましくは上記表面付近の領域に向かい合うウェハ領域内に高濃度の酸素析出物を有するゾーンが形成される、酸素含有ウェハの処理方法を提示することを目的としている。
本発明の典型的な実施形態について、図面を参照しながらより詳細に説明する。
これらの図では、別段の記載がない限り、同一の参照符号は、同一の意味を有する同一のウェハ領域または素子領域を示している。
12 空孔
21 ソースゾーン
22 基材ゾーン
23 ドリフトゾーン
24 ドレインゾーン、エミッタゾーン
25 ソース電極
26 ドレイン電極、エミッタ電極
27 ゲート電極
28 ゲート絶縁膜
31 p型エミッタ
32 ベース
33 n型エミッタ
34 端子電極
35 端子電極
100 半導体ウェハ
100' ウェハ除去後のウェハ区域
101 半導体ウェハの前面
102 半導体ウェハの背面
103 ウェハの低析出物半導体ゾーン
103' ウェハの第1の半導体領域
104 酸素凝集体を含むウェハの半導体ゾーン
104' ウェハの第2の半導体領域
104'' 空孔濃度が高められた半導体ウェハの領域
110 トレンチ
111 除去された半導体ウェハの背面、半導体基材の背面
200 エピタキシャル層
201 エピタキシャル層の前面、半導体基材の前面
A アノード端子
D ドレイン端子
E エミッタ端子
G ゲート端子
K カソード端子
S ソース端子
Claims (19)
- 垂直パワー半導体素子であって、
チョクラルスキー法に従って形成されていると共に酸素析出物の低い半導体ゾーン(103)を有する半導体基板(100')を備えた半導体基材と、
上記素子がオフ状態において駆動された際に逆電圧に耐え得るように設計されており、且つ、少なくとも部分的には、酸素析出物の低い上記半導体ゾーン(103)内に配置されており、且つ、水素誘起ドナーによって形成されたn型基本ドーピングを有している、素子ゾーン(23;32)とを有している、垂直パワー半導体素子。 - 上記半導体基材は、上記半導体基板に付着されたエピタキシャル層(200)を有しており、上記逆電圧に耐え得る上記ゾーンは、部分的には上記エピタキシャル層(200)内に配置されている、請求項1に記載の半導体素子。
- 上記逆電圧に耐え得る上記ゾーンを形成するドリフトゾーン(23)を有するMOSFETまたはIGBTとして構成されている、請求項1または2に記載の半導体素子。
- 上記逆電圧に耐え得る上記ゾーンを形成するn型ベースを有するサイリスタまたはダイオードとして形成されている、請求項1または2に記載の半導体素子。
- ドープされていないか、あるいは排他的に基本ドーピングのみを有しており、第1の面(101)と、当該第1の面(101)の反対側の第2の面(102)と、当該第1の面(101)に隣接する第1の半導体領域(103')と、上記第2の面(102)に隣接する第2の半導体領域(104')とを有している酸素含有半導体ウェハ(100)の処理方法であって、
上記第2の半導体領域(104')内に格子空孔が生じるように、上記ウェハ(100)の上記第2の面(102)にプロトンまたはヘリウムイオンを照射する工程を含んでいる方法。 - 上記ウェハ(100)が700℃〜1100℃の間の温度に加熱される第1の熱プロセスを行う工程をさらに含んでいる、請求項5に記載の方法。
- 上記第1の熱プロセスの長さは、上記第2の半導体領域内に酸素凝集体が形成されるように、且つ、上記第1の半導体領域内から上記第2の半導体領域へ格子空孔が拡散するように選択される、請求項6に記載の方法。
- 上記第1の熱プロセスの上記長さは、1時間〜20時間の間である、請求項7に記載の方法。
- 上記ウェハは、上記熱プロセス中に、まず、790℃〜810℃の間の温度に、10時間よりも短い第1の長さの時間加熱され、次に、985℃〜1015℃の間の温度に、10時間よりも長い第2の長さの時間加熱される、請求項6〜8のいずれか1項に記載の方法。
- 上記ウェハの厚さは、400μm〜1000μmの間であり、照射エネルギーは、70KeV〜10MeVの間である、請求項5〜9のいずれか1項に記載の方法。
- プロトンの注入線量は、1・1013cm-2〜1・1015cm-2の間である、請求項5〜10のいずれか1項に記載の方法。
- 上記ウェハ(100)の上記第2の面(102)の照射前に、第2の熱プロセスを行う工程を含んでおり、
上記第2の熱プロセスでは、上記ウェハ(100)が1000℃を超える温度に加熱され、また、少なくとも上記第1の面(100)が湿潤雰囲気および/または酸化性雰囲気に曝露される、請求項5〜9のいずれか1項に記載の方法。 - 上記第1の面および第2の面は、上記熱プロセス中に湿潤雰囲気および/または酸化性雰囲気に曝露される、請求項12に記載の方法。
- 上記第1の熱プロセスの後または前に、第3の熱プロセスを行うさらなる工程を含んでおり、
上記第3の熱プロセスでは、少なくとも上記第1の半導体ゾーン(103)が、上記ウェハの上記第1の面(101)を介して酸素原子が上記第1の半導体ゾーン(103)から外部拡散するように加熱される、請求項6〜9のいずれか1項に記載の方法。 - 上記第1の面および第2の面(101、102)のうち少なくともいずれか1つを介して上記ウェハ(100)にプロトンを照射することによって、上記第1の半導体ゾーン内に結晶欠陥を生じさせる工程と、
水素誘起ドナーを有するフィールドストップゾーン(29)が生じるように、上記ウェハ(100)が350℃〜550℃の間の温度に加熱される熱プロセスを行う工程とによって、
上記ウェハ内にnドープされたフィールドストップゾーン(29)を形成する工程を含んでいる、請求項5〜14のいずれか1項に記載の方法。 - 上記ウェハの上記第2の面(102)の上記照射は、それぞれ異なる照射エネルギーを用いた少なくとも2つの照射工程を含んでいる、請求項5〜14のいずれか1項に記載の方法。
- 上記熱プロセスは、時間的に分離した少なくとも2つの熱工程を含んでおり、
上記熱工程では、それぞれの場合において、上記ウェハ(100)が加熱され、
上記熱工程の少なくとも1つは、時間的に、2つの照射工程の間において行われる、請求項16に記載の方法。 - 第1の面および第2の面をそれぞれ有する第1の半導体ウェハおよび第2の半導体ウェハを設ける工程と、
上記2つの各ウェハに対して、上記2つの半導体ウェハのそれぞれに対して請求項7〜17のいずれか1項に記載の方法を行って、上記ウェハの上記第1の面に隣接する低析出物ゾーンを形成する工程と、
上記第1の半導体ウェハの第1の面と上記第2の半導体ウェハの第1の面とが互いに面するように、且つ、上記第1の半導体ウェハの第1の面と上記第2の半導体ウェハの第1の面との間に絶縁層が存在するように、上記第1の半導体ウェハと上記第2の半導体ウェハとを接続する工程とを含んでいる、SOI基板の形成方法。 - 第1の面(101)と、当該第1の面の反対側の第2の面(102)と、当該第1の面(101)に隣接していると共に酸素析出物の低い第1の半導体ゾーン(103)とを有する半導体ウェハ内に、nドープされたゾーンを形成する方法を含み、
上記nドープされたゾーンを形成する方法は、
上記第1の面(101)を介して上記ウェハにプロトンを注入することによって、上記第1の半導体ゾーン(103)内に結晶欠陥を生じさせる工程であって、プロトンが、注入エネルギーに応じて、上記半導体ウェハ内の末端域領域内に注入される工程と、
さらなる熱プロセスを行う工程とを含んでおり、当該さらなる熱プロセスでは、
上記ウェハ(100)が、水素誘起ドナーを有するn型ドープされた半導体ゾーンが生じるように、少なくとも上記第1の面(101)の上記領域内において400℃〜570℃の温度に加熱され、
プロトンが上記末端域領域から上記第1の面(101)の方向に拡散するように、且つ、上記n型ドープされた半導体ゾーン(105)が、上記末端域領域と上記第1の面(101)との距離の少なくとも60%超または80%を超えるドーピングの領域と、上記プロトン注入によって形成された少なくともほぼ均質なドーピングとを有するように、且つ、均質なドーピングの上記領域内における最高ドーピング濃度と最低ドーピング濃度との割合が最大3であるように、長さおよび温度が選択される、請求項7〜17のいずれか1項に記載の方法。
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- 2007-01-19 DE DE502007003501T patent/DE502007003501D1/de active Active
- 2007-01-19 EP EP07702904A patent/EP1979934B1/de not_active Not-in-force
- 2007-01-19 US US12/161,472 patent/US20110042791A1/en not_active Abandoned
- 2007-01-19 CN CN201410026471.XA patent/CN103943672B/zh not_active Expired - Fee Related
- 2007-01-19 AT AT07702904T patent/ATE465510T1/de active
- 2007-01-19 EP EP09150636A patent/EP2058846B1/de not_active Not-in-force
- 2007-01-19 WO PCT/EP2007/000475 patent/WO2007085387A1/de active Application Filing
- 2007-01-19 AT AT09150636T patent/ATE522927T1/de active
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2013
- 2013-03-06 JP JP2013044811A patent/JP2013153183A/ja active Pending
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2015
- 2015-01-26 JP JP2015012799A patent/JP2015122521A/ja active Pending
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Cited By (1)
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DE112021000055T5 (de) | 2020-02-18 | 2022-06-30 | Fuji Electric Co., Ltd. | Halbleitervorrichtung |
Also Published As
Publication number | Publication date |
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ATE465510T1 (de) | 2010-05-15 |
CN103943672B (zh) | 2020-06-16 |
WO2007085387A1 (de) | 2007-08-02 |
EP2058846A1 (de) | 2009-05-13 |
EP1979934A1 (de) | 2008-10-15 |
EP1979934B1 (de) | 2010-04-21 |
JP2015122521A (ja) | 2015-07-02 |
JP2009524227A (ja) | 2009-06-25 |
JP5358189B2 (ja) | 2013-12-04 |
ATE522927T1 (de) | 2011-09-15 |
JP2017224837A (ja) | 2017-12-21 |
CN103943672A (zh) | 2014-07-23 |
EP2058846B1 (de) | 2011-08-31 |
US20110042791A1 (en) | 2011-02-24 |
DE502007003501D1 (de) | 2010-06-02 |
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