JP2016131245A - 多層基板 - Google Patents

多層基板 Download PDF

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Publication number
JP2016131245A
JP2016131245A JP2016004538A JP2016004538A JP2016131245A JP 2016131245 A JP2016131245 A JP 2016131245A JP 2016004538 A JP2016004538 A JP 2016004538A JP 2016004538 A JP2016004538 A JP 2016004538A JP 2016131245 A JP2016131245 A JP 2016131245A
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Japan
Prior art keywords
semiconductor substrate
electrodes
conductive particles
substrate
electrode
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Pending
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JP2016004538A
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English (en)
Japanese (ja)
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JP2016131245A5 (https=
Inventor
恭志 阿久津
Yasushi Akutsu
恭志 阿久津
朋之 石松
Tomoyuki Ishimatsu
朋之 石松
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Dexerials Corp
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Dexerials Corp
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Publication of JP2016131245A publication Critical patent/JP2016131245A/ja
Publication of JP2016131245A5 publication Critical patent/JP2016131245A5/ja
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • HELECTRICITY
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    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01204Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates
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    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01212Manufacture or treatment of bump connectors, dummy bumps or thermal bumps at a different location than on the final device, e.g. forming as prepeg
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    • H10W72/221Structures or relative sizes
    • H10W72/222Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
    • H10W72/223Multilayered bumps, e.g. a coating on top and side surfaces of a bump core characterised by the structure of the outermost layers, e.g. multilayered coatings
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    • H10W99/00Subject matter not provided for in other groups of this subclass

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  • Non-Insulated Conductors (AREA)
  • Wire Bonding (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Laminated Bodies (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Adhesive Tapes (AREA)
  • Combinations Of Printed Boards (AREA)
JP2016004538A 2015-01-13 2016-01-13 多層基板 Pending JP2016131245A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015004595 2015-01-13
JP2015004595 2015-01-13

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2020161099A Division JP7207382B2 (ja) 2015-01-13 2020-09-25 多層基板

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JP2016131245A true JP2016131245A (ja) 2016-07-21
JP2016131245A5 JP2016131245A5 (https=) 2019-02-21

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ID=56405859

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JP2016004538A Pending JP2016131245A (ja) 2015-01-13 2016-01-13 多層基板
JP2020161099A Active JP7207382B2 (ja) 2015-01-13 2020-09-25 多層基板

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Country Status (6)

Country Link
US (1) US10199358B2 (https=)
JP (2) JP2016131245A (https=)
KR (1) KR101974763B1 (https=)
CN (2) CN107112314B (https=)
TW (3) TWI709221B (https=)
WO (1) WO2016114318A1 (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018185175A (ja) * 2017-04-24 2018-11-22 デクセリアルズ株式会社 検査冶具の製造方法
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