WO2013089199A1 - 異方導電性フィルム付き半導体チップ、異方導電性フィルム付き半導体ウェハ、及び半導体装置 - Google Patents
異方導電性フィルム付き半導体チップ、異方導電性フィルム付き半導体ウェハ、及び半導体装置 Download PDFInfo
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
- H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
Definitions
- the present invention relates to a semiconductor chip with an anisotropic conductive film, in which an anisotropic conductive film is previously provided in a semiconductor chip for electrically connecting electrodes on a circuit board facing the electrodes of the semiconductor chip, and a circuit to face
- the semiconductor wafer for manufacturing a semiconductor chip used for electrically connecting the electrodes of the substrate, and the electrodes on the circuit board facing the electrodes of the semiconductor chip are electrically connected by an adhesive.
- the present invention relates to a semiconductor device.
- An anisotropic conductive film is a film in which conductive particles are dispersed in an insulating adhesive, and is used for connection between a semiconductor chip electrode and a circuit board electrode facing the semiconductor chip electrode.
- Anisotropic conductive films are widely used mainly in the field of flat panel displays, for example, for connecting an organic substrate and a semiconductor chip and a glass substrate and a semiconductor chip.
- connection part can be inspected before connection, the number of conductive particles contributing to the connection can be predicted, and the alignment mark at the time of connection
- the semiconductor chip with an anisotropic conductive film which is excellent in recognizability.
- Another object of the present invention is to provide a semiconductor wafer with an anisotropic conductive film capable of inspecting a connection part before dicing, and conductive particles that contribute to connection by dicing the semiconductor wafer with an anisotropic conductive film. It is possible to provide a method for manufacturing a semiconductor chip with an anisotropic conductive film that can predict the number and is excellent in recognition of an alignment mark at the time of connection.
- the present inventors have found that the above problems can be solved by using a semiconductor chip or wafer with an anisotropic conductive film having a specific structure.
- the present invention has been completed. That is, the present invention is as follows.
- the semiconductor chip with an anisotropic conductive film which is present.
- the height of the insulating resin component on the surface side of the average height of the circuit electrode is 1.0 to 2.0 times the average diameter of the conductive particles.
- the anisotropic conductive film has an insulating adhesive layer and a conductive particle layer covering the circuit electrode, and the conductive particle layer is substantially flat in the insulating resin.
- the conductive particles are substantially spherical particles having an average diameter of 2 to 50 ⁇ m, and are metal particles coated with plastic particles, metal particles, alloy particles, and metal particles or alloy particles.
- the anisotropic conductive film layer has an insulating adhesive layer and a conductive particle layer, and the conductive particle layer is one layer in which the conductive particles are substantially planar in an insulating resin.
- [15] including a step of aligning and thermocompression bonding the circuit electrode of the semiconductor chip with the anisotropic conductive film according to any one of [1] to [9] with a circuit board having a corresponding connection electrode.
- a method for manufacturing a semiconductor device including a step of aligning and thermocompression bonding the circuit electrode of the semiconductor chip with the anisotropic conductive film according to any one of [1] to [9] with a circuit board having a corresponding connection electrode.
- a semiconductor wafer with an anisotropic conductive film having a semiconductor wafer having a plurality of circuit electrodes on one side and an anisotropic conductive film covering the circuit electrodes, the anisotropic conductive film having an insulating property 60% or more of the total number of conductive particles contained in the anisotropic conductive film, including a resin component and conductive particles, is closer to the surface side of the anisotropic conductive film than the average height of the circuit electrode.
- the semiconductor wafer with an anisotropic conductive film which is present.
- the height of the insulating resin component on the surface side of the average height of the circuit electrode is 1.0 to 2.0 times the average diameter of the conductive particles.
- the anisotropic conductive film has an insulating adhesive layer and a conductive particle layer covering the circuit electrode, and the conductive particle layer is substantially flat in the insulating resin.
- the conductive particles are substantially spherical particles having an average diameter of 2 to 50 ⁇ m, and are metal particles coated with plastic particles, metal particles, alloy particles, and metal particles or alloy particles.
- the anisotropic conductive film layer has an insulating adhesive layer and a conductive particle layer, and the conductive particle layer is one layer in which the conductive particles are substantially planar in an insulating resin.
- a method for manufacturing a semiconductor chip with an anisotropic conductive film comprising a step of dicing the semiconductor wafer with an anisotropic conductive film according to any one of [18] to [25].
- a semiconductor device including a semiconductor chip having a plurality of circuit electrodes on one side, a circuit board having connection electrodes corresponding to the circuit electrodes, and an adhesive, the adhesive being an insulating resin and a conductive material Conductive particles that are close to the semiconductor chip in a cross-section that includes particles and is disposed between the semiconductor chip and the circuit board and that is cleaved in the thickness direction between the circuit electrodes on the semiconductor chip that has the shortest distance. And a distance between particles in the thickness direction of the conductive particles farthest from the semiconductor chip is not more than one time the average diameter of the conductive particles.
- the conductive particles are substantially spherical particles having an average diameter of 2 to 50 ⁇ m, and are metal particles coated with plastic particles, metal particles, alloy particles, and metal particles or alloy particles.
- the semiconductor chip or wafer with an anisotropic conductive film according to the present invention can be inspected before connection, can predict the number of conductive particles contributing to the connection, and at the time of connection Excellent alignment mark recognition.
- Sectional drawing which shows an example of the semiconductor chip with an anisotropically conductive film which concerns on this Embodiment.
- Sectional drawing which shows an example of the semiconductor chip with an anisotropically conductive film which concerns on this Embodiment (structure consisting of a conductive particle layer / insulating adhesive layer).
- Schematic which shows an example of the manufacturing method (method 1) of the semiconductor chip with an anisotropically conductive film which concerns on this Embodiment.
- (A) is a semiconductor chip having a plurality of circuit electrodes on one side of a laminate formed by laminating a support and an anisotropic conductive film layer in which conductive particles are unevenly distributed on the support side in the cross-sectional thickness direction. The process of laminating the circuit electrode surface is shown.
- (B) shows the process of peeling this laminated
- Schematic which shows an example of the manufacturing method (method 2) of the semiconductor chip with an anisotropically conductive film which concerns on this Embodiment.
- (A) shows the process of filling the circuit electrode surface of a semiconductor chip having a plurality of circuit electrodes on one side with an insulating adhesive.
- (B) is a conductive particle layer formed on a support in the obtained semiconductor chip with an insulating adhesive layer and having conductive particles dispersed in a substantially planar shape in an insulating resin; The process of laminating is shown.
- Schematic which shows an example of the manufacturing method (method 3) of the semiconductor chip with an anisotropically conductive film which concerns on this Embodiment.
- A shows the process of filling the circuit electrode surface of a semiconductor chip having a plurality of circuit electrodes on one side with an insulating adhesive.
- B shows the process of laminating
- Sectional drawing which shows an example of the semiconductor wafer with an anisotropically conductive film which concerns on this Embodiment.
- Sectional drawing which shows an example of the semiconductor wafer with an anisotropically conductive film which concerns on this Embodiment (structure consisting of a conductive particle layer / insulating adhesive layer).
- Schematic which shows an example of the manufacturing method (method 1) of the semiconductor wafer with an anisotropically conductive film which concerns on this Embodiment.
- (A) is a semiconductor wafer having a plurality of circuit electrodes on one side of a laminate formed by laminating a support and an anisotropic conductive film layer in which conductive particles are unevenly distributed on the support side in the cross-sectional thickness direction. The process of laminating the circuit electrode surface is shown.
- (B) shows the process of peeling this laminated
- Schematic shows an example of the manufacturing method (method 2) of the semiconductor wafer with an anisotropically conductive film which concerns on this Embodiment.
- (A) shows the process of filling the circuit electrode surface of the semiconductor wafer which has a plurality of circuit electrodes on one side with an insulating adhesive.
- (B) is a conductive particle layer formed on a support in the obtained semiconductor wafer with an insulating adhesive layer and having conductive particles dispersed in a substantially planar shape in an insulating resin; The process of laminating is shown.
- FIG. 14 is a cross-sectional view illustrating an example of a semiconductor device according to an embodiment
- the semiconductor chip with an anisotropic conductive film of the present embodiment has a semiconductor chip having a plurality of circuit electrodes on one side (at least one of the main surfaces) and an anisotropic conductive film covering the circuit electrodes (FIG. 1). reference).
- the anisotropic conductive film includes an insulating resin component and conductive particles, and the conductive particles are unevenly distributed in the cross-sectional thickness direction. Specifically, 60% or more, preferably 70% or more, more preferably 80% or more of the total number of conductive particles on the surface side of the anisotropic conductive film with respect to the average height of the circuit electrodes of the semiconductor chip. However, more preferably 90% or more is present.
- the average height of the circuit electrodes refers to the average height of each circuit electrode on the basis of the portion where the circuit electrodes are not arranged in the cross section of the semiconductor chip.
- the surface side of the anisotropic conductive film refers to a side opposite to the side in contact with the semiconductor chip in the cross section of the anisotropic conductive film. If 60% or more of the total number of conductive particles is present on the surface side of the anisotropic conductive film with respect to the average height of the circuit electrodes of the semiconductor chip, it is preferable in terms of stabilization of connection resistance.
- the insulating resin component of the anisotropic conductive film can also contain a curable resin or a curing agent.
- metal particles or particles made of plastic particles coated with a metal thin film can be used.
- metal particles for example, simple particles such as gold, silver, copper, nickel, aluminum, zinc, tin, lead, indium, palladium, or particles in which two or more of these metals are combined in a layered or inclined manner, or An alloy, solder, etc. by 2 or more types of combinations are mentioned.
- alloy particles or solder particles having a melting point of 150 ° C. or more and 500 ° C. or less it is preferable to coat the particle surface with a flux or the like in advance. By using the flux, surface oxides and the like can be removed.
- fatty acids such as abietic acid can be used.
- the plastic particles covered with a metal thin film include epoxy resin, styrene resin, silicone resin, acrylic resin, polyolefin resin, melamine resin, benzoguanamine resin, urethane resin, phenol resin, polyester resin, divinylbenzene resin, NBR,
- grains which carried out metal coating by plating etc. are illustrated to the 1 type, or 2 or more types of combination chosen from polymers, such as SBR.
- the thickness of the metal thin film is preferably in the range of 0.005 ⁇ m to 1 ⁇ m from the viewpoint of connection stability and particle cohesion. It is also possible to use particles obtained by further insulatingly coating the surface of such conductive particles, or confetti type particles having microprotrusions formed on the surface.
- spherical particles are preferably used, and in that case, particles close to a true sphere are more preferable.
- the ratio of the minor axis to the major axis is preferably 0.5 or more, more preferably 0.7 or more, and further preferably 0.9 or more.
- the maximum value of the ratio of the short axis to the long axis is 1.
- the average diameter of the conductive particles needs to be smaller than the distance between adjacent electrodes to be connected, and is preferably larger than the variation in the electrode height of the electronic component to be connected. Therefore, the average diameter of the conductive particles is preferably in the range of 2.0 ⁇ m to 50 ⁇ m, more preferably 2.5 ⁇ m to 40 ⁇ m, further preferably 3.0 ⁇ m to 35 ⁇ m, and particularly preferably 4.0 ⁇ m to 30 ⁇ m. .
- the standard deviation of the particle size distribution of the conductive particles is preferably 50% or less of the average diameter.
- the anisotropic conductive film may further contain insulating particles, fillers, softeners, curing accelerators, stabilizers, colorants, flame retardants, flow regulators, coupling agents, and the like.
- insulating particles fillers, softeners, curing accelerators, stabilizers, colorants, flame retardants, flow regulators, coupling agents, and the like.
- the maximum diameter is preferably less than the average diameter of the conductive particles.
- a coupling agent an epoxy group, a ketimine group, a vinyl group, an acrylic group, an amino group, an isocyanate group and the like-containing silane coupling agent are preferable from the viewpoint of adhesion.
- the height (thickness) of the insulating resin component on the surface side of the anisotropic conductive film on the surface side with respect to the average height of the circuit electrodes is 1.0 to 2.0 times the average diameter of the conductive particles contained.
- the ratio is preferably 1.0 to 1.5 times, more preferably 1.0 to 1.2 times.
- the average diameter of the conductive particles refers to the average of the long diameters of the conductive particles.
- the thickness is preferably 1.0 times or more the average diameter of the conductive particles. From the viewpoint of suppressing the movement of the conductive particles, it is preferably 2.0 times or less.
- the thickness is preferably 1.05 to 1.5 times the average height of the circuit electrodes. From the viewpoint of controlling the tack property of the anisotropic conductive film and controlling the conductive particle retention, the thickness is preferably 1.05 times or more the average height of the circuit electrode, From the viewpoint of suppressing the movement of the conductive particles, it is preferably 1.5 times or less.
- the anisotropic conductive film is preferably composed of an insulating adhesive layer and a conductive particle layer in which conductive particles are dispersed and arranged in a substantially planar shape in an insulating resin (see FIG. 2).
- the thickness of the insulating resin in the conductive particle layer is preferably 0.4 to 2.0 times the average diameter of the conductive particles, more preferably 0.5 to 1.8 times, and still more preferably. 0.7 to 1.0 times. From the viewpoint of controlling the tack property of the conductive particle layer or controlling the conductive particle retention property, the thickness is preferably 0.4 times or more, and from the viewpoint of connection stability, 2.0 times. The following is preferable.
- the maximum protrusion length is preferably ⁇ 20 to 50 ⁇ m, which indicates the amount of the anisotropic conductive film protruding from the outer shape of the semiconductor chip.
- the thickness is preferably ⁇ 10 to 30 ⁇ m, and more preferably 0 to 20 ⁇ m. From the viewpoint of electrical and mechanical connectivity, the protrusion length is preferably ⁇ 20 ⁇ m or more. On the other hand, from the viewpoint of handling property and resin protrusion at the time of connection, it is preferably 50 ⁇ m or less.
- the total number of conductive particles in the anisotropic conductive film of the present embodiment is partially exposed from the surface of the anisotropic conductive film.
- the number of exposed particles is more preferably 80% or more, and still more preferably 90% or more.
- the conductive particles are exposed from the surface of the anisotropic conductive film from the viewpoint of connectivity with the opposing electrode.
- the exposure height that indicates the degree of exposure per exposed particle is preferably less than 50% of the average diameter of the particle. When the exposed height is less than 50%, it is preferable in that the loss of conductive particles hardly occurs.
- the insulating adhesive used in the present embodiment can contain one or more kinds of resins selected from the group consisting of thermosetting resins, thermoplastic resins, photocurable resins, and electron beam curable resins.
- these resins include epoxy resin, oxetane resin, phenol resin, silicone resin, urethane resin, acrylic resin, polyimide resin, phenoxy resin, polyvinyl butyral resin, SBR, SBS, NBR, polyethylene terephthalate resin, polyamide resin, polystyrene
- examples thereof include resins, polyisobutylene resins, alkylphenol resins, styrene butadiene resins, carboxyl-modified nitrile resins, and modified resins thereof.
- the insulating adhesive preferably contains an epoxy resin or an oxetane resin.
- epoxy resin used here examples include bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, tetramethylene bisphenol A type epoxy resin, biphenyl type epoxy resin, naphthalene type epoxy resin, and resorcinol type epoxy.
- Resin fluorene type epoxy resin, phenol novolak type epoxy resin, cresol novolak type epoxy resin, bisphenol A type novolak type epoxy resin, aliphatic ether type epoxy resin, glycidyl ether type epoxy resin, glycidyl ether ester type epoxy resin, glycidyl ester Type epoxy resin, glycidylamine type epoxy resin, alicyclic epoxy resin, etc., and these epoxy resins may be halogenated or hydrogenated. It may be, also, urethane-modified, rubber-modified, may be a modified epoxy resins such as silicone-modified.
- thermoplastic resin preferably has a molecular weight of 5000 to 1000000, more preferably 8000 to 80000, and still more preferably 9000 to 60000.
- the content of the thermoplastic resin component is preferably 5 to 80 parts by mass, more preferably 10 to 70 parts by mass, and more preferably 20 to 60 parts by mass with respect to all the resin components in the anisotropic conductive film. More preferably, it is a part. If this content is 5 mass parts or more, it is preferable from a viewpoint of film forming property, and if it is 80 mass parts or less, it is preferable from a viewpoint of connection stability.
- curing agent in the case of using an epoxy resin and an oxetane resin, a latent hardening
- the latent curing agent it is preferable to use a microcapsule type latent curing agent, a thermal cationic curing agent, or the like.
- the microcapsule-type curing agent is a material whose surface is stabilized with a resin film, etc., and the resin film is destroyed by heat and load during connection, and the curing agent diffuses outside the microcapsule, resulting in an epoxy resin or oxetane. Reacts with resin.
- a latent curing agent obtained by microencapsulating an adduct-type curing agent such as an amine adduct or an imidazole adduct is preferable in terms of excellent balance between stability and curability.
- the microcapsule type curing agent is used in an amount of 2 to 100 parts by mass with respect to 100 parts by mass of the epoxy resin.
- an aromatic sulfonium salt type curing agent is preferable.
- the thermal cationic curing agent is preferable because it can be uniformly blended in the curable resin and can be cured in a catalyst type, so that it can be cured at a low temperature in a short time and has good solvent stability.
- the anion of the aromatic sulfonium salt type curing agent hexafluoroantimonate, hexafluorophosphate, tetrafluoroborate, tetrakispentahalogenated phenylborate and the like can be used, but tetrakispenta can be used because impurity ions can be reduced.
- Halogenated phenylborate is preferred, and tetrakispentafluorophenylborate is particularly preferred.
- conductive particles may be added to the insulating adhesive layer as long as the insulating properties are not impaired for the purpose of preventing charging.
- the average interval between adjacent conductive particles is preferably 1.0 to 20 times the average diameter of the conductive particles, and more preferably 2 to 10 times. preferable. If it is 1.0 times or more, it is preferable in that a short circuit hardly occurs. On the other hand, if it is 20 times or less, it is preferable in that it is easy to secure the number of conductive particles necessary for connection stability.
- the dispersed arrangement state on the plane where the conductive particles are distributed is preferably arranged in a substantially equilateral triangular shape.
- the conductive particles are arranged in a substantially equilateral triangle shape, the intervals between adjacent conductive particles are close to each other, the number of conductive particles located on the connection electrode is substantially constant, and the number of conductive particles in the connection portion. This is preferable because the variation in the resistance is small and the connection resistance is stabilized.
- the conductive particle layer is made of conductive particles and an insulating resin, and can also contain a curable resin or a curing agent.
- the viscosity of the insulating resin of the conductive particle layer at 100 ° C. is preferably in the range of 3000 Pa ⁇ s to 500,000 Pa ⁇ s, more preferably 5000 Pa ⁇ s to 300,000 Pa ⁇ s, and 10,000 Pa ⁇ s to 200000 Pa ⁇ s. More preferably. If the viscosity is 3000 Pa ⁇ s or more, it is preferable in that the flow of the conductive particles can be easily suppressed. On the other hand, if it is 500,000 Pa ⁇ s or less, the connection resistance value is favorable.
- the viscosity at 100 ° C. and the viscosity at 20 ° C. to 100 ° C. of the insulating resin of the conductive particle layer can be measured with a rheometer, respectively. It is preferable to prepare a sheet of the conductive particle layer from which the conductive particles are removed and measure under a temperature rising condition of 60 ° C./min.
- the insulating adhesive layer has a viscosity at 100 ° C. of preferably 100 Pa ⁇ s to 10,000 Pa ⁇ s, more preferably 200 Pa ⁇ s to 5000 Pa ⁇ s, and more preferably 300 Pa ⁇ s to 1000 Pa ⁇ s. More preferably, it is in the range.
- the viscosity at 100 ° C. of the insulating adhesive layer is preferably 100 Pa ⁇ s from the viewpoint of handling properties, and is preferably 10,000 Pa ⁇ s or less from the viewpoint of connection stability.
- the viscosity of the insulating resin of the conductive particle layer at 100 ° C. is preferably 2 to 1000 times the viscosity of the resin component of the insulating adhesive layer at 100 ° C., more preferably in the range of 5 to 500 times.
- the range of 8 times to 400 times is more preferable, and the range of 10 times to 300 times is particularly preferable. If the viscosity ratio is 2 times or more, it is preferable from the viewpoint of suppressing the flow of conductive particles at the time of connection, and on the other hand, it is preferably 1000 times or less from the viewpoint of stabilization of connection resistance.
- the insulating resin component of the conductive particle layer may be the same as the resin component of the insulating adhesive layer, but if different, the insulating resin component of the conductive particle layer in a temperature range of 20 to 100 ° C.
- the viscosity of the insulating adhesive layer is preferably higher than the viscosity of the resin component of the insulating adhesive layer, more preferably the viscosity of the insulating resin component of the conductive particle layer and the insulating adhesive layer at each temperature in the temperature range.
- the viscosity ratio of the resin component is 2 to 1000 times, more preferably the ratio is 10 to 500 times, and particularly preferably the ratio is 20 to 100 times.
- the viscosity of the insulating resin component of the conductive particle layer is the resin of the insulating adhesive layer. Preferably higher than the viscosity of the components.
- the viscosity of the insulating resin component of the conductive particle layer is higher than the viscosity of the resin component of the insulating adhesive layer from the viewpoint of suppressing the adhesion of dust onto the conductive particle layer and handling properties before connection. Is preferred. From the viewpoint of connection stability, the viscosity ratio is preferably 1000 times or less.
- Method 1 comprises the following steps: The circuit electrode surface of a semiconductor chip having a plurality of circuit electrodes on one side in a laminate formed by laminating a support and an anisotropic conductive film layer in which conductive particles are unevenly distributed on the support side in the cross-sectional thickness direction And laminating the laminated semiconductor chip together with the anisotropic conductive film layer from the support, It is a manufacturing method of the semiconductor chip with an anisotropically conductive film containing (refer FIG. 3). It is preferable from the viewpoint of connection reliability that the anisotropic conductive film layer has an insulating adhesive layer and a conductive particle layer in which the conductive particles are dispersed and arranged substantially in a plane.
- a method for forming a conductive particle layer in which conductive particles are dispersed and arranged in a substantially planar shape on a support the following method is preferably used.
- An adhesive layer is formed on a biaxially stretchable support (support film), the conductive particles are closely packed on the adhesive layer, an insulating resin varnish is applied on the conductive particles, and the conductive particles are dried.
- a filled resin sheet is produced. Thereafter, the conductive particle-filled sheet is biaxially stretched to obtain a conductive particle layer formed on the support.
- the anisotropic conductive film formed on the support can be obtained by laminating the insulating adhesive layer formed on the release sheet on the conductive particle layer thus obtained and removing the release sheet.
- a conductive particle dispersion array sheet in which conductive particles are dispersed and arranged on a support is prepared, and an insulating resin sheet separately formed on a release film is laminated on the conductive particle dispersion array sheet thus obtained,
- the conductive particle layer formed on the support is produced, and the insulating adhesive formed separately on the release sheet on the conductive particle layer thus obtained It is also possible to obtain an anisotropic conductive film formed on a support by laminating layers and removing the release sheet.
- an adhesive layer is formed on a biaxially stretchable support film, the conductive particles are closely packed on the adhesive layer, and then the conductive particle-filled sheet A biaxially-stretching method, or forming recesses with a depth of 0.8 to 1.2 times the average diameter of conductive particles in a predetermined array pattern, and producing a sheet filled with conductive particles in the recesses Further, the adhesive layer surface of the adhesive film in which the adhesive layer is formed on the support film is laminated to the sheet filled with the conductive particles, and the adhesive particle on the support film is peeled off by peeling the sheet filled with the conductive particles.
- the method of producing the film which transferred the electroconductive particle to the layer is mentioned.
- Method 2 comprises the following steps: Filling a circuit electrode surface of a semiconductor chip having a plurality of circuit electrodes on one side with an insulating adhesive; A step of laminating the obtained semiconductor chip with an insulating adhesive layer on the support, and laminating a conductive particle layer in which conductive particles are dispersed and arranged substantially in a plane in an insulating resin; Peeling the semiconductor chip with the insulating adhesive layer from the support together with the conductive particle layer; It is a manufacturing method of the semiconductor chip with an anisotropically conductive film containing (refer FIG. 4). As a method for forming the conductive particle layer, the above-described method can be used.
- Method 3 comprises the following steps: Filling a circuit electrode surface of a semiconductor chip having a plurality of circuit electrodes on one side with an insulating adhesive; A step of laminating conductive particles formed by dispersing and arranging on the pressure-sensitive adhesive layer laminated on the support to the obtained semiconductor chip with an insulating adhesive layer; Peeling the semiconductor chip with an insulating adhesive layer from the pressure-sensitive adhesive layer laminated on the support together with the conductive particles; It is a manufacturing method of the semiconductor chip with an anisotropically conductive film containing (refer FIG. 5). As a method for producing the conductive particles formed by being dispersed and arranged on the pressure-sensitive adhesive layer laminated on the support, the above-mentioned method for producing the conductive particle dispersed arrangement sheet can be used.
- vacuum lamination is preferably performed at 20 ° C. to 100 ° C., more preferably 30 to 80 ° C., and still more preferably 40 to 70 ° C.
- the temperature of the laminating process is preferably 100 ° C. or lower, and from the viewpoint of laminating properties, 20 ° C. or higher is preferable.
- an organic substrate or an inorganic substrate can be used; however, an inorganic substrate such as silicon, alumina, gallium arsenide, or glass is preferably used.
- the circuit board is a semiconductor chip and has a semiconductor chip stacked structure. When a plurality of semiconductor chips are stacked, it is preferable that a through circuit is provided in the semiconductor chip, a connection electrode is provided on the upper surface side, and a circuit electrode is formed on the lower surface side. Further, an electrode for wire bonding can be separately provided on the connection electrode surface, and electrical connection with another circuit board can be formed by wire bonding.
- the linear expansion coefficient of the circuit board may be in the range of 2.5 ⁇ 10 ⁇ 6 K ⁇ 1 to 8 ⁇ 10 ⁇ 6 K ⁇ 1 from the viewpoint of characteristic change due to warpage of the connection structure connected to the semiconductor chip. preferable.
- Circuit electrode arrangement of a semiconductor chip includes an overall arrangement in which electrodes are arranged almost on the entire lower surface of the chip, a peripheral surface arrangement in which electrodes are arranged in a portion other than the central portion of the lower surface of the chip, and electrodes on two or four sides of the lower end.
- a zigzag arrangement in which some or all of the electrodes are arranged in two or more rows can be used.
- the shape of the semiconductor chip a square or rectangular shape can be used. In the case of a rectangle, the ratio of the long side to the short side is preferably in the range of 1-30.
- the protrusion length indicating the amount of protrusion of the anisotropic conductive film from the outer periphery of the semiconductor chip is The electrode height is preferably in the range of 0.5 to 100 times, more preferably in the range of 1 to 80 times, and still more preferably in the range of 2 to 70 times.
- the protrusion length is preferably 100 times or less from the viewpoint of high-density mounting, and preferably 0.5 times or more from the viewpoint of electrical and mechanical connection.
- the amount of protrusion during crimping adjusts the circuit electrode height, electrode area, anisotropic conductive film thickness, amount of protrusion of anisotropic conductive film (length), resin viscosity of anisotropic conductive film, connection temperature, etc. Can be controlled.
- the circuit electrode of the semiconductor chip is a convex electrode made of gold, solder or copper on a single layer or multiple layers made of one or more metals selected from aluminum, copper, nickel, tungsten, titanium and silver. It is preferable to use those formed.
- the portions other than the convex electrodes of the semiconductor chip are preferably covered with an insulating film such as silicon oxide, silicon nitride, silicon oxynitride, or polyimide.
- the connection electrode of the circuit board is a single-layer or multi-layer electrode composed of one or more selected from aluminum, nickel, copper, tungsten, titanium, tantalum, molybdenum, indium tin oxide, and indium zinc oxide. It is preferable.
- the portion other than the connection electrode of the circuit board is preferably covered with an insulating film such as silicon oxide, silicon nitride, silicon oxynitride, or polyimide.
- the area of the projection electrodes of the circuit electrodes is preferably in the range of 500 [mu] m 2 ⁇ 10000 2, more preferably in the range of 1000 ⁇ m 2 ⁇ 5000 ⁇ m 2.
- the semiconductor chip with an anisotropic conductive film of the present embodiment is preferably visually inspected for the number of conductive particles on the circuit electrode before thermocompression bonding. By visual inspection, the number of conductive particles can be confirmed in advance, and abnormalities such as contamination can be confirmed.
- the number of conductive particles per unit area on the circuit electrode after connection is the conductivity per unit area of the portion other than the circuit electrode It is preferably 65% or more of the number of particles, more preferably 80% or more, and further preferably 90% or more. If the number of the conductive particles is 65% or more, it is preferable in that the conductive particles on the connection electrode hardly move and the balance between the connectivity and the insulating property is easily obtained.
- the semiconductor wafer with an anisotropic conductive film of the present embodiment has a semiconductor wafer having a plurality of circuit electrodes on one side (at least one of the main surfaces) and an anisotropic conductive film covering the circuit electrodes (FIG. 6). reference).
- the anisotropic conductive film includes an insulating resin component and conductive particles, and the conductive particles are unevenly distributed in the cross-sectional thickness direction. Specifically, 60% or more, preferably 70% or more, more preferably 80% or more of the total number of conductive particles on the surface side of the anisotropic conductive film relative to the average height of the circuit electrodes of the semiconductor wafer. However, more preferably 90% or more is present.
- the average height of the circuit electrodes refers to the average height of each circuit electrode on the basis of the portion where the circuit electrodes are not arranged in the cross section of the semiconductor chip.
- the surface side of the anisotropic conductive film refers to a side opposite to the side in contact with the semiconductor chip in the cross section of the anisotropic conductive film. If 60% or more of the total number of conductive particles is present on the surface side of the anisotropic conductive film with respect to the average height of the circuit electrodes of the semiconductor wafer, it is preferable in that the connection resistance is stabilized.
- the insulating resin component of the anisotropic conductive film can also contain a curable resin or a curing agent.
- the conductive particles can be the same as those described above for the semiconductor chip with anisotropic conductive film.
- the anisotropic conductive film includes the same insulating particles, fillers, softeners, curing accelerators, stabilizers, colorants, flame retardants, flow modifiers, and the like as described above for the semiconductor chips with anisotropic conductive films.
- a coupling agent or the like can be further contained.
- the height (thickness) of the insulating resin component on the surface side of the anisotropic conductive film on the surface side with respect to the average height of the circuit electrodes can be the same as that described above for the semiconductor chip with the anisotropic conductive film.
- the anisotropic conductive film is a conductive material in which an insulating adhesive layer and conductive particles are dispersed and arranged in a substantially planar manner in an insulating resin. It preferably consists of a particle layer (see FIG. 7).
- the thickness of the insulating resin of the conductive particle layer can be the same as that described above for the semiconductor chip with an anisotropic conductive film.
- the ratio of the total number of conductive particles in the anisotropic conductive film of the present embodiment can also be the same as described above for the semiconductor chip with an anisotropic conductive film.
- the conductive particles are preferably exposed from the surface of the anisotropic conductive film, and the exposure height indicating the degree of exposure per exposed particle is also related to the semiconductor chip with the anisotropic conductive film. It can be the same as described above.
- the insulating adhesive used in the present embodiment can also be the same as described above for the semiconductor chip with an anisotropic conductive film.
- thermoplastic resin curing agent that can be used can be the same as described above.
- the dispersion arrangement of the conductive particles can also be the same as that described above for the semiconductor chip with the anisotropic conductive film.
- the conductive particle layer is composed of conductive particles and an insulating resin as described above with respect to the semiconductor chip with an anisotropic conductive film, and may also contain a curable resin or a curing agent.
- the viscosity of the insulating resin component of the conductive particle layer can also be as described above for the semiconductor chip with an anisotropic conductive film.
- the semiconductor chip with an anisotropic conductive film according to the present embodiment is manufactured by manufacturing the semiconductor wafer with an anisotropic conductive film according to the present embodiment, and then separating (cutting out and dicing) it into pieces. Since the manufacturing method of the semiconductor wafer with an anisotropic conductive film according to the present embodiment can be manufactured, the manufacturing method of the semiconductor chip with the anisotropic conductive film is substantially the same as described above with respect to the semiconductor chip with the anisotropic conductive film, and the singulation process. Can be the same.
- the semiconductor wafer with an anisotropic conductive film of the present embodiment is preferably visually inspected for the number of conductive particles on the circuit electrode before dicing.
- the number of conductive particles can be confirmed in advance, and abnormalities such as contamination can be confirmed. Further, by specifying the abnormal part, it is possible to distinguish between a non-defective product and a defective product after dicing. Furthermore, when there are many defective portions of the semiconductor wafer with the anisotropic conductive film, it is possible to reduce the loss of the semiconductor wafer by removing the anisotropic conductive film and attaching the anisotropic conductive film again. .
- the semiconductor device is a semiconductor device including a semiconductor chip 1 having a plurality of circuit electrodes 2 on one side, a circuit board 11 having connection electrodes 12 corresponding to the circuit electrodes 2, and an adhesive 10.
- the adhesive 10 includes an insulating resin and conductive particles 4, and is disposed between the semiconductor chip 1 and the circuit board 11, and between the circuit electrodes having the shortest distance on the semiconductor chip 1.
- the distance between particles in the thickness direction of the conductive particles closest to the semiconductor chip and the conductive particles farthest from the semiconductor chip in the cross section cut in the thickness direction is not more than 1 times the average diameter of the conductive particles ( (See FIG. 11).
- the inter-particle distance in the thickness direction of the conductive particles closest to the semiconductor chip and the conductive particles farthest from the semiconductor chip is an imaginary straight line drawn perpendicularly to the thickness direction from the center of the particle farthest from the semiconductor chip. 15 and the virtual straight line 16 drawn perpendicularly to the thickness direction from the center of the particle closest to the semiconductor chip (see FIG. 11).
- the semiconductor device of this embodiment is excellent in connection resistance and insulation after a reliability test by taking the arrangement of the conductive particles defined above.
- the interparticle distance in the thickness direction of the conductive particles closest to the semiconductor chip and the conductive particles farthest from the semiconductor chip is preferably 0.9 times or less of the average diameter of the conductive particles,
- the ratio is more preferably 0.8 times or less, further preferably 0.5 times or less, and particularly preferably 0.35 times or less.
- the minimum value of the distance is 0 times.
- the semiconductor device defined above includes, for example, a semiconductor chip with an anisotropic conductive film having a plurality of circuit electrodes on one side and conductive particles in the anisotropic conductive adhesive film being unevenly distributed in the cross-sectional thickness direction. It can be obtained by pressure bonding to a circuit board having opposing connection electrodes.
- the circuit electrodes can be the same as described above for the semiconductor chip with anisotropic conductive film.
- the average diameter of the conductive particles needs to be smaller than the distance between adjacent electrodes to be connected, and is preferably larger than the variation in the electrode height of the electronic component to be connected.
- the average diameter of the conductive particles is preferably in the range of 2.0 ⁇ m to 50 ⁇ m, more preferably 2.5 ⁇ m to 40 ⁇ m, further preferably 3.0 ⁇ m to 35 ⁇ m, and particularly preferably 4.0 ⁇ m to 30 ⁇ m. .
- the standard deviation of the particle size distribution of the conductive particles is preferably 50% or less of the average diameter.
- the maximum protrusion length which indicates the amount of adhesive protruding from the semiconductor chip outer shape, is preferably ⁇ 20 to 50 ⁇ m, more preferably ⁇ 10 to 30 ⁇ m. More preferably, it is 0 to 20 ⁇ m. From the viewpoint of electrical and mechanical connectivity, the protrusion length is preferably ⁇ 20 ⁇ m or more. On the other hand, from the viewpoint of handling property and resin protrusion at the time of connection, it is preferably 50 ⁇ m or less.
- the number of conductive particles per unit area on the circuit electrode is preferably 65% or more of the number of conductive particles per unit area other than the circuit electrode, and 80% or more. It is more preferable that it is 90% or more. If the number of conductive particles is 65% or more, it is preferable in terms of easy balance between connectivity and insulation.
- Inspection evaluation of semiconductor chip with anisotropic conductive film Inspectability evaluation: The number of conductive particles on the gold bump was measured from the anisotropic conductive film surface of the wafer with the anisotropic conductive film using a microscope. The measurement was evaluated as OK and the measurement impossible as NG. Inspection result evaluation: In the same manner as above, the number of conductive particles on the connection bumps was measured for 50 bumps. When the standard deviation / average value is less than 0.3, ⁇ , and when 0.3 or more, ⁇ As evaluated.
- the number of conductive particles on the gold bump after pressure bonding was measured for 50 bumps in the same manner as described above, and the average number of captured particles and the ratio of the number of conductive particles on the connection bump measured before connection were calculated.
- the evaluation was evaluated as ⁇ when it was 65% or more and less than 90%, ⁇ when it was 90% or more, and ⁇ when it was less than 65%.
- Tantalum wiring (0.8 ⁇ m) on a non-alkali glass with a thickness of 0.5 mm so that the gold bumps on the aluminum thin film of the semiconductor chip are connected in a positional relationship with the gold bumps on the adjacent aluminum thin film, Then, a connection pad (42 ⁇ m wide, 120 ⁇ m long) of an indium tin oxide film (1400 mm) was formed. Each time 20 gold bumps are connected, an indium tin oxide thin film lead wiring is formed on the connection pad, and an aluminum titanium thin film (titanium 1%, 3000 mm) is formed on the lead wiring to form a connection evaluation board. .
- connection pads of the connection evaluation board and the gold bumps of the semiconductor chip were aligned and pressure-bonded with a load of 40 MPa at 190 ° C. for 10 seconds to produce a semiconductor device.
- resistance was measured with a four-terminal resistance meter between the lead wires (daisy chain of 20 gold bumps) to obtain an initial connection resistance value.
- This connection resistance measurement substrate was held in an environment of 85 ° C. and 85% RH for 500 hours, taken out, measured for connection resistance value after being left at 25 ° C. for 1 hour, and set as a connection resistance value after a reliability test.
- Tantalum wiring (0.8 ⁇ m) and then indium tin oxide film (1400 mm) in a positional relationship such that two gold bumps on an aluminum thin film of a semiconductor chip are connected to an alkali-free glass having a thickness of 0.5 mm.
- Connection pads (width 42 ⁇ m, length 120 ⁇ m). A connection wiring of an indium tin oxide thin film was formed so that every other five connection pads could be connected.
- An indium tin oxide thin film (1400 mm) lead wiring was formed on each connection wiring, and an aluminum titanium thin film (titanium 1%, 3000 mm) was formed on the lead wiring to provide an insulating evaluation substrate.
- connection pads of the insulation resistance evaluation board and the gold bumps of the semiconductor chip were aligned and pressure-bonded at 190 ° C. for 10 seconds with a load of 40 MPa to obtain an insulation resistance test substrate.
- a DC voltage of 30 V was applied between the pair of lead wires using a low voltage low current power source.
- the insulation resistance between the wires was measured every 5 minutes, the time until the insulation resistance became 10 M ⁇ or less was measured, and the value was taken as the insulation decrease time.
- the case where the insulation decrease time was less than 500 hours was evaluated as NG and the case where the insulation decrease time was 500 hours or more was evaluated as OK.
- the distance between the electrodes that is the shortest and that is closest to the center in the long side direction is cleaved in the thickness direction with the target cross-section sample preparation device (EM TXP manufactured by LEICA). To do. After polishing to the vicinity of the observation site with polishing paper, the obtained cross section is smoothed with a broad ion beam apparatus (model number: E-3500, manufactured by Hitachi, Ltd.).
- the fractured surface of the measurement target was a fractured surface containing 5 or more conductive particles between the electrodes.
- osmium was deposited on the fractured surface using a vapor deposition apparatus (model number: HPC-1s Osmium coat manufactured by Vacuum Device), thereby conducting a conductive treatment.
- a scanning electron microscope (model number: S-4700, manufactured by Hitachi, Ltd.) was used for cross-sectional observation. Measure the distance between the virtual straight line drawn perpendicular to the thickness direction from the center of the particle farthest from the semiconductor chip between the electrodes and the virtual straight line drawn perpendicular to the thickness direction from the center of the particle closest to the semiconductor chip, The interparticle distance in the thickness direction of the conductive particles closest to the semiconductor chip and the conductive particles farthest from the semiconductor chip was used. The distance from the semiconductor chip was the length of the perpendicular line from the center of the conductive particles to the Si substrate in the split section.
- Adhesive layer A 90 g of phenoxy resin (glass transition temperature 84 ° C., number average molecular weight 9500), bisphenol A type liquid epoxy resin (epoxy equivalent 190, 25 ° C. viscosity, 14000 mPa ⁇ s) 10 g, 1.5 g of ⁇ -glycidoxypropyltriethoxysilane, And 250 g of ethyl acetate were mixed to obtain an insulating resin varnish for the conductive particle layer.
- This insulating resin varnish for conductive particle layer was applied on a polyethylene terephthalate film having a thickness of 38 ⁇ m, and dried at 60 ° C.
- a viscosity measurement sheet was prepared in the same manner, and the viscosity at 100 ° C. was measured with a rheometer (60 ° C./min, temperature increase).
- Insulating adhesive layer B 40 g of phenoxy resin (glass transition temperature 91 ° C., number average molecular weight 11300), bisphenol A type liquid epoxy resin (epoxy equivalent 190, 25 ° C. viscosity, 14000 mPa ⁇ s) 10 g, and ⁇ -glycidoxypropyltriethoxysilane 1.0 g was dissolved in a mixed solvent of ethyl acetate-toluene (mixing ratio 1: 1) to obtain a 50% solid content solution.
- phenoxy resin glass transition temperature 91 ° C., number average molecular weight 11300
- bisphenol A type liquid epoxy resin epoxy equivalent 190, 25 ° C. viscosity, 14000 mPa ⁇ s
- ⁇ -glycidoxypropyltriethoxysilane 1.0 g was dissolved in a mixed solvent of ethyl acetate-toluene (mixing ratio 1: 1) to obtain a 50% solid
- liquid epoxy resin containing microcapsule type latent imidazole curing agent (average particle size of microcapsule 5 ⁇ m, active temperature 123 degrees, liquid epoxy resin) (containing 33.5 g of liquid epoxy resin) Were mixed and dispersed. Then, this was apply
- a sheet for viscosity measurement was prepared by the same method, and the viscosity at 100 ° C. was measured with a rheometer (60 ° C./min, temperature increase), which was 450 Pa ⁇ s.
- Conductive particle dispersion arrangement sheet C On an unstretched copolymer polypropylene film having a thickness of 100 ⁇ m, a graft copolymer adhesive of nitrile rubber latex-methyl methacrylate was applied as an adhesive layer to a thickness of 4 ⁇ m. On this adhesive layer-coated polypropylene film, gold-plated plastic particles (acrylic resin, conductive particles) having an average diameter of 3.8 ⁇ m are laid so that the conductive particles form a plurality of layers on the surface of the adhesive. The conductive particles were scraped off with a scrubber made of soft rubber, and filled with a single layer with almost no gap. The filling rate was 80%.
- This film was fixed with 10 chucks in the vertical and horizontal directions using a biaxial stretching device (Toyo Seiki X6H-S, pantograph type corner stretching type biaxial stretching device), preheated to 125 ° C for 120 seconds, and then The conductive particle-dispersed array sheet C was obtained by being stretched and fixed 2.4 times at a rate of 10% / second.
- a biaxial stretching device Toyo Seiki X6H-S, pantograph type corner stretching type biaxial stretching device
- Anisotropic conductive film D Adhesive layer A is laminated on the conductive particle dispersion arrangement surface of conductive particle dispersion arrangement sheet C, and vacuum lamination is performed under conditions of 80 ° C. and 0.4 MPa to produce a conductive particle layer, and the polyethylene terephthalate film is peeled off.
- the insulating adhesive layer B was laminated on the peeled surface, vacuum laminated under the conditions of 55 ° C. and 0.6 MPa, and then the polyethylene terephthalate film was peeled off to obtain an anisotropic conductive film D.
- Semiconductor chip E with anisotropic conductive film The gold bump arrangement surface side of the semiconductor chip is vacuum laminated (55 ° C., 1.0 MPa) on the adhesive layer A side of the anisotropic conductive film D, and then the semiconductor chip is attached with an adhesive layer together with the anisotropic conductive film. It peeled from the polypropylene film and obtained the semiconductor chip E with an anisotropically conductive film. It was 18.8 micrometers when the thickness of the insulating resin component of the anisotropic conductive film of the semiconductor chip E with an anisotropic conductive film was measured with the laser microscope. The thickness of the insulating resin component of the anisotropic conductive film on the gold bump was 3.8 ⁇ m. This semiconductor chip E with anisotropic conductive film was frozen and cut, and the cross-section was observed to confirm 50 conductive particle positions. It was confirmed that 50 out of 50 were on the surface side from the average height of the bumps.
- Conductive particle layer F On an unstretched copolymer polypropylene film having a thickness of 100 ⁇ m, a graft copolymer adhesive of nitrile rubber latex-methyl methacrylate was applied as an adhesive layer to a thickness of 4 ⁇ m. Gold-plated plastic particles (acrylic resin, conductive particles) having an average diameter of 3.8 ⁇ m are laid on this adhesive layer-coated polypropylene film so that the conductive particles form a plurality of layers on the pressure-sensitive adhesive surface. The particles were scraped off with a scrubber made of soft rubber to fill a single layer with almost no gap. The filling rate was 80%.
- the conductive particle-filled film is fixed by using 10 chucks in the vertical and horizontal directions using a biaxial stretching apparatus (Toyo Seiki X6H-S, pantograph type corner stretch type biaxial stretching apparatus), and 125 ° C., 120 Preheating was performed for 2 seconds, and then the film was stretched by 2.4 times and fixed at a rate of 10% / second to obtain a conductive particle layer F.
- a biaxial stretching apparatus Toyo Seiki X6H-S, pantograph type corner stretch type biaxial stretching apparatus
- 125 ° C., 120 Preheating was performed for 2 seconds, and then the film was stretched by 2.4 times and fixed at a rate of 10% / second to obtain a conductive particle layer F.
- the number of conductive particles was measured using a microscope, the number of conductive particles in the range of 100 ⁇ m ⁇ 100 ⁇ m was 139.
- the average particle spacing of the conductive particles was 12.0 ⁇ m, the conductive particles were dispersed and arranged in a
- Semiconductor chip G with insulating adhesive layer An insulating adhesive layer was produced in the same manner as in Example 1 except that the film thickness was 18 ⁇ m.
- the gold bump placement surface side of the semiconductor chip is vacuum-laminated (55 ° C., 1.0 MPa) on the insulating adhesive layer, and then the semiconductor chip is peeled off from the polyethylene terephthalate film together with the insulating adhesive layer.
- the insulating adhesive layer was removed, and a semiconductor chip G with an insulating adhesive layer was obtained.
- Semiconductor chip H with anisotropic conductive film The insulating adhesive layer surface side of the semiconductor chip G with the insulating adhesive layer is laminated on the conductive particle layer F (55 ° C., 1.0 MPa), and then the semiconductor chip with the insulating adhesive layer together with the conductive particle layer. was peeled from the polypropylene film with an adhesive layer to obtain a semiconductor chip H with an anisotropic conductive film.
- the thickness of the insulating resin component of the anisotropic conductive film of the semiconductor chip H with the anisotropic conductive film was measured with a laser microscope, it was 19.1 ⁇ m.
- the thickness of the insulating resin component of the anisotropic conductive film on the gold bump was 4.1 ⁇ m.
- the semiconductor chip H with the anisotropic conductive film was frozen and cut, and the cross-section was observed to confirm 50 conductive particle positions. It was confirmed that 50 out of 50 were on the surface side from the average height of the bumps.
- Example 3 A semiconductor chip I with an anisotropic conductive film was obtained in the same manner as in Example 1 except that the thickness of the adhesive layer A was 4.0 ⁇ m. It was 19.8 micrometers when the thickness of the insulating resin component of the anisotropic conductive film of the semiconductor chip I with an anisotropic conductive film was measured with the laser microscope. The thickness of the insulating resin component of the anisotropic conductive film on the gold bump was 4.8 ⁇ m. The semiconductor chip I with anisotropic conductive film was frozen and cut, and the cross-section was observed to confirm 50 conductive particle positions. It was confirmed that 50 out of 50 were on the surface side from the average height of the bumps.
- Example 4 Semiconductor chip J with anisotropic conductive film A semiconductor chip with an insulating adhesive layer was produced in the same manner as in Example 2 except that the film thickness was 19.5 ⁇ m, and a vacuum was formed on the conductive particle-dispersed array sheet C produced in the same manner as in Example 1. After laminating (40 ° C., 0.5 MPa), the semiconductor chip with the insulating adhesive layer was peeled off from the polypropylene film with the adhesive layer together with the conductive particles to obtain the semiconductor chip J with the anisotropic conductive film. It was 18.8 micrometers when the thickness of the insulating resin component of the anisotropic conductive film of the semiconductor chip J with an anisotropic conductive film was measured with the laser microscope.
- the thickness of the insulating resin component of the anisotropic conductive film on the gold bump was 3.8 ⁇ m. From the anisotropic conductive film surface, the amount of exposure from the surface of the conductive particles was measured using a microscope. When 50 conductive particles were measured, all of them were exposed, and the average exposure height was 0.3 ⁇ m.
- Example 1 An insulating adhesive layer was prepared in the same manner as in Example 1 except that the film thickness was 19 ⁇ m, and was laminated (50 ° C., 0.005 ° C.) on the conductive particle-dispersed array sheet C prepared in the same manner as in Example 1. 5 MPa) to obtain an anisotropic conductive film K.
- the anisotropic conductive film K was slit to a width of 1.6 mm.
- the slit anisotropic conductive film K was temporarily pressure-bonded at 80 ° C. for 1 second at 0.2 MPa so that the connection electrode on the connection evaluation substrate was covered and the conductive particle layer was disposed on the substrate side.
- connection evaluation board was temporarily bonded by the above method and the semiconductor chip was not attached with an anisotropic conductive film. The same conditions and methods as in the examples were used.
- liquid epoxy resin containing microcapsule type latent imidazole curing agent (average particle size of microcapsule 5 ⁇ m, active temperature 123 degrees, liquid epoxy resin) (containing 33.5 g of liquid epoxy resin)
- a varnish for anisotropic conductive film To this varnish for anisotropic conductive film, gold plated plastic particles (acrylic resin, conductive particles) having an average diameter of 3.8 ⁇ m are added so that the density of conductive particles is 50000 / mm 2, and a polyethylene terephthalate film having a thickness of 50 ⁇ m. It applied on top and dried at 60 degreeC for 15 minutes, and the anisotropic conductive film L with a film thickness of 20 micrometers was obtained.
- the gold bump placement surface side of the semiconductor chip is vacuum laminated (55 ° C., 1.0 MPa), and then the semiconductor chip is peeled from the polyethylene terephthalate film together with the anisotropic conductive film L, Excess anisotropic conductive film was removed to obtain a semiconductor chip M with anisotropic conductive film. It was 19.8 micrometers when the thickness of the insulating resin component of the anisotropic conductive film of the semiconductor chip M with an anisotropic conductive film was measured with the laser microscope. The thickness of the insulating resin component of the anisotropic conductive film on the gold bump was 4.8 ⁇ m. The semiconductor chip M was frozen and cut, and the cross section was observed. The conductive particles were distributed almost uniformly in the thickness direction.
- Comparative Example 3 The same as Comparative Example 2 except that gold-plated plastic particles (acrylic resin, conductive particles) having an average diameter of 3.8 ⁇ m were added to the anisotropic conductive film varnish so that the conductive particle density was 10,000 particles / mm 2. Thus, an anisotropic conductive film N was obtained.
- the gold bump placement surface side of the semiconductor chip is vacuum laminated (55 ° C., 1.0 MPa) on the anisotropic conductive film N, and then the semiconductor chip is peeled from the polyethylene terephthalate film together with the anisotropic conductive film N, Excess anisotropic conductive film was removed to obtain a semiconductor chip O with an anisotropic conductive film.
- Table 1 below shows the evaluation results of each item in each example and comparative example.
- the semiconductor chip with anisotropic conductive film shown in each example has a distance between the conductive particles in the thickness direction of the semiconductor device of not more than twice the average diameter of the conductive particles. It was excellent in all of inspection property, connection resistance after reliability test, insulation test evaluation result, and alignment property.
- Inspection evaluation of semiconductor wafer with anisotropic conductive film Inspectability evaluation: The number of conductive particles on the gold bump was measured from the anisotropic conductive film surface of the wafer with the anisotropic conductive film using a microscope. The measurement was evaluated as OK and the measurement impossible as NG. Inspection result evaluation: In the same manner as above, the number of conductive particles on the connection bumps was measured for 50 bumps. When the standard deviation / average value is less than 0.3, ⁇ , and when 0.3 or more, ⁇ As evaluated.
- the number of conductive particles on the gold bump after pressure bonding was measured for 50 bumps in the same manner as described above, and the average number of captured particles and the ratio of the number of conductive particles on the connection bump measured before connection were calculated.
- the evaluation was evaluated as ⁇ when it was 65% or more and less than 90%, ⁇ when it was 90% or more, and ⁇ when it was less than 65%.
- Tantalum wiring (0.8 ⁇ m) so that the gold bump on the aluminum thin film of the evaluation chip is connected to the gold bump on the adjacent aluminum thin film in a positional relationship on an alkali-free glass with a thickness of 0.5 mm, Subsequently, a connection pad (42 ⁇ m wide, 120 ⁇ m long) of an indium tin oxide film (1400 mm) was formed. Each time 20 gold bumps are connected, an indium tin oxide thin film lead wiring is formed on the connection pad, and an aluminum titanium thin film (titanium 1%, 3000 mm) is formed on the lead wiring to form a connection evaluation board. .
- connection pads of this connection evaluation board and the gold bumps of the semiconductor chip with the anisotropic conductive film were aligned and pressure-bonded at 190 ° C. for 10 seconds with a load of 40 MPa. After crimping, resistance was measured with a four-terminal resistance meter between the lead wires (daisy chain of 20 gold bumps) to obtain an initial connection resistance value.
- This connection resistance measurement substrate was held in an environment of 85 ° C. and 85% RH for 500 hours, taken out, measured for connection resistance value after being left at 25 ° C. for 1 hour, and set as a resistance value after a reliability test.
- connection pads of this insulation resistance evaluation board and the gold bumps of the semiconductor chip with an anisotropic conductive film were aligned and pressure-bonded at 190 ° C. for 10 seconds under a load of 40 MPa to obtain an insulation resistance test board.
- a DC voltage of 30 V was applied between the pair of lead wires using a low voltage low current power source.
- the insulation resistance between the wires was measured every 5 minutes, the time until the insulation resistance became 10 M ⁇ or less was measured, and the value was taken as the insulation decrease time.
- the case where the insulation decrease time was less than 500 hours was evaluated as NG and the case where the insulation decrease time was 500 hours or more was evaluated as OK.
- Adhesive layer A 90 g of phenoxy resin (glass transition temperature 84 ° C., number average molecular weight 9500), bisphenol A type liquid epoxy resin (epoxy equivalent 190, 25 ° C. viscosity, 14000 mPa ⁇ s) 10 g, 1.5 g of ⁇ -glycidoxypropyltriethoxysilane, And 250 g of ethyl acetate were mixed to obtain an insulating resin varnish for the conductive particle layer.
- This insulating resin varnish for conductive particle layer was applied on a polyethylene terephthalate film having a thickness of 38 ⁇ m, and dried at 60 ° C.
- a viscosity measurement sheet was prepared in the same manner, and the viscosity at 100 ° C. was measured with a rheometer (60 ° C./min, temperature increase).
- Insulating adhesive layer B 40 g of phenoxy resin (glass transition temperature 91 ° C., number average molecular weight 11300), bisphenol A type liquid epoxy resin (epoxy equivalent 190, 25 ° C. viscosity, 14000 mPa ⁇ s) 10 g, and ⁇ -glycidoxypropyltriethoxysilane 1.0 g was dissolved in a mixed solvent of ethyl acetate-toluene (mixing ratio 1: 1) to obtain a 50% solid content solution.
- phenoxy resin glass transition temperature 91 ° C., number average molecular weight 11300
- bisphenol A type liquid epoxy resin epoxy equivalent 190, 25 ° C. viscosity, 14000 mPa ⁇ s
- ⁇ -glycidoxypropyltriethoxysilane 1.0 g was dissolved in a mixed solvent of ethyl acetate-toluene (mixing ratio 1: 1) to obtain a 50% solid
- liquid epoxy resin containing microcapsule type latent imidazole curing agent (average particle size of microcapsule 5 ⁇ m, active temperature 123 degrees, liquid epoxy resin) (containing 33.5 g of liquid epoxy resin) Were mixed and dispersed. Then, this was apply
- a sheet for viscosity measurement was prepared by the same method, and the viscosity at 100 ° C. was measured with a rheometer (60 ° C./min, temperature increase), which was 450 Pa ⁇ s.
- Conductive particle dispersion arrangement sheet C On an unstretched copolymer polypropylene film having a thickness of 100 ⁇ m, a graft copolymer adhesive of nitrile rubber latex-methyl methacrylate was applied as an adhesive layer to a thickness of 4 ⁇ m. On this adhesive layer-coated polypropylene film, gold-plated plastic particles (acrylic resin, conductive particles) having an average diameter of 3.8 ⁇ m are laid so that the conductive particles form a plurality of layers on the surface of the adhesive. The conductive particles were scraped off with a scrubber made of soft rubber, and filled with a single layer with almost no gap. The filling rate was 80%.
- This film was fixed with 10 chucks in the vertical and horizontal directions using a biaxial stretching device (Toyo Seiki X6H-S, pantograph type corner stretching type biaxial stretching device), preheated to 125 ° C for 120 seconds, and then The conductive particle-dispersed array sheet C was obtained by being stretched and fixed 2.4 times at a rate of 10% / second.
- a biaxial stretching device Toyo Seiki X6H-S, pantograph type corner stretching type biaxial stretching device
- Anisotropic conductive film D Adhesive layer A is laminated on the conductive particle dispersion arrangement surface of conductive particle dispersion arrangement sheet C, and vacuum lamination is performed under conditions of 80 ° C. and 0.4 MPa to produce a conductive particle layer, and the polyethylene terephthalate film is peeled off.
- the insulating adhesive layer B was laminated on the peeled surface, vacuum laminated under the conditions of 55 ° C. and 0.6 MPa, and then the polyethylene terephthalate film was peeled off to obtain an anisotropic conductive film D.
- Semiconductor wafer E with anisotropic conductive film The gold bump placement surface side of the semiconductor wafer is vacuum laminated (55 ° C., 1.0 MPa) on the anisotropic conductive film D, and then the semiconductor wafer is peeled off from the polypropylene film with the adhesive layer together with the anisotropic conductive film. And the semiconductor wafer E with an anisotropically conductive film was obtained. It was 18.8 micrometers when the thickness of the insulating resin component of the anisotropic conductive film of the semiconductor wafer E with an anisotropic conductive film was measured with the laser microscope. The thickness of the insulating resin component of the anisotropic conductive film on the gold bump was 3.8 ⁇ m. The semiconductor wafer E with anisotropic conductive film was frozen and cut, and the cross-section was observed to confirm 50 conductive particle positions. It was confirmed that 50 out of 50 were on the surface side from the average height of the bumps.
- Conductive particle layer F On an unstretched copolymer polypropylene film having a thickness of 100 ⁇ m, a graft copolymer adhesive of nitrile rubber latex-methyl methacrylate was applied as an adhesive layer to a thickness of 4 ⁇ m. Gold-plated plastic particles (acrylic resin, conductive particles) having an average diameter of 3.8 ⁇ m are laid on this adhesive layer-coated polypropylene film so that the conductive particles form a plurality of layers on the pressure-sensitive adhesive surface. The particles were scraped off with a scrubber made of soft rubber to fill a single layer with almost no gap. The filling rate was 80%.
- the conductive particle-filled film is fixed by using 10 chucks in the vertical and horizontal directions using a biaxial stretching apparatus (Toyo Seiki X6H-S, pantograph type corner stretch type biaxial stretching apparatus), and 125 ° C., 120 Preheating was performed for 2 seconds, and then the film was stretched by 2.4 times and fixed at a rate of 10% / second to obtain a conductive particle layer F.
- a biaxial stretching apparatus Toyo Seiki X6H-S, pantograph type corner stretch type biaxial stretching apparatus
- 125 ° C., 120 Preheating was performed for 2 seconds, and then the film was stretched by 2.4 times and fixed at a rate of 10% / second to obtain a conductive particle layer F.
- the number of conductive particles was measured using a microscope, the number of conductive particles in the range of 100 ⁇ m ⁇ 100 ⁇ m was 139.
- the average particle spacing of the conductive particles was 12.0 ⁇ m, the conductive particles were dispersed and arranged in a
- insulating adhesive layer was produced in the same manner as in Example 1 except that the film thickness was 18 ⁇ m.
- the gold bump placement surface side of the semiconductor wafer is vacuum-laminated (55 ° C., 1.0 MPa) on this insulating adhesive layer, and then the semiconductor wafer is peeled off from the polyethylene terephthalate film together with the insulating adhesive layer to remove excess The insulating adhesive layer was removed, and a semiconductor wafer G with an insulating adhesive layer was obtained.
- Semiconductor wafer H with anisotropic conductive film The insulating adhesive layer surface side of the semiconductor wafer G with the insulating adhesive layer is laminated on the conductive particle layer F (55 ° C., 1.0 MPa), and then the semiconductor wafer with the insulating adhesive layer together with the conductive particle layer.
- the thickness of the insulating resin component of the anisotropic conductive film on the gold bump was 4.0 ⁇ m.
- the semiconductor wafer H with the anisotropic conductive film was frozen and cut, and the cross-section was observed to confirm 50 conductive particle positions. It was confirmed that 50 out of 50 were on the surface side from the average height of the bumps.
- Example 7 A semiconductor wafer I with an anisotropic conductive film was obtained in the same manner as in Example 1 except that the thickness of the adhesive layer A was 4.0 ⁇ m. It was 19.8 micrometers when the thickness of the insulating resin component of the anisotropic conductive film of the semiconductor wafer I with an anisotropic conductive film was measured with the laser microscope. The thickness of the insulating resin component of the anisotropic conductive film on the gold bump was 4.8 ⁇ m. The semiconductor wafer I with anisotropic conductive film was cleaved and subjected to cross-sectional observation, and 50 conductive particle positions were confirmed. It was confirmed that 50 out of 50 were on the surface side from the average height of the bumps.
- Example 8 Semiconductor wafer with anisotropic conductive film J A semiconductor wafer with an insulating adhesive layer was produced in the same manner as in Example 2 except that the film thickness was 19.5 ⁇ m, and a vacuum was formed on the conductive particle-dispersed array sheet C produced in the same manner as in Example 1. After laminating (40 ° C., 0.5 MPa), the semiconductor wafer with an insulating adhesive layer was peeled off from the polypropylene film with an adhesive layer together with the conductive particles to obtain a semiconductor wafer J with an anisotropic conductive film.
- the thickness of the insulating resin component of the anisotropic conductive film of the semiconductor wafer J with an anisotropic conductive film was measured with the laser microscope. Moreover, the thickness of the insulating resin component of the anisotropic conductive film on the gold bump was 3.7 ⁇ m. From the anisotropic conductive film surface, the amount of exposure from the surface of the conductive particles was measured using a microscope. When 50 conductive particles were measured, all of them were exposed, and the average exposure height was 0.25 ⁇ m.
- liquid epoxy resin containing microcapsule type latent imidazole curing agent (average particle size of microcapsule 5 ⁇ m, active temperature 123 degrees, liquid epoxy resin) (containing 33.5 g of liquid epoxy resin)
- a varnish for anisotropic conductive film To this varnish for anisotropic conductive film, gold plated plastic particles (acrylic resin, conductive particles) having an average diameter of 3.8 ⁇ m are added so that the density of conductive particles is 50000 / mm 2, and a polyethylene terephthalate film having a thickness of 50 ⁇ m. It was coated on top and dried at 60 ° C. for 15 minutes to obtain an anisotropic conductive film K having a thickness of 20 ⁇ m.
- the gold bump placement surface side of the semiconductor wafer is vacuum laminated (55 ° C., 1.0 MPa) on the anisotropic conductive film K, and then the semiconductor wafer is peeled from the polyethylene terephthalate film together with the anisotropic conductive film K, Excess anisotropic conductive film was removed to obtain a semiconductor wafer L with an anisotropic conductive film. It was 19.7 micrometers when the thickness of the insulating resin component of the anisotropic conductive film of the semiconductor wafer L with an anisotropic conductive film was measured with the laser microscope. The thickness of the insulating resin component of the anisotropic conductive film on the gold bump was 4.7 ⁇ m. This semiconductor wafer L was frozen and cut, and the cross section was observed. The conductive particles were not distributed unevenly in the thickness direction and were distributed almost uniformly.
- Comparative Example 5 The same as Comparative Example 1 except that gold-plated plastic particles (acrylic resin, conductive particles) with an average diameter of 3.8 ⁇ m were added to the anisotropic conductive film varnish so that the density of conductive particles was 10,000 particles / mm 2. Thus, an anisotropic conductive film M was obtained. On this anisotropic conductive film M, the gold bump placement surface side of the semiconductor chip is vacuum laminated (55 ° C., 1.0 MPa), and then the semiconductor wafer is peeled from the polyethylene terephthalate film together with the anisotropic conductive film M, Excess anisotropic conductive film was removed to obtain a semiconductor wafer N with an anisotropic conductive film.
- gold-plated plastic particles acrylic resin, conductive particles
- the semiconductor wafer with an anisotropic conductive film shown in each example has any of inspection property, dicing property, connection resistance after reliability test, insulation test evaluation result, and alignment property. was also excellent.
- the present invention can be suitably used for semiconductor chip stacked connection, connection of semiconductor chips to an interposer, and the like.
Abstract
Description
これまで、半導体チップ電極のような微細回路を接続するための異方導電性フィルムに関して、短絡防止のため、導電性粒子の表面を電気絶縁樹脂で被覆する方法(以下の特許文献1参照)、導電性粒子を含む層と含まない層を積層し、隣接する回路間の短絡を防止する方法(以下の特許文献2、3参照)等が公知である。また、導電性粒子を単層に配列し、異方導電性フィルム中の導電性粒子を低減し、接続-絶縁のバランス化を図る方法も公知である(以下の特許文献4参照)。さらに半導体チップの接続電極面に接続端子表面が出るように絶縁性樹脂層を形成し、相対する電極に圧着する方法(以下の特許文献5~7参照)、半導体チップの接続端子面に接続端子表面が出るように絶縁性接着層を形成し、略1層の異方導電性フィルムを貼り付けた電極に圧着する方法(以下の特許文献8参照)、異方導電性フィルムに半導体チップをラミネートした後、剥離して異方導電性フィルムを転写した半導体チップを形成・圧着する方法(以下の特許文献9,10参照)も公知である。また、半導体ウェハにスピンコートにより異方導電性接着剤層を形成し、次いでウェハをダイシングして個々のチップに分割する方法も提案されている(以下の特許文献11参照)。
また、半導体チップに導電性粒子のない絶縁性接着剤層のみを形成する場合、相対する電極に圧着した際、電極上の絶縁性樹脂が残りやすく、あるいは、電極高さばらつきの影響で接続抵抗が不安定になり、接続信頼性の点でも問題がある。
さらに、半導体チップ上に異方導電性フィルムを貼り付ける方法においては、微小サイズの電極を高接続信頼性で接続するために、導電性粒子の配合量を多くする必要があり、その際に、半導体チップ面のアライメントマークが読み取り困難で位置決めができないという問題がある。
かかる状況下、本発明が解決しようとする課題は、接続前に接続部の検査が可能であり、接続に寄与する導電性粒子数を予測することが可能であり、かつ、接続時のアライメントマークの認識性に優れる異方導電性フィルム付き半導体チップを提供することである。
また、ダイシング前に接続部の検査が可能である異方導電性フィルム付き半導体ウェハを提供することであり、該異方導電性フィルム付き半導体ウェハをダイシングすることで、接続に寄与する導電性粒子数を予測することが可能であり、かつ、接続時のアライメントマークの認識性に優れる異方導電性フィルム付き半導体チップの製造方法を提供することである。
すなわち、本発明は、下記の通りのものである。
支持体、導電性粒子が断面厚み方向において支持体側に偏在している異方導電性フィルム層、の順に積層してなる積層体に、片面に複数の回路電極を有する半導体チップの該回路電極面をラミネートする工程、及び
該ラミネートした該半導体チップを、該異方導電性フィルム層とともに、該支持体から剥離する工程、
を含む、前記[1]に記載の異方導電性フィルム付き半導体チップの製造方法。
片面に複数の回路電極を有する半導体チップの回路電極面に、絶縁性接着剤を充填する工程、
得られた絶縁性接着剤層付き半導体チップに、支持体上に形成され、かつ、絶縁性樹脂中に導電性粒子が略平面状に1層分散配列した導電性粒子層を、ラミネートする工程、
前記絶縁性接着剤層付き半導体チップを、前記導電性粒子層とともに、前記支持体から剥離する工程、
を含む、前記[3]に記載の異方導電性フィルム付き半導体チップの製造方法。
片面に複数の回路電極を有する半導体チップの回路電極面に、絶縁性接着剤を充填する工程、
得られた絶縁性接着剤層付き半導体チップに、支持体上に積層した粘着剤層上に分散配列して形成された導電性粒子を、ラミネートする工程、
前記絶縁性接着剤層付き半導体チップを、前記導電性粒子とともに、前記支持体上に積層した粘着剤層から剥離する工程、
を含む、前記[3]に記載の異方導電性フィルム付き半導体チップの製造方法。
支持体、導電性粒子が断面厚み方向において支持体側に偏在している異方導電性フィルム層、の順に積層してなる積層体に、片面に複数の回路電極を有する半導体ウェハの該回路電極面をラミネートする工程、及び
該ラミネートした該半導体ウェハを、該異方導電性フィルム層とともに、該支持体から剥離する工程、
を含む、前記[18]に記載の異方導電性フィルム付き半導体ウェハの製造方法。
片面に複数の回路電極を有する半導体ウェハの回路電極面に、絶縁性接着剤を充填する工程、
得られた絶縁性接着剤層付き半導体ウェハに、支持体上に形成され、かつ、絶縁性樹脂中に導電性粒子が略平面状に1層分散配列した導電性粒子層を、ラミネートする工程、
前記絶縁性接着剤層付き半導体ウェハを、前記導電性粒子層とともに、前記支持体から剥離する工程、
を含む、前記[20]に記載の異方導電性フィルム付き半導体ウェハの製造方法。
片面に複数の回路電極を有する半導体ウェハの回路電極面に、絶縁性接着剤を充填する工程、
得られた絶縁性接着剤層付き半導体ウェハに、支持体上に積層した粘着剤層上に分散配列して形成された導電性粒子を、ラミネートする工程、
前記絶縁性接着剤層付き半導体ウェハを、前記導電性粒子とともに、前記支持体上に積層した粘着剤層から剥離する工程、
を含む、前記[20]に記載の異方導電性フィルム付き半導体ウェハの製造方法。
本実施の形態の異方導電性フィルム付き半導体チップは、片面(主面の少なくとも一方)に回路電極を複数有している半導体チップと、回路電極を覆う異方導電性フィルムを有する(図1参照)。
異方導電性フィルムの絶縁性樹脂成分には、硬化性樹脂や硬化剤を含むこともできる。
導電性粒子としては、球状のものを用いることが好ましく、その場合、真球に近いものがより好ましい。長軸に対する短軸の比は、0.5以上が好ましく、0.7以上がより好ましく、0.9以上がさらに好ましい。長軸に対する短軸の比の最大値は1である。
絶縁性粒子や充填剤等固形物を配合する場合、これらの最大直径は、導電性粒子の平均直径未満であることが好ましい。カップリング剤としては、エポキシ基、ケチミン基、ビニル基、アクリル基、アミノ基、イソシアネート基等含有シランカップリング剤が、密着性の観点から、好ましい。
また、該厚みは回路電極の平均高さの1.05倍~1.5倍であることが好ましい。異方導電性フィルムのタック性の制御、及び導電性粒子保持性の制御の観点から、該厚みは、回路電極の平均高さの1.05倍以上であることが好ましく、他方、接続時の導電性粒子の移動抑制の観点から、1.5倍以下であることが好ましい。
導電性粒子層の絶縁性樹脂の厚みは、導電性粒子の平均直径の0.4~2.0倍であることが好ましく、より好ましくは0.5~1.8倍であり、さらに好ましくは0.7~1.0倍である。導電性粒子層のタック性の制御、又は導電性粒子保持性の制御の観点から、該厚みは、0.4倍以上であることが好ましく、他方、接続安定性の観点から、2.0倍以下であることが好ましい。
熱カチオン硬化剤としては、芳香族スルホニウム塩型硬化剤が好ましい。熱カチオン硬化剤は、硬化性樹脂中に均一配合でき、触媒型で硬化できるため、低温、短時間での硬化が可能となり、溶剤安定性も良いため、好ましい。芳香族スルホニウム塩型硬化剤の陰イオンとしては、ヘキサフルオロアンチモネート、ヘキサフルオロホスフェート、テトラフルオロボレート、テトラキスペンタハロゲン化フェニルボレート等を用いることができるが、不純物イオンを低減できる点で、テトラキスペンタハロゲン化フェニルボレートが好ましく、テトラキスペンタフルオロフェニルボレートが特に好ましい。
また、絶縁性接着剤層には、帯電防止等のため、絶縁性が損なわれない範囲内で導電性粒子を添加してもよい。
また、導電性粒子は、全数の90%以上が単独で存在し、互いに凝集していないことが好ましい。凝集している場合であっても、凝集粒子は、4個以上の導電性粒子が凝集したものでないことが好ましい。
絶縁性接着剤層の樹脂成分の100℃における粘度、及び20℃~100℃における粘度の測定方法は、それぞれ、導電性粒子層の絶縁性樹脂の粘度の測定と同様の方法であることができる。導電性粒子層の絶縁性樹脂の100℃における粘度は、絶縁性接着剤層の樹脂成分の100℃における粘度の2倍~1000倍であることが好ましく、5倍~500倍の範囲がより好ましく、8倍~400倍の範囲がさらに好ましく、10倍~300倍の範囲が特に好ましい。該粘度比が2倍以上であれば、接続時に導電性粒子の流れ出しが抑制できる点で、好ましく、他方、接続抵抗安定化の観点から、1000倍以下であることが、好ましい。
方法1は、以下の工程:
支持体、導電性粒子が断面厚み方向において支持体側に偏在している異方導電性フィルム層、の順に積層してなる積層体に、片面に複数の回路電極を有する半導体チップの該回路電極面をラミネートする工程、及び
該ラミネートした該半導体チップを、該異方導電性フィルム層とともに、該支持体から剥離する工程、
を含む、異方導電性フィルム付き半導体チップの製造方法である(図3参照)。
前記異方導電性フィルム層は、絶縁性接着剤層と、前記導電性粒子が略平面状に1層分散配列した導電性粒子層を有することが、接続信頼性の観点から好ましい。
2軸延伸可能な支持体(支持フィルム)上に粘着層を形成し、粘着層上に導電性粒子を最密充填し、導電性粒子上に絶縁性樹脂ワニスを塗布、乾燥して導電性粒子充填樹脂シートを作製する。その後、該導電性粒子充填シートを2軸延伸することにより、支持体上に形成した導電性粒子層を得る。こうして得た導電性粒子層に、剥離シート上に形成した絶縁性接着剤層をラミネートし、剥離シートを除去することにより、支持体上に形成した異方導電性フィルムを得ることができる。また、導電性粒子が支持体上に分散配列した導電性粒子分散配列シートを作製し、こうして得た導電性粒子分散配列シートに、剥離フィルム上に別途形成した絶縁性樹脂シートをラミネートして、導電性粒子層を形成し、剥離フィルムを除去することにより、支持体上に形成した導電性粒子層を作製し、こうして得た導電性粒子層に、剥離シート上に別途形成した絶縁性接着剤層をラミネートし、該剥離シートを除去することにより、支持体上に形成した異方導電性フィルムを得ることも可能である。
方法2は、以下の工程:
片面に複数の回路電極を有する半導体チップの回路電極面に、絶縁性接着剤を充填する工程、
得られた絶縁性接着剤層付き半導体チップに、支持体上に形成され、かつ、絶縁性樹脂中に導電性粒子が略平面状に1層分散配列した導電性粒子層を、ラミネートする工程、
前記絶縁性接着剤層付き半導体チップを、前記導電性粒子層とともに、前記支持体から剥離する工程、
を含む、異方導電性フィルム付き半導体チップの製造方法である(図4参照)。導電性粒子層の形成方法としては、前記した方法を用いることができる。
方法3は、以下の工程:
片面に複数の回路電極を有する半導体チップの回路電極面に、絶縁性接着剤を充填する工程、
得られた絶縁性接着剤層付き半導体チップに、支持体上に積層した粘着剤層上に分散配列して形成された導電性粒子を、ラミネートする工程、
前記絶縁性接着剤層付き半導体チップを、前記導電性粒子とともに、前記支持体上に積層した粘着剤層から剥離する工程、
を含む、異方導電性フィルム付き半導体チップの製造方法である(図5参照)。支持体上に積層した粘着剤層上に分散配列して形成された導電性粒子の作製方法としては、前記した導電性粒子分散配列シートの作製方法を用いることができる。
本実施の形態の異方導電性フィルム付き半導体チップを、相対する電極を有する回路基板に圧着した際の、半導体チップ外周からの異方導電性フィルムのはみ出し量を指標するはみ出し長さは、接続電極高さの0.5~100倍の範囲にあることが好ましく、1~80倍の範囲がより好ましく、2倍~70倍の範囲がさらに好ましい。高密度実装の観点から、該はみ出し長さは、100倍以下であることが好ましく、電気的、機械的接続観点から、0.5倍以上であることが好ましい。圧着時のはみ出し量は、回路電極高さ、電極面積、異方導電性フィルム厚み、異方導電性フィルムのはみ出し量(長さ)、異方導電性フィルムの樹脂粘度、接続温度等を調整することにより制御することができる。
回路基板の接続電極以外の部分は、酸化ケイ素、窒化ケイ素、酸化窒化ケイ素、ポリイミド等の絶縁膜で覆われていることが好ましい。
本実施の形態の異方導電性フィルム付き半導体チップは、熱圧着前に、回路電極上の導電性粒子数を目視検査することが好ましい。目視検査することにより、導電性粒子の個数を予め確認することができ、また、異物混入等の異常も確認することが可能となる。
異方導電性フィルムの絶縁性樹脂成分には、硬化性樹脂や硬化剤を含むこともできる。
また、異方導電性フィルムには、異方導電性フィルム付き半導体チップに関して前記したものと同じ絶縁粒子、充填剤、軟化剤、硬化促進剤、安定剤、着色剤、難燃剤、流動調整剤、カップリング剤等をさらに含有することもできる。
異方導電性フィルムの、回路電極平均高さよりも表面側にある絶縁性樹脂成分の高さ(厚み)は、異方導電性フィルム付き半導体チップに関して前記したものと同じであることができる。
導電性粒子層の絶縁性樹脂の厚みは、異方導電性フィルム付き半導体チップに関して前記したものと同じであることができる。
本実施の形態の異方導電性フィルム中の全導電性粒子数の割合も、異方導電性フィルム付き半導体チップに関して前記したものと同じであることができる。また、導電性粒子は、異方導電性フィルムの表面から露出していることが好ましく、露出している1粒子当りの露出程度を指標する露出高さも、異方導電性フィルム付き半導体チップに関して、前記したものと同じであることができる。
本実施の形態に用いられる絶縁性接着剤も、異方導電性フィルム付き半導体チップに関して前記したものと同じであることができる。
導電性粒子の分散配列も、異方導電性フィルム付き半導体チップに関して前記したものと同じであることができる。
導電性粒子層は、異方導電性フィルム付き半導体チップに関して前記したような、導電性粒子と絶縁性樹脂からなり、硬化性樹脂や硬化剤を含むこともできる。
導電性粒子層の絶縁性樹脂成分の粘度も、異方導電性フィルム付き半導体チップに関して前記したようなものであることができる。
ここで、最も半導体チップに近い導電性粒子と、最も半導体チップに遠い導電性粒子の厚み方向の粒子間距離とは、半導体チップから最も遠い粒子の中心から、厚み方向に垂直に引いた仮想直線15と、半導体チップから最も近い粒子の中心から、厚み方向に垂直に引いた仮想直線16との距離を指す(図11参照)。
本実施の形態の半導体装置は、上記に規定した導電性粒子の配置を取ることで、信頼性試験後の接続抵抗、絶縁性に優れる。当該観点から、最も半導体チップに近い導電性粒子と、最も半導体チップに遠い導電性粒子の厚み方向の粒子間距離は、該導電性粒子の平均直径の0.9倍以下であることが好ましく、0.8倍以下であることがより好ましく、0.5倍以下であることがさらに好ましく、0.35倍以下であることが特に好ましい。上記距離の最小値は0倍である。
回路電極は、異方導電性フィルム付き半導体チップに関して前記したものと同じであることができる。
導電性粒子の平均直径は、接続しようとする隣接電極間距離よりも小さい必要があると同時に、接続する電子部品の電極高さのバラツキよりも大きいことが好ましい。そのため、導電性粒子の平均直径は、2.0μm以上50μm以下の範囲が好ましく、2.5μm以上40μm以下がより好ましく、3.0μm以上35μm以下がさらに好ましく、4.0μm以上30μm以下が特に好ましい。また、導電性粒子の粒子径分布の標準偏差は、平均直径の50%以下であることが好ましい。
本実施の形態の半導体装置の、回路電極上の単位面積当たりの導電性粒子数は、回路電極以外の部分の単位面積当たりの導電性粒子数の65%以上であることが好ましく、80%以上であることがより好ましく、90%以上であることがさらに好ましい。該導電性粒子数が65%以上であれば、接続性、絶縁性のバランスが取り易い点で、好ましい。
(半導体チップの作製)
縦横が1.6mm×15.1mmのシリコン片(厚み0.28mm)全面に酸化膜を形成し、外辺部から20μm内側に横58μm、縦120μmのアルミ薄膜(厚さ1000Å)をそれぞれが2μm間隔になるように長辺側に各々480個形成した。それらアルミ薄膜上に、10μm間隔になるように横20μm、縦100μmの金バンプ(厚み15μm)をそれぞれ2個ずつ形成するために、それぞれの金バンプ配置箇所の外周部から7μm内側に横6μm、縦86μmの開口部を残す以外の部分に酸化ケイ素/窒化ケイ素からなる厚み0.1μmの保護膜を形成した。その後、前記金バンプを形成し、半導体チップとした。回路電極である金バンプの、電極の配置されていない保護膜面を基準とした平均高さは、15.0μmであった。
検査性評価:該異方導電性フィルム付きウェハの異方導電性フィルム表面から、マイクロスコープを用いて、金バンプ上の導電性粒子数を計測した。計測可能なものをOK、計測不能なものをNGとして評価した。
検査結果評価:上記と同様の方法で、50バンプ分について接続バンプ上の導電性粒子数を計測し、標準偏差/平均値が0.3未満の場合を○、0.3以上の場合を×として評価した。
圧着後の金バンプ上の導電性粒子数を上記と同様に50バンプ分測定し、その平均捕捉粒子数と、接続前に計測した接続バンプ上の導電性粒子数の割合を算出した。65%以上90%未満の場合を○、90%以上の場合を◎、そして65%未満の場合を×として評価した。
厚み0.5mmの無アルカリガラス上に、半導体チップのアルミ薄膜上の金バンプが隣接するアルミ薄膜上の金バンプと対になる位置関係で接続されるようにタンタル配線(0.8μm)、次いで、インジウム錫酸化物膜(1400Å)の接続パッド(横42μm、縦120μm)を形成した。20個の金バンプが接続される毎に前記接続パッドにインジウム錫酸化物薄膜の引き出し配線を形成し、引き出し配線上はアルミチタン薄膜(チタン1%、3000Å)を形成し、接続評価基板とした。この接続評価基板の接続パッドと異方導電性フィルム付き半導体チップの金バンプを位置合わせし、又は、接続評価基板に異方導電性フィルムを仮圧着した後、接続評価基板の接続パッドと半導体チップの金バンプを位置合わせし、190℃、10秒間、40MPaの荷重で圧着し、半導体装置を作成した。圧着後、前記引き出し配線間(金バンプ20個のデイジーチェイン)の抵抗値四端子法の抵抗計で抵抗測定し、初期接続抵抗値とした。この接続抵抗測定基板を85℃、85%RHの環境下、500時間保持し、取り出して25℃、1時間放置後の接続抵抗値を測定し、信頼性試験後接続抵抗値とした。
厚み0.5mmの無アルカリガラス上に、半導体チップのアルミ薄膜上の2個の金バンプがそれぞれ接続されるような位置関係にタンタル配線(0.8μm)、次いで、インジウム錫酸化物膜(1400Å)の接続パッド(横42μm、縦120μm)を形成した。前記接続パッドを1個おきに5個接続できるようにインジウム錫酸化物薄膜の接続配線を形成した。それぞれの接続配線にインジウム錫酸化物薄膜(1400Å)の引き出し配線を形成し、引き出し配線上にアルミチタン薄膜(チタン1%、3000Å)を形成して絶縁性評価基板とした。この絶縁抵抗評価基板の接続パッドと異方導電性フィルム付き半導体チップの金バンプを位置合わせし、又は接続評価基板に異方導電性フィルムを仮圧着した後、接続評価基板の接続パッドと半導体チップの金バンプを位置合わせし、190℃、10秒間、40MPaの荷重で圧着し、絶縁抵抗試験基板とした。この絶縁抵抗試験基板を85℃、85%RHに保持しながら、低電圧低電流電源を用いて、対となる引き出し配線間に30Vの直流電圧を印加した。この配線間の絶縁抵抗を5分間毎に測定し、絶縁抵抗が10MΩ以下になるまでの時間を測定し、その値を絶縁低下時間とした。この絶縁低下時間が500時間未満の場合をNG、500時間以上の場合をOKとして評価した。
圧着装置にて圧着を行った際、アライメントマーク読み取りエラーがでた場合をNG、エラーがでない場合をOKとして評価した。エラーが出た場合、繰り返し操作を行い、正常圧着できるまでの回数を計測した。
上記接続抵抗試験によって作製した半導体装置の電極のうち、電極間距離が最も狭く、長辺方向の中心に最も近い電極間を、ターゲット断面試料作製装置(LEICA製 EM TXP)にて厚み方向に割断する。研磨紙で観察箇所近傍まで研磨後、得られた断面をブロードイオンビーム装置(日立製作所製 型番:E-3500)にて平滑化する。測定対象の割断面は、上記電極間で導電性粒子が5個以上含まれる割断面とした。その後割断面に蒸着装置(真空デバイス製 型番:HPC-1s Osmium coat)を用いてオスミウムを蒸着することにより、導電化処理を行った。断面観察には走査型電子顕微鏡(日立製作所製 型番:S-4700)を用いた。
電極間における、半導体チップから最も遠い粒子の中心から、厚み方向に垂直に引いた仮想直線と、半導体チップから最も近い粒子の中心から、厚み方向に垂直に引いた仮想直線の距離を測定し、最も半導体チップに近い導電性粒子と、最も半導体チップに遠い導電性粒子の厚み方向の粒子間距離とした。半導体チップからの距離は、当該割断面において、導電性粒子の中心からSi基板まで降ろした垂線の長さとした。
接着層A
フェノキシ樹脂(ガラス転移温度84℃、数平均分子量9500)90g、ビスフェノールA型液状エポキシ樹脂(エポキシ当量190、25℃粘度、14000mPa・s)10g、γ-グリシドキシプロピルトリエトキシシラン1.5g、及び酢酸エチル250gを混合し、導電性粒子層用絶縁性樹脂ワニスを得た。この導電性粒子層用絶縁性樹脂ワニスを、厚さ38μmの剥離処理したポリエチレンテレフタレートフィルム上に塗布し、60℃で15分間乾燥し、膜厚2.8μmの接着層Aを得た。同様の方法で粘度測定用のシートを作製し、レオメータ(60℃/分、昇温)で100℃粘度を測定したところ、35000Pa・sであった。
フェノキシ樹脂(ガラス転移温度91℃、数平均分子量11300)40g、ビスフェノールA型液状エポキシ樹脂(エポキシ当量190、25℃粘度、14000mPa・s)10g、及びγ-グリシドキシプロピルトリエトキシシラン1.0gを、酢酸エチル-トルエンの混合溶剤(混合比1:1)に溶解し、固形分50%溶液とした。マイクロカプセル型潜在性イミダゾール硬化剤を含有する液状エポキシ樹脂(マイクロカプセルの平均粒径5μm、活性温度123度、液状エポキシ樹脂)50g(液状エポキシ樹脂33.5g含有)を、前記固形分50%溶液に混合分散させた。その後、これを、厚さ38μmの剥離処理したポリエチレンテレフタレートフィルム上に塗布し、60℃、15分間送風乾燥し、厚さ16μmの絶縁性接着剤層Bを得た。同様の方法で粘度測定用のシートを作製し、レオメータ(60℃/分、昇温)で100℃粘度を測定したところ、450Pa・sであった。
厚さ100μmの無延伸共重合ポリプロピレンフィルム上に、粘着層としてニトリルゴムラテックス-メチルメタアクリレートのグラフト共重合体接着剤を4μmの厚みで塗布した。この粘着層付きポリプロピレンフィルムに、平均直径3.8μmの金めっきプラスチック粒子(アクリル樹脂、導電性粒子)を、該粘着剤表面に導電性粒子が複数層となるように敷き詰め、その後、過剰な導電性粒子を軟質ゴムからなるスクレバーで掻き落とすことで、ほぼ隙間無く単層充填した。充填率は80%であった。このフィルムを2軸延伸装置(東洋精機X6H-S、パンタグラフ方式のコーナーストレッチ型の2軸延伸装置)を用いて縦横にそれぞれ10個のチャックを用いて固定し、125℃、120秒予熱しその後、10%/秒の速度で2.4倍延伸して固定し導電性粒子分散配列シートCを得た。マイクロスコープを用いて、導電性粒子数を測定したところ、100μm×100μmの範囲内の導電性粒子数は134個であった。導電性粒子の平均粒子間隔は12.0μmであり、導電性粒子は略正三角形に分散配列しており、凝集粒子は0であった。
上記導電性粒子分散配列シートCの導電性粒子分散配列面に、接着層Aを積層し、80℃、0.4MPaの条件で真空ラミネートして導電性粒子層を作製し、ポリエチレンテレフタレートフィルムを剥がし、その剥離面に、絶縁性接着剤層Bを積層し、55℃、0.6MPaの条件で真空ラミネートし、その後ポリエチレンテレフタレートフィルムを剥がし、異方導電性フィルムDを得た。
上記異方導電性フィルムDの接着層A側に、上記半導体チップの金バンプ配置面側を真空ラミネート(55℃、1.0MPa)し、その後、異方導電性フィルムと共に半導体チップを粘着層付きポリプロピレンフィルムから剥離し、異方導電性フィルム付き半導体チップEを得た。
異方導電性フィルム付き半導体チップEの異方導電性フィルムの絶縁性樹脂成分の厚みを、レーザー顕微鏡で測定したところ、18.8μmであった。また、金バンプ上の異方導電性フィルムの絶縁性樹脂成分の厚みは、3.8μmであった。この異方導電性フィルム付き半導体チップEを凍結割断し、断面観察を行い、導電性粒子位置を50個分確認した。50個のうち50個がバンプの平均高さより表面側にあることを確認した。
導電性粒子層F
厚さ100μmの無延伸共重合ポリプロピレンフィルム上に、粘着層としてニトリルゴムラテックス-メチルメタアクリレートのグラフト共重合体接着剤を4μmの厚みで塗布した。この粘着層付きポリプロピレンフィルムに平均直径3.8μmの金めっきプラスチック粒子(アクリル樹脂、導電性粒子)を、該粘着剤表面に導電性粒子が複数層となるように敷き詰め、その後、過剰な導電性粒子を軟質ゴムからなるスクレバーで掻き落とすことで、ほぼ隙間無く単層充填した。充填率は80%であった。フェノキシ樹脂(ガラス転移温度84℃、数平均分子量9500)95g、ビスフェノールA型液状エポキシ樹脂(エポキシ当量190、25℃粘度14000mPa・s)5g、及びγ-グリシドキシプロピルトリエトキシシラン1.2g、メチルエチルケトン250gを混合し、導電性粒子層用絶縁性樹脂ワニスを得た。この導電性粒子層用絶縁性樹脂ワニスを、前記導電性粒子を敷き詰めたフィルム上に塗布し、60℃、15分間乾燥し、厚み11μmの導電性粒子充填フィルムを得た。
膜厚を18μmとする以外は、実施例1と同様にして絶縁性接着剤層を作製した。
この絶縁性接着剤層上に該半導体チップの金バンプ配置面側を真空ラミネート(55℃、1.0MPa)し、その後、絶縁性接着剤層と共に半導体チップをポリエチレンテレフタレートフィルムから剥離し、余分な絶縁性接着剤層を取り除き、絶縁性接着剤層付き半導体チップGを得た。
導電性粒子層F上に絶縁性接着剤層付き半導体チップGの絶縁性接着剤層面側をラミネート(55℃、1.0MPa)し、その後、導電性粒子層と共に絶縁性接着剤層付き半導体チップを粘着層付きポリプロピレンフィルムから剥離し、異方導電性フィルム付き半導体チップHを得た。
異方導電性フィルム付き半導体チップHの異方導電性フィルムの絶縁性樹脂成分の厚みを、レーザー顕微鏡で測定したところ、19.1μmであった。また金バンプ上の異方導電性フィルムの絶縁性樹脂成分の厚みは、4.1μmであった。この異方導電性フィルム付き半導体チップHを凍結割断し、断面観察を行い、導電性粒子位置を50個分確認した。50個のうち50個がバンプの平均高さより表面側にあることを確認した。
接着層Aの厚みを4.0μmとする以外は、実施例1と同様にして、異方導電性フィルム付き半導体チップIを得た。
異方導電性フィルム付き半導体チップIの異方導電性フィルムの絶縁性樹脂成分の厚みを、レーザー顕微鏡で測定したところ、19.8μmであった。また、金バンプ上の異方導電性フィルムの絶縁性樹脂成分の厚みは、4.8μmであった。この異方導電性フィルム付き半導体チップIを凍結割断し、断面観察を行い、導電性粒子位置を50個分確認した。50個のうち50個がバンプの平均高さより表面側にあることを確認した。
異方導電性フィルム付き半導体チップJ
膜厚を19.5μmとする以外は、実施例2と同様にして、絶縁性接着剤層付き半導体チップを作製し、実施例1と同様にして作製した導電性粒子分散配列シートC上に真空ラミネート(40℃、0.5MPa)し、その後、導電性粒子と共に絶縁性接着剤層付き半導体チップを粘着層付きポリプロピレンフィルムから剥離し、異方導電性フィルム付き半導体チップJを得た。
異方導電性フィルム付き半導体チップJの異方導電性フィルムの絶縁性樹脂成分の厚みを、レーザー顕微鏡で測定したところ、18.8μmであった。また、金バンプ上の異方導電性フィルムの絶縁性樹脂成分の厚みは、3.8μmであった。異方導電性フィルム表面から、マイクロスコープを用いて導電性粒子の表面からの露出量を測定した。導電性粒子50個を測定したところ、その全てが露出しており、平均露出高さは0.3μmであった。
膜厚を19μmとする以外は、実施例1と同様にして絶縁性接着剤層を作製し、実施例1と同様にして作製した導電性粒子分散配列シートC上にラミネート(50℃、0.5MPa)し、異方導電性フィルムKを得た。この異方導電性フィルムKを1.6mm幅にスリットした。接続評価基板上の接続電極が覆われ、基板側に導電粒子層が配置されるように、スリットした異方導電性フィルムKを80℃、1秒、0.2MPaで仮圧着した。接続抵抗試験、絶縁性試験評価については、接続評価基板に上記方法で仮圧着したものを使用し、半導体チップに異方導電性フィルムがついていない物を使用した以外は、他の実施例、比較例と同様の条件、方法で行った。
フェノキシ樹脂(ガラス転移温度91℃、数平均分子量11300)40g、ビスフェノールA型液状エポキシ樹脂(エポキシ当量190、25℃粘度、14000mPa・s)10g、及びγ-グリシドキシプロピルトリエトキシシラン1.0gを、酢酸エチル-トルエンの混合溶剤(混合比1:1)に溶解し、固形分50%溶液とした。マイクロカプセル型潜在性イミダゾール硬化剤を含有する液状エポキシ樹脂(マイクロカプセルの平均粒径5μm、活性温度123度、液状エポキシ樹脂)50g(液状エポキシ樹脂33.5g含有)を、前記固形分50%溶液に混合分散させ、異方導電性フィルム用ワニスを得た。この異方導電性フィルム用ワニスに、導電性粒子密度50000個/mm2となるよう平均直径3.8μmの金めっきプラスチック粒子(アクリル樹脂、導電性粒子)を加え、厚さ50μmのポリエチレンテレフタレートフィルム上に塗布し、60℃で15分間乾燥し、膜厚20μmの異方導電性フィルムLを得た。
この異方導電性フィルムL上に該半導体チップの金バンプ配置面側を真空ラミネート(55℃、1.0MPa)し、その後、異方導電性フィルムLと共に半導体チップをポリエチレンテレフタレートフィルムから剥離し、余分な異方導電性フィルムを取り除き、異方導電性フィルム付き半導体チップMを得た。
異方導電性フィルム付き半導体チップMの異方導電性フィルムの絶縁性樹脂成分の厚みを、レーザー顕微鏡で測定したところ、19.8μmであった。また、金バンプ上の異方導電性フィルムの絶縁性樹脂成分の厚みは、4.8μmであった。この半導体チップMを凍結割断し、断面観察を行った。導電性粒子は厚み方向にほぼ均一に分布していた。
異方導電性フィルム用ワニスに導電性粒子密度10000個/mm2となるよう平均直径3.8μmの金めっきプラスチック粒子(アクリル樹脂、導電性粒子)を加えた以外は、比較例2と同様にして異方導電性フィルムNを得た。この異方導電性フィルムN上に該半導体チップの金バンプ配置面側を真空ラミネート(55℃、1.0MPa)し、その後、異方導電性フィルムNと共に半導体チップをポリエチレンテレフタレートフィルムから剥離し、余分な異方導電性フィルムを取り除き、異方導電性フィルム付き半導体チップOを得た。
異方導電性フィルム付き半導体チップOの異方導電性フィルムの絶縁性樹脂成分の厚みを、レーザー顕微鏡で測定したところ、19.7μmであった。また、金バンプ上の異方導電性フィルムの絶縁性樹脂成分の厚みは、4.7μmであった。この半導体チップOを凍結割断し、断面観察を行った。導電性粒子は厚み方向にほぼ均一に分布していた。
6インチ径、厚み0.28mmのシリコンウェハ上に全面に酸化膜を形成し、切り出し後の外形数法が縦横1.6mm×15.1mmとなるチップを530個形成した。各々のチップエリアの外辺部から20μm内側に横58μm、縦120μmのアルミ薄膜(厚さ1000Å)をそれぞれが2μm間隔になるように長辺側に各々480個形成した。それらアルミ薄膜上に、10μm間隔になるように横20μm、縦100μmの金バンプ(厚み15μm)をそれぞれ2個ずつ形成するために、それぞれの金バンプ配置箇所の外周部から7μm内側に横6μm、縦86μmの開口部を残す以外の部分に酸化ケイ素/窒化ケイ素からなる厚み0.1μmの保護膜を形成した。その後、前記金バンプを形成した。その後、厚み0.28mmまで研磨し、裏面にダイシングフィルム(リンテック社製、D-650)を貼り付け、半導体ウェハとした。回路電極である金バンプの、電極の配置されていない保護膜面を基準とした平均高さは、15.0μmであった。
ダイシング装置(DISCO社製、DAD3350、ブレードNBC ZH2060、30000rpm、切削速度 50mm/s)を用いて、各実施例によって製造された異方導電性フィルム付き半導体ウェハを、530個のチップ(1.6mm×15.1mm)を切り出すようにダイシングした(ダイシングフィルムへの切り込み量、20μm)。ダイシングしたチップを評価用チップとした。
外観評価:切り出したチップにダイシング屑の付着のあるものが5%以上の場合を×、5%以下の場合を○として評価した。
剥がれ評価:切り出したチップのダイシング端面を観察し、ダイシング端面からの異方導電性フィルムの平均剥がれ量が25μm未満の場合を○、25μm以上の場合を×として評価した。
検査性評価:該異方導電性フィルム付きウェハの異方導電性フィルム表面から、マイクロスコープを用いて、金バンプ上の導電性粒子数を計測した。計測可能なものをOK、計測不能なものをNGとして評価した。
検査結果評価:上記と同様の方法で、50バンプ分について接続バンプ上の導電性粒子数を計測し、標準偏差/平均値が0.3未満の場合を○、0.3以上の場合を×として評価した。
圧着後の金バンプ上の導電性粒子数を上記と同様に50バンプ分測定し、その平均捕捉粒子数と、接続前に計測した接続バンプ上の導電性粒子数の割合を算出した。65%以上90%未満の場合を○、90%以上の場合を◎、そして65%未満の場合を×として評価した。
厚み0.5mmの無アルカリガラス上に、評価用チップのアルミ薄膜上の金バンプが隣接するアルミ薄膜上の金バンプと対になる位置関係で接続されるようにタンタル配線(0.8μm)、次いで、インジウム錫酸化物膜(1400Å)の接続パッド(横42μm、縦120μm)を形成した。20個の金バンプが接続される毎に前記接続パッドにインジウム錫酸化物薄膜の引き出し配線を形成し、引き出し配線上はアルミチタン薄膜(チタン1%、3000Å)を形成し、接続評価基板とした。この接続評価基板の接続パッドと異方導電性フィルム付き半導体チップの金バンプを位置合わせし、190℃、10秒間、40MPaの荷重で圧着した。圧着後、前記引き出し配線間(金バンプ20個のデイジーチェイン)の抵抗値四端子法の抵抗計で抵抗測定し、初期接続抵抗値とした。この接続抵抗測定基板を85℃、85%RHの環境下、500時間保持し、取り出して25℃、1時間放置後の接続抵抗値を測定し、信頼性試験後抵抗値とした。
厚み0.5mmの無アルカリガラス上に、評価用チップのアルミ薄膜上の2個の金バンプがそれぞれ接続されるような位置関係にタンタル配線(0.8μm)、次いで、インジウム錫酸化物膜(1400Å)の接続パッド(横42μm、縦120μm)を形成した。前記接続パッドを1個おきに5個接続できるようにインジウム錫酸化物薄膜の接続配線を形成した。それぞれの接続配線にインジウム錫酸化物薄膜(1400Å)の引き出し配線を形成し、引き出し配線上にアルミチタン薄膜(チタン1%、3000Å)を形成して絶縁性評価基板とした。この絶縁抵抗評価基板の接続パッドと異方導電性フィルム付き半導体チップの金バンプを位置合わせし、190℃、10秒間、40MPaの荷重で圧着し、絶縁抵抗試験基板とした。この絶縁抵抗試験基板を85℃、85%RHに保持しながら、低電圧低電流電源を用いて、対となる引き出し配線間に30Vの直流電圧を印加した。この配線間の絶縁抵抗を5分間毎に測定し、絶縁抵抗が10MΩ以下になるまでの時間を測定し、その値を絶縁低下時間とした。この絶縁低下時間が500時間未満の場合をNG、500時間以上の場合をOKとして評価した。
圧着装置にて圧着を行った際、アライメントマーク読み取りエラーがでた場合をNG、エラーがでない場合をOKとして評価した。エラーが出た場合、繰り返し操作を行い、正常圧着できるまでの回数を計測した。
接着層A
フェノキシ樹脂(ガラス転移温度84℃、数平均分子量9500)90g、ビスフェノールA型液状エポキシ樹脂(エポキシ当量190、25℃粘度、14000mPa・s)10g、γ-グリシドキシプロピルトリエトキシシラン1.5g、及び酢酸エチル250gを混合し、導電性粒子層用絶縁性樹脂ワニスを得た。この導電性粒子層用絶縁性樹脂ワニスを、厚さ38μmの剥離処理したポリエチレンテレフタレートフィルム上に塗布し、60℃で15分間乾燥し、膜厚2.8μmの接着層Aを得た。同様の方法で粘度測定用のシートを作製し、レオメータ(60℃/分、昇温)で100℃粘度を測定したところ、35000Pa・sであった。
フェノキシ樹脂(ガラス転移温度91℃、数平均分子量11300)40g、ビスフェノールA型液状エポキシ樹脂(エポキシ当量190、25℃粘度、14000mPa・s)10g、及びγ-グリシドキシプロピルトリエトキシシラン1.0gを、酢酸エチル-トルエンの混合溶剤(混合比1:1)に溶解し、固形分50%溶液とした。マイクロカプセル型潜在性イミダゾール硬化剤を含有する液状エポキシ樹脂(マイクロカプセルの平均粒径5μm、活性温度123度、液状エポキシ樹脂)50g(液状エポキシ樹脂33.5g含有)を、前記固形分50%溶液に混合分散させた。その後、これを、厚さ38μmの剥離処理したポリエチレンテレフタレートフィルム上に塗布し、60℃、15分間送風乾燥し、厚さ16μmの絶縁性接着剤層Bを得た。同様の方法で粘度測定用のシートを作製し、レオメータ(60℃/分、昇温)で100℃粘度を測定したところ、450Pa・sであった。
厚さ100μmの無延伸共重合ポリプロピレンフィルム上に、粘着層としてニトリルゴムラテックス-メチルメタアクリレートのグラフト共重合体接着剤を4μmの厚みで塗布した。この粘着層付きポリプロピレンフィルムに、平均直径3.8μmの金めっきプラスチック粒子(アクリル樹脂、導電性粒子)を、該粘着剤表面に導電性粒子が複数層となるように敷き詰め、その後、過剰な導電性粒子を軟質ゴムからなるスクレバーで掻き落とすことで、ほぼ隙間無く単層充填した。充填率は80%であった。このフィルムを2軸延伸装置(東洋精機X6H-S、パンタグラフ方式のコーナーストレッチ型の2軸延伸装置)を用いて縦横にそれぞれ10個のチャックを用いて固定し、125℃、120秒予熱しその後、10%/秒の速度で2.4倍延伸して固定し導電性粒子分散配列シートCを得た。マイクロスコープを用いて、導電性粒子数を測定したところ、100μm×100μmの範囲内の導電性粒子数は134個であった。導電性粒子の平均粒子間隔は12.0μmであり、導電性粒子は略正三角形に分散配列しており、凝集粒子は0であった。
上記導電性粒子分散配列シートCの導電性粒子分散配列面に、接着層Aを積層し、80℃、0.4MPaの条件で真空ラミネートして導電性粒子層を作製し、ポリエチレンテレフタレートフィルムを剥がし、その剥離面に、絶縁性接着剤層Bを積層し、55℃、0.6MPaの条件で真空ラミネートし、その後ポリエチレンテレフタレートフィルムを剥がし、異方導電性フィルムDを得た。
上記異方導電性フィルムD上に、上記半導体ウェハの金バンプ配置面側を真空ラミネート(55℃、1.0MPa)し、その後、異方導電性フィルムと共に半導体ウェハを粘着層付きポリプロピレンフィルムから剥離し、異方導電性フィルム付き半導体ウェハEを得た。
異方導電性フィルム付き半導体ウェハEの異方導電性フィルムの絶縁性樹脂成分の厚みを、レーザー顕微鏡で測定したところ、18.8μmであった。また、金バンプ上の異方導電性フィルムの絶縁性樹脂成分の厚みは、3.8μmであった。この異方導電性フィルム付き半導体ウェハEを凍結割断し、断面観察を行い、導電性粒子位置を50個分確認した。50個のうち50個がバンプの平均高さより表面側にあることを確認した。
導電性粒子層F
厚さ100μmの無延伸共重合ポリプロピレンフィルム上に、粘着層としてニトリルゴムラテックス-メチルメタアクリレートのグラフト共重合体接着剤を4μmの厚みで塗布した。この粘着層付きポリプロピレンフィルムに平均直径3.8μmの金めっきプラスチック粒子(アクリル樹脂、導電性粒子)を、該粘着剤表面に導電性粒子が複数層となるように敷き詰め、その後、過剰な導電性粒子を軟質ゴムからなるスクレバーで掻き落とすことで、ほぼ隙間無く単層充填した。充填率は80%であった。フェノキシ樹脂(ガラス転移温度84℃、数平均分子量9500)95g、ビスフェノールA型液状エポキシ樹脂(エポキシ当量190、25℃粘度14000mPa・s)5g、及びγ-グリシドキシプロピルトリエトキシシラン1.2g、メチルエチルケトン250gを混合し、導電性粒子層用絶縁性樹脂ワニスを得た。この導電性粒子層用絶縁性樹脂ワニスを、前記導電性粒子を敷き詰めたフィルム上に塗布し、60℃、15分間乾燥し、厚み11μmの導電性粒子充填フィルムを得た。
膜厚を18μmとする以外は、実施例1と同様にして絶縁性接着剤層を作製した。
この絶縁性接着剤層上に該半導体ウェハの金バンプ配置面側を真空ラミネート(55℃、1.0MPa)し、その後、絶縁性接着剤層と共に半導体ウェハをポリエチレンテレフタレートフィルムから剥離し、余分な絶縁性接着剤層を取り除き、絶縁性接着剤層付き半導体ウェハGを得た。
導電性粒子層F上に絶縁性接着剤層付き半導体ウェハGの絶縁性接着剤層面側をラミネート(55℃、1.0MPa)し、その後、導電性粒子層と共に絶縁性接着剤層付き半導体ウェハを粘着層付きポリプロピレンフィルムから剥離し、異方導電性フィルム付き半導体ウェハHを得た。
異方導電性フィルム付き半導体ウェハHの異方導電性フィルムの絶縁性樹脂成分の厚みを、レーザー顕微鏡で測定したところ、19.0μmであった。また金バンプ上の異方導電性フィルムの絶縁性樹脂成分の厚みは、4.0μmであった。この異方導電性フィルム付き半導体ウェハHを凍結割断し、断面観察を行い、導電性粒子位置を50個分確認した。50個のうち50個がバンプの平均高さより表面側にあることを確認した。
接着層Aの厚みを4.0μmとする以外は、実施例1と同様にして、異方導電性フィルム付き半導体ウェハIを得た。
異方導電性フィルム付き半導体ウェハIの異方導電性フィルムの絶縁性樹脂成分の厚みを、レーザー顕微鏡で測定したところ、19.8μmであった。また、金バンプ上の異方導電性フィルムの絶縁性樹脂成分の厚みは、4.8μmであった。この異方導電性フィルム付き半導体ウェハIを凍結割断し、断面観察を行い、導電性粒子位置を50個分確認した。50個のうち50個がバンプの平均高さより表面側にあることを確認した。
異方導電性フィルム付き半導体ウェハJ
膜厚を19.5μmとする以外は、実施例2と同様にして、絶縁性接着剤層付き半導体ウェハを作製し、実施例1と同様にして作製した導電性粒子分散配列シートC上に真空ラミネート(40℃、0.5MPa)し、その後、導電性粒子と共に絶縁性接着剤層付き半導体ウェハを粘着層付きポリプロピレンフィルムから剥離し、異方導電性フィルム付き半導体ウェハJを得た。
異方導電性フィルム付き半導体ウェハJの異方導電性フィルムの絶縁性樹脂成分の厚みを、レーザー顕微鏡で測定したところ、18.7μmであった。また、金バンプ上の異方導電性フィルムの絶縁性樹脂成分の厚みは、3.7μmであった。異方導電性フィルム表面から、マイクロスコープを用いて導電性粒子の表面からの露出量を測定した。導電性粒子50個を測定したところ、その全てが露出しており、平均露出高さは0.25μmであった。
フェノキシ樹脂(ガラス転移温度91℃、数平均分子量11300)40g、ビスフェノールA型液状エポキシ樹脂(エポキシ当量190、25℃粘度、14000mPa・s)10g、及びγ-グリシドキシプロピルトリエトキシシラン1.0gを、酢酸エチル-トルエンの混合溶剤(混合比1:1)に溶解し、固形分50%溶液とした。マイクロカプセル型潜在性イミダゾール硬化剤を含有する液状エポキシ樹脂(マイクロカプセルの平均粒径5μm、活性温度123度、液状エポキシ樹脂)50g(液状エポキシ樹脂33.5g含有)を、前記固形分50%溶液に混合分散させ、異方導電性フィルム用ワニスを得た。この異方導電性フィルム用ワニスに、導電性粒子密度50000個/mm2となるよう平均直径3.8μmの金めっきプラスチック粒子(アクリル樹脂、導電性粒子)を加え、厚さ50μmのポリエチレンテレフタレートフィルム上に塗布し、60℃で15分間乾燥し、膜厚20μmの異方導電性フィルムKを得た。
この異方導電性フィルムK上に該半導体ウェハの金バンプ配置面側を真空ラミネート(55℃、1.0MPa)し、その後、異方導電性フィルムKと共に半導体ウェハをポリエチレンテレフタレートフィルムから剥離し、余分な異方導電性フィルムを取り除き、異方導電性フィルム付き半導体ウェハLを得た。
異方導電性フィルム付き半導体ウェハLの異方導電性フィルムの絶縁性樹脂成分の厚みを、レーザー顕微鏡で測定したところ、19.7μmであった。また、金バンプ上の異方導電性フィルムの絶縁性樹脂成分の厚みは、4.7μmであった。この半導体ウェハLを凍結割断し、断面観察を行った。導電性粒子は厚み方向に偏在なく、ほぼ均一に分布していた。
異方導電性フィルム用ワニスに導電性粒子密度10000個/mm2となるよう平均直径3.8μmの金めっきプラスチック粒子(アクリル樹脂、導電性粒子)を加えた以外は、比較例1と同様にして異方導電性フィルムMを得た。この異方導電性フィルムM上に該半導体チップの金バンプ配置面側を真空ラミネート(55℃、1.0MPa)し、その後、異方導電性フィルムMと共に半導体ウェハをポリエチレンテレフタレートフィルムから剥離し、余分な異方導電性フィルムを取り除き、異方導電性フィルム付き半導体ウェハNを得た。
異方導電性フィルム付き半導体ウェハNの異方導電性フィルムの絶縁性樹脂成分の厚みを、レーザー顕微鏡で測定したところ、19.8μmであった。また、金バンプ上の異方導電性フィルムの絶縁性樹脂成分の厚みは、4.8μmであった。この半導体ウェハNを凍結割断し、断面観察を行った。導電性粒子は厚み方向に偏在なく、ほぼ均一に分布していた。
2 回路電極
3 異方導電性フィルム
4 導電性粒子
5 絶縁性接着剤層
6 導電性粒子層
7 支持体
8 粘着剤層
9 半導体ウェハ
10 接着剤
11 回路基板
12 接続電極
13 半導体素子部
14 Si基板
15 半導体チップから最も遠い粒子の中心から、厚み方向に垂直に引いた仮想直線
16 半導体チップから最も近い粒子の中心から、厚み方向に垂直に引いた仮想直線
Claims (36)
- 片面に複数の回路電極を有する半導体チップと、該回路電極を覆う異方導電性フィルムとを有する異方導電性フィルム付き半導体チップであって、該異方導電性フィルムは、絶縁性樹脂成分と導電性粒子とを含み、かつ、該異方導電性フィルムに含まれる全導電性粒子数の60%以上が、該回路電極の平均高さよりも該異方導電性フィルムの表面側に存在することを特徴とする、前記異方導電性フィルム付き半導体チップ。
- 前記異方導電性フィルムの、前記回路電極の平均高さよりも表面側にある絶縁性樹脂成分の高さが、前記導電性粒子の平均直径の1.0倍~2.0倍である、請求項1に記載の異方導電性フィルム付き半導体チップ。
- 前記異方導電性フィルムが、前記回路電極を覆う絶縁性接着剤層と導電性粒子層とを有し、該導電性粒子層は、絶縁性樹脂中に前記導電性粒子が略平面状に1層分散配列している、請求項1又は2に記載の異方導電性フィルム付き半導体チップ。
- 前記絶縁性接着剤層の樹脂成分の粘度が、20℃~100℃の温度範囲において、前記導電性粒子層の絶縁性樹脂の粘度よりも低い、請求項3に記載の異方導電性フィルム付き半導体チップ。
- 前記導電性粒子層の絶縁性樹脂の厚みが、前記導電性粒子の平均直径の0.4~2.0倍である、請求項3又は4に記載の異方導電性フィルム付き半導体チップ。
- 前記導電性粒子層中の全導電性粒子数の90%以上が単独で存在し、隣接する導電性粒子間の平均粒子間距離が、該導電性粒子の平均直径の1.0~20倍である、請求項3~5のいずれか1項に記載の異方導電性フィルム付き半導体チップ。
- 前記全導電性粒子数の70%以上が、前記異方導電性フィルムの表面からその一部を露出している、請求項1~6のいずれか1項に記載の異方導電性フィルム付き半導体チップ。
- 前記導電性粒子は、平均直径2~50μmの略球状の粒子であり、かつ、プラスチック製の粒子に金属被覆した粒子、金属粒子、合金粒子、及び金属製の粒子若しくは合金製の粒子に金属若しくは合金を被覆した粒子からなる群から選ばれる、請求項1~7のいずれか1項に記載の異方導電性フィルム付き半導体チップ。
- 前記半導体チップの外形からの前記異方導電性フィルムの最大はみ出し長が、50μm以下である、請求項1~8のいずれか1項に記載の異方導電性フィルム付き半導体チップ。
- 以下の工程:
支持体、導電性粒子が断面厚み方向において支持体側に偏在している異方導電性フィルム層、の順に積層してなる積層体に、片面に複数の回路電極を有する半導体チップの該回路電極面をラミネートする工程、及び
該ラミネートした該半導体チップを、該異方導電性フィルム層とともに、該支持体から剥離する工程、
を含む、請求項1に記載の異方導電性フィルム付き半導体チップの製造方法。 - 前記異方導電性フィルム層が、絶縁性接着剤層と導電性粒子層とを有し、該導電性粒子層は、絶縁性樹脂中に前記導電性粒子が略平面状に1層分散配列している、請求項10に記載の方法。
- 以下の工程:
片面に複数の回路電極を有する半導体チップの回路電極面に、絶縁性接着剤を充填する工程、
得られた絶縁性接着剤層付き半導体チップに、支持体上に形成され、かつ、絶縁性樹脂中に導電性粒子が略平面状に1層分散配列した導電性粒子層を、ラミネートする工程、
前記絶縁性接着剤層付き半導体チップを、前記導電性粒子層とともに、前記支持体から剥離する工程、
を含む、請求項3に記載の異方導電性フィルム付き半導体チップの製造方法。 - 以下の工程:
片面に複数の回路電極を有する半導体チップの回路電極面に、絶縁性接着剤を充填する工程、
得られた絶縁性接着剤層付き半導体チップに、支持体上に積層した粘着剤層上に分散配列して形成された導電性粒子を、ラミネートする工程、
前記絶縁性接着剤層付き半導体チップを、前記導電性粒子とともに、前記支持体上に積層した粘着剤層から剥離する工程、
を含む、請求項3に記載の異方導電性フィルム付き半導体チップの製造方法。 - 前記ラミネートする工程において、20℃~100℃で真空ラミネートする、請求項10~13のいずれか1項に記載の方法。
- 請求項1~9のいずれか1項に記載の異方導電性フィルム付き半導体チップの回路電極を、対応する接続電極を有する回路基板と、位置合わせして熱圧着する工程を含む、半導体装置の製造方法。
- 前記熱圧着する工程の前に、前記回路電極上の導電性粒子数を目視検査する工程を含む、請求項15に記載の方法。
- 前記熱圧着後の前記接続電極上の単位面積当たりの導電性粒子数が、前記回路電極以外の部分の単位面積あたりの導電性粒子数の65%以上である、請求項15又は16に記載の方法により製造された半導体装置。
- 片面に複数の回路電極を有する半導体ウェハと、該回路電極を覆う異方導電性フィルムとを有する異方導電性フィルム付き半導体ウェハであって、該異方導電性フィルムは、絶縁性樹脂成分と導電性粒子とを含み、かつ、該異方導電性フィルムに含まれる全導電性粒子数の60%以上が、該回路電極の平均高さよりも該異方導電性フィルムの表面側に存在することを特徴とする、前記異方導電性フィルム付き半導体ウェハ。
- 前記異方導電性フィルムの、前記回路電極の平均高さよりも表面側にある絶縁性樹脂成分の高さが、前記導電性粒子の平均直径の1.0倍~2.0倍である、請求項18に記載の異方導電性フィルム付き半導体ウェハ。
- 前記異方導電性フィルムが、前記回路電極を覆う絶縁性接着剤層と導電性粒子層とを有し、該導電性粒子層は、絶縁性樹脂中に前記導電性粒子が略平面状に1層分散配列している、請求項18又は19に記載の異方導電性フィルム付き半導体ウェハ。
- 前記絶縁性接着剤層の樹脂成分の粘度が、20℃~100℃の温度範囲において、前記導電性粒子層の絶縁性樹脂の粘度よりも低い、請求項20に記載の異方導電性フィルム付き半導体ウェハ。
- 前記導電性粒子層の絶縁性樹脂の厚みが、前記導電性粒子の平均直径の0.4~2.0倍である、請求項20又は21に記載の異方導電性フィルム付き半導体ウェハ。
- 前記導電性粒子層中の全導電性粒子数の90%以上が単独で存在し、隣接する導電性粒子間の平均粒子間距離が、該導電性粒子の平均直径の1.0~20倍である、請求項20~22のいずれか1項に記載の異方導電性フィルム付き半導体ウェハ。
- 前記全導電性粒子数の70%以上が、前記異方導電性フィルムの表面からその一部を露出している、請求項18~23のいずれか1項に記載の異方導電性フィルム付き半導体ウェハ。
- 前記導電性粒子は、平均直径2~50μmの略球状の粒子であり、かつ、プラスチック製の粒子に金属被覆した粒子、金属粒子、合金粒子、及び金属製の粒子若しくは合金製の粒子に金属若しくは合金を被覆した粒子からなる群から選ばれる、請求項18~24のいずれか1項に記載の異方導電性フィルム付き半導体ウェハ。
- 以下の工程:
支持体、導電性粒子が断面厚み方向において支持体側に偏在している異方導電性フィルム層、の順に積層してなる積層体に、片面に複数の回路電極を有する半導体ウェハの該回路電極面をラミネートする工程、及び
該ラミネートした該半導体ウェハを、該異方導電性フィルム層とともに、該支持体から剥離する工程、
を含む、請求項18に記載の異方導電性フィルム付き半導体ウェハの製造方法。 - 前記異方導電性フィルム層が、絶縁性接着剤層と導電性粒子層とを有し、該導電性粒子層は、絶縁性樹脂中に前記導電性粒子が略平面状に1層分散配列している、請求項26に記載の方法。
- 以下の工程:
片面に複数の回路電極を有する半導体ウェハの回路電極面に、絶縁性接着剤を充填する工程、
得られた絶縁性接着剤層付き半導体ウェハに、支持体上に形成され、かつ、絶縁性樹脂中に導電性粒子が略平面状に1層分散配列した導電性粒子層を、ラミネートする工程、
前記絶縁性接着剤層付き半導体ウェハを、前記導電性粒子層とともに、前記支持体から剥離する工程、
を含む、請求項20に記載の異方導電性フィルム付き半導体ウェハの製造方法。 - 以下の工程:
片面に複数の回路電極を有する半導体ウェハの回路電極面に、絶縁性接着剤を充填する工程、
得られた絶縁性接着剤層付き半導体ウェハに、支持体上に積層した粘着剤層上に分散配列して形成された導電性粒子を、ラミネートする工程、
前記絶縁性接着剤層付き半導体ウェハを、前記導電性粒子とともに、前記支持体上に積層した粘着剤層から剥離する工程、
を含む、請求項20に記載の異方導電性フィルム付き半導体ウェハの製造方法。 - 前記ラミネートする工程において、20℃~100℃で真空ラミネートする、請求項26~29のいずれか1項に記載の方法。
- 請求項18~25のいずれか1項に記載の異方導電性フィルム付き半導体ウェハをダイシングする工程を含む、異方導電性フィルム付き半導体チップの製造方法。
- 前記異方導電性フィルム付き半導体ウェハをダイシングする工程の前に、前記回路電極上の導電性粒子数を目視検査する工程を含む、請求項31に記載の方法。
- 片面に複数の回路電極を有する半導体チップと、該回路電極に対応する接続電極を有する回路基板と、接着剤とを含む半導体装置であって、該接着剤は絶縁性樹脂と導電性粒子を含み、該半導体チップと該回路基板との間に配置され、該半導体チップ上の、距離が一番短い回路電極間の、厚み方向に割断した断面における、最も半導体チップに近い導電性粒子と、最も半導体チップに遠い導電性粒子の厚み方向の粒子間距離が、該導電性粒子の平均直径の1倍以下である、半導体装置。
- 前記導電性粒子は、平均直径2~50μmの略球状の粒子であり、かつ、プラスチック製の粒子に金属被覆した粒子、金属粒子、合金粒子、及び金属製の粒子若しくは合金製の粒子に金属若しくは合金を被覆した粒子からなる群から選ばれる、請求項33に記載の半導体装置。
- 前記半導体チップの外形からの前記接着剤の最大はみ出し長が、50μm以下である、請求項33又は34に記載の半導体装置。
- 前記熱圧着後の前記接続電極上の単位面積当たりの導電性粒子数が、前記回路電極以外の部分の単位面積あたりの導電性粒子数の65%以上である、請求項33~35のいずれか1項に記載の半導体装置。
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---|---|---|---|---|
WO2015108025A1 (ja) * | 2014-01-16 | 2015-07-23 | デクセリアルズ株式会社 | 接続体、接続体の製造方法、接続方法、異方性導電接着剤 |
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Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10125725A (ja) * | 1996-10-18 | 1998-05-15 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2009016133A (ja) * | 2007-07-03 | 2009-01-22 | Sony Chemical & Information Device Corp | 異方性導電膜及びその製造方法、並びに接合体 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3417110B2 (ja) * | 1994-12-30 | 2003-06-16 | カシオ計算機株式会社 | 電子部品の接続方法 |
KR100273499B1 (ko) * | 1995-05-22 | 2001-01-15 | 우찌가사끼 이사오 | 배선기판에전기접속된반도체칩을갖는반도체장치 |
JP4574631B2 (ja) * | 1996-08-06 | 2010-11-04 | 日立化成工業株式会社 | マルチチップ実装法 |
WO2000033375A1 (en) * | 1998-12-02 | 2000-06-08 | Seiko Epson Corporation | Anisotropic conductor film, semiconductor chip, and method of packaging |
JP3684886B2 (ja) * | 1998-12-17 | 2005-08-17 | セイコーエプソン株式会社 | 半導体チップの実装構造、液晶装置及び電子機器 |
KR100650284B1 (ko) * | 2005-02-22 | 2006-11-27 | 제일모직주식회사 | 도전성능이 우수한 고분자 수지 미립자, 전도성 미립자 및이를 포함한 이방 전도성 접속재료 |
JP2007217503A (ja) * | 2006-02-15 | 2007-08-30 | Asahi Kasei Electronics Co Ltd | 異方導電性接着フィルム |
EP2073316A4 (en) * | 2006-09-26 | 2010-07-21 | Hitachi Chemical Co Ltd | ANISOTROPIC CONDUCTIVE ADHESIVE COMPOSITION, ANISOTROPIC CONDUCTIVE FILM, CIRCUIT ELEMENT CONNECTION STRUCTURE, AND METHOD OF MANUFACTURING COATED PARTICLES |
KR100838647B1 (ko) * | 2007-07-23 | 2008-06-16 | 한국과학기술원 | Acf/ncf 이중층을 이용한 웨이퍼 레벨 플립칩패키지의 제조방법 |
JP5192194B2 (ja) * | 2007-07-26 | 2013-05-08 | デクセリアルズ株式会社 | 接着フィルム |
JP2009147231A (ja) * | 2007-12-17 | 2009-07-02 | Hitachi Chem Co Ltd | 実装方法、半導体チップ、及び半導体ウエハ |
-
2012
- 2012-12-13 CN CN201280061980.5A patent/CN103988289A/zh active Pending
- 2012-12-13 KR KR1020147015696A patent/KR20140100511A/ko not_active Application Discontinuation
- 2012-12-13 WO PCT/JP2012/082413 patent/WO2013089199A1/ja active Application Filing
- 2012-12-13 JP JP2013549317A patent/JPWO2013089199A1/ja active Pending
- 2012-12-14 TW TW101147680A patent/TWI541958B/zh active
-
2015
- 2015-05-15 JP JP2015100484A patent/JP2015159333A/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10125725A (ja) * | 1996-10-18 | 1998-05-15 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2009016133A (ja) * | 2007-07-03 | 2009-01-22 | Sony Chemical & Information Device Corp | 異方性導電膜及びその製造方法、並びに接合体 |
Cited By (29)
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US10424538B2 (en) | 2013-10-15 | 2019-09-24 | Dexerials Corporation | Anisotropic conductive film |
WO2015108025A1 (ja) * | 2014-01-16 | 2015-07-23 | デクセリアルズ株式会社 | 接続体、接続体の製造方法、接続方法、異方性導電接着剤 |
JP2015135878A (ja) * | 2014-01-16 | 2015-07-27 | デクセリアルズ株式会社 | 接続体、接続体の製造方法、接続方法、異方性導電接着剤 |
US10175544B2 (en) | 2014-01-16 | 2019-01-08 | Dexerials Corporation | Connection body, method for manufacturing a connection body, connecting method and anisotropic conductive adhesive agent |
CN105917529B (zh) * | 2014-01-16 | 2020-02-21 | 迪睿合株式会社 | 连接体、连接体的制造方法、连接方法、各向异性导电粘接剂 |
CN111508855A (zh) * | 2014-01-16 | 2020-08-07 | 迪睿合株式会社 | 连接体及其制造方法、连接方法、各向异性导电粘接剂 |
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JP2015149451A (ja) * | 2014-02-07 | 2015-08-20 | デクセリアルズ株式会社 | アライメント方法、電子部品の接続方法、接続体の製造方法、接続体、異方性導電フィルム |
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WO2015119093A1 (ja) * | 2014-02-07 | 2015-08-13 | デクセリアルズ株式会社 | アライメント方法、電子部品の接続方法、接続体の製造方法、接続体、異方性導電フィルム |
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CN103988289A (zh) | 2014-08-13 |
JPWO2013089199A1 (ja) | 2015-04-27 |
KR20140100511A (ko) | 2014-08-14 |
TWI541958B (zh) | 2016-07-11 |
TW201332070A (zh) | 2013-08-01 |
JP2015159333A (ja) | 2015-09-03 |
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