TWI541958B - A semiconductor wafer having an anisotropic conductive film, a semiconductor wafer having an anisotropic conductive film, and a semiconductor device - Google Patents

A semiconductor wafer having an anisotropic conductive film, a semiconductor wafer having an anisotropic conductive film, and a semiconductor device Download PDF

Info

Publication number
TWI541958B
TWI541958B TW101147680A TW101147680A TWI541958B TW I541958 B TWI541958 B TW I541958B TW 101147680 A TW101147680 A TW 101147680A TW 101147680 A TW101147680 A TW 101147680A TW I541958 B TWI541958 B TW I541958B
Authority
TW
Taiwan
Prior art keywords
semiconductor wafer
conductive film
anisotropic conductive
layer
conductive particles
Prior art date
Application number
TW101147680A
Other languages
English (en)
Other versions
TW201332070A (zh
Inventor
Hideaki Tamaya
Akira Otani
Tokihiro Nematsu
Original Assignee
Asahi Kasei E Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asahi Kasei E Materials Corp filed Critical Asahi Kasei E Materials Corp
Publication of TW201332070A publication Critical patent/TW201332070A/zh
Application granted granted Critical
Publication of TWI541958B publication Critical patent/TWI541958B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09JADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J7/00Adhesives in the form of films or foils
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09JADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J7/00Adhesives in the form of films or foils
    • C09J7/10Adhesives in the form of films or foils without carriers
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09JADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J9/00Adhesives characterised by their physical nature or the effects produced, e.g. glue sticks
    • C09J9/02Electrically-conducting adhesives
    • CCHEMISTRY; METALLURGY
    • C08ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08KUse of inorganic or non-macromolecular organic substances as compounding ingredients
    • C08K2201/00Specific properties of additives
    • C08K2201/001Conductive additives
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09JADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J2301/00Additional features of adhesives in the form of films or foils
    • C09J2301/30Additional features of adhesives in the form of films or foils characterized by the chemical, physicochemical or physical properties of the adhesive or the carrier
    • C09J2301/314Additional features of adhesives in the form of films or foils characterized by the chemical, physicochemical or physical properties of the adhesive or the carrier the adhesive layer and/or the carrier being conductive
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09JADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J2301/00Additional features of adhesives in the form of films or foils
    • C09J2301/40Additional features of adhesives in the form of films or foils characterized by the presence of essential components
    • C09J2301/408Additional features of adhesives in the form of films or foils characterized by the presence of essential components additives as essential feature of the adhesive layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13184Tungsten [W] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/27001Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/27003Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the layer preform
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/274Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2743Manufacturing methods by blanket deposition of the material of the layer connector in solid form
    • H01L2224/27436Lamination of a preform, e.g. foil, sheet or layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/274Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2743Manufacturing methods by blanket deposition of the material of the layer connector in solid form
    • H01L2224/27442Manufacturing methods by blanket deposition of the material of the layer connector in solid form using a powder
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/279Methods of manufacturing layer connectors involving a specific sequence of method steps
    • H01L2224/27901Methods of manufacturing layer connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29075Plural core members
    • H01L2224/2908Plural core members being stacked
    • H01L2224/29082Two-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/2929Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29301Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29309Indium [In] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29301Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29311Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29301Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29316Lead [Pb] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29317Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/29318Zinc [Zn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29317Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/29324Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29344Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29347Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29355Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29363Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29364Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/2939Base material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29399Coating material
    • H01L2224/294Coating material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29499Shape or distribution of the fillers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731Location prior to the connecting process
    • H01L2224/73101Location prior to the connecting process on the same surface
    • H01L2224/73103Bump and layer connectors
    • H01L2224/73104Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901Pressing the bump connector against the bonding areas by means of another connector
    • H01L2224/81903Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9211Parallel connecting processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/0781Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811Extrinsic, i.e. with electrical conductive fillers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788Glasses, e.g. amorphous oxides, nitrides or fluorides

Landscapes

  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Non-Insulated Conductors (AREA)
  • Adhesive Tapes (AREA)
  • Adhesives Or Adhesive Processes (AREA)

Description

附各向異性導電性膜之半導體晶片、附各向異性導電性膜之半導體晶圓及半導體裝置
本發明係關於:一種附各向異性導電性膜之半導體晶片,其係將用於將半導體晶片之電極與相對之電路基板上之電極彼此電性連接的各向異性導電性膜預先備置於半導體晶片上者;一種附各向異性導電性膜之半導體晶圓,其係用於製造為將相對之電路基板之電極彼此電性連接而使用之半導體晶片者;及一種半導體裝置,其係半導體晶片之電極與相對之電路基板上之電極彼此由接著劑電性連接者。
各向異性導電性膜係於絕緣性接著劑中分散有導電性粒子之膜,用於半導體晶片電極與相對之電路基板電極之間的連接。各向異性導電性膜例如以有機基板與半導體晶片、玻璃基板與半導體晶片之連接用途而主要於平板顯示器領域中得到廣泛應用。
然而,半導體晶片中,隨著高積體化、高頻化發展,除先前之安裝於有機基板上之方法之外,對於使用可縮短配線長度之各向異性導電性膜的半導體晶片之積層化連接、或與內插器連接之需求不斷高漲。
迄今為止,關於用於連接如半導體晶片電極般之細微電路之各向異性導電性膜,眾所周知為了防止短路,而以電性絕緣樹脂將被覆導電性粒子之表面被覆之方法(參照以下之專利文獻1),將包含導電性粒子之層與不包含導電性 粒子之層積層,而防止鄰接之電路間之短路之方法(參照以下之專利文獻2、3)。又,亦眾所周知有將導電性粒子單層排列,且減少各向異性導電性膜中之導電性粒子,而謀求連接-絕緣之平衡化之方法(參照以下之專利文獻4)。進而亦眾所周知有:於半導體晶片之連接電極面以露出連接端子表面之方式形成絕緣性樹脂層,壓接於相對之電極上之方法(參照以下之專利文獻5~7);於半導體晶片之連接端子面以露出連接端子表面之方式形成絕緣性接著層,壓接於貼附有大致1層各向異性導電性膜之電極上之方法(參照以下之專利文獻8);將半導體晶片層壓於各向異性導電性膜上後剝離,形成轉印有各向異性導電性膜之半導體晶片且壓接之方法(參照以下之專利文獻9、10)。又,提出有如下之方法:由旋塗法而於半導體晶圓上形成各向異性導電性接著劑層,然後將晶圓切晶而分割成各個晶片(參照以下之專利文獻11)。
[先前技術文獻] [專利文獻]
[專利文獻1]日本專利特開平3-112011號公報
[專利文獻2]日本專利特開平6-60712號公報
[專利文獻3]日本專利特開平6-45024號公報
[專利文獻4]國際公開第2005/054388號說明書
[專利文獻5]日本專利特開2004-315688號公報
[專利文獻6]日本專利特開2008-133423號公報
[專利文獻7]日本專利特開2011-174010號公報
[專利文獻8]日本專利特開2009-147231號公報
[專利文獻9]日本專利特開2007-158367號公報
[專利文獻10]日本專利特開2006-287269號公報
[專利文獻11]日本專利特開平9-36143號公報
雖有上述之先前技術,但使用各向異性導電性膜的眾所周知之方法中,難以於連接前檢查連接部之導電性粒子數、異常等。又,由於連接時導電性粒子會產生移動,故難以預先預測有助於連接之導電性粒子數。當有助於連接之導電性粒子數較少時,具有連接時之電阻值變高,連接後之半導體裝置之發熱量變大之問題。
又,於半導體晶片上僅形成無導電性粒子之絕緣性接著劑層之情形時,當壓接於相對之電極上時,電極上易殘留絕緣性樹脂,或者因電極高度不均之影響而連接電阻變得不穩定,於連接可靠性方面亦有問題。
進而,於半導體晶片上貼附各向異性導電性膜之方法中,為將微小尺寸之電極以高連接可靠性連接,必需增加導電性粒子之調配量,此時,具有半導體晶片面之對準標記(alignment mark)讀取困難而無法定位之問題。
於此狀況下,本發明所欲解決之問題在於提供一種附各向異性導電性膜之半導體晶片,其可於連接前進行連接部之檢查,可預測有助於連接之導電性粒子數,且連接時之對準標記之辨識性優異。
又,提供一種切晶前可進行連接部之檢查的附各向異性導電性膜之半導體晶圓,且藉由將該附各向異性導電性膜之半導體晶圓切晶,而提供一種可預測有助於連接之導電性粒子數,且接時之對準標記之辨識性優異的附各向異性導電性膜之半導體晶片之製造方法。
本發明者們為解決上述問題進行銳意研究,重複實驗,其結果發現,藉由使用具有特定結構之附各向異性導電性膜之半導體晶片或晶圓可解決上述問題,至此完成本發明。
即,本發明為如下所述者。
[1]一種附各向異性導電性膜之半導體晶片,其特徵在於:其係包含於單面具有複數個電路電極之半導體晶片,及覆蓋該電路電極之各向異性導電性膜者;該各向異性導電性膜包含絕緣性樹脂成分及導電性粒子,且該各向異性導電性膜中所含之全導電性粒子數之60%以上存在於較該電路電極之平均高度更靠該各向異性導電性膜之表面側。
[2]如上述[1]之附各向異性導電性膜之半導體晶片,其中上述各向異性導電性膜之位於較上述電路電極之平均高度更靠表面側之絕緣性樹脂成分的高度為上述導電性粒子之平均直徑之1.0倍~2.0倍。
[3]如上述[1]或[2]之附各向異性導電性膜之半導體晶片,其中上述各向異性導電性膜包含覆蓋上述電路電極之絕緣性接著劑層及導電性粒子層,該導電性粒子層係上述導電性粒子於絕緣性樹脂中以大致平面狀分散排列1層。
[4]如上述[3]之附各向異性導電性膜之半導體晶片,其中於20℃~100℃之溫度範圍內,上述絕緣性接著劑層之樹脂成分之黏度低於上述導電性粒子層之絕緣性樹脂之黏度。
[5]如上述[3]或[4]之附各向異性導電性膜之半導體晶片,其中上述導電性粒子層之絕緣性樹脂之厚度為上述導電性粒子之平均直徑的0.4~2.0倍。
[6]如上述[3]~[5]中任一項之附各向異性導電性膜之半導體晶片,其中上述導電性粒子層中之全導電性粒子數之90%以上為單獨存在,鄰接之導電性粒子間之平均粒子間距離為該導電性粒子之平均直徑的1.0~20倍。
[7]如上述[1]至[6]中任一項之附各向異性導電性膜之半導體晶片,其中上述全導電性粒子數之70%以上自上述各向異性導電性膜之表面露出其一部分。
[8]如上述[1]至[7]中任一項之附各向異性導電性膜之半導體晶片,其中上述導電性粒子為平均直徑2~50 μm之大致球狀之粒子,且選自由對塑膠製之粒子被覆金屬之粒子、金屬粒子、合金粒子、及對金屬製之粒子或合金製之粒子被覆金屬或合金之粒子所組成之群。
[9]如上述[1]至[8]中任一項之附各向異性導電性膜之半導體晶片,其中上述各向異性導電性膜自上述半導體晶片之外形的最大伸出長度為50 μm以下。
[10]一種如上述[1]之附各向異性導電性膜之半導體晶片之製造方法,其包含以下步驟: 於依序積層支持體及導電性粒子在剖面厚度方向上偏向存在於支持體側之各向異性導電性膜層而成之積層體上,將於單面具有複數個電路電極之半導體晶片的該電路電極面進行層壓之步驟;及將經該層壓之該半導體晶片與該各向異性導電性膜層一起自該支持體剝離之步驟。
[11]如上述[10]之方法,其中上述各向異性導電性膜層包含絕緣性接著劑層及導電性粒子層,該導電性粒子層係上述導電性粒子於絕緣性樹脂中以大致平面狀分散排列1層。
[12]一種如上述[3]之附各向異性導電性膜之半導體晶片之製造方法,其包含以下步驟:於單面具有複數個電路電極之半導體晶片的電路電極面,填充絕緣性接著劑之步驟;於所獲得之附絕緣性接著劑層之半導體晶片上,將形成於支持體上且導電性粒子於絕緣性樹脂中以大致平面狀分散排列1層之導電性粒子層進行層壓之步驟;及將上述附絕緣性接著劑層之半導體晶片與上述導電性粒子層一起自上述支持體上剝離之步驟。
[13]一種如上述[3]之附各向異性導電性膜之半導體晶片之製造方法,其包含以下步驟:於單面具有複數個電路電極之半導體晶片的電路電極面,填充絕緣性接著劑之步驟;於所獲得之附絕緣性接著劑層之半導體晶片上,將分散 排列形成於積層在支持體上之黏著劑層上的導電性粒子進行層壓之步驟;及將上述附絕緣性接著劑層之半導體晶片與上述導電性粒子一起自積層在上述支持體上之黏著劑層剝離之步驟。
[14]如上述[10]至[13]中任一項之方法,其中於上述層壓步驟中,以20℃~100℃進行真空層壓。
[15]一種半導體裝置之製造方法,其包含下述步驟:將如上述[1]至[9]中任一項之附各向異性導電性膜之半導體晶片的電路電極、與具有對應之連接電極之電路基板位置進行對準並熱壓接。
[16]如上述[15]之方法,其包含下述步驟:於上述熱壓接步驟之前,目視檢查上述電路電極上之導電性粒子數。
[17]一種半導體裝置,其係藉由如上述[15]或[16]之方法而製造者,且上述熱壓接後上述連接電極上之每單位面積之導電性粒子數,為上述電路電極以外之部分之每單位面積之導電性粒子數的65%以上。
[18]一種附上述各向異性導電性膜之半導體晶圓,其特徵在於:其係包含於單面具有複數個電路電極之半導體晶圓,及覆蓋該電路電極之各向異性導電性膜者;該各向異性導電性膜包含絕緣性樹脂成分及導電性粒子,且該各向異性導電性膜中所含之全導電性粒子數之60%以上存在於較該電路電極之平均高度更靠該各向異性導電性膜之表面側。
[19]如上述[18]之附各向異性導電性膜之半導體晶圓, 其中上述各向異性導電性膜之位於較上述電路電極之平均高度更靠表面側之絕緣性樹脂成分的高度為上述導電性粒子之平均直徑之1.0倍~2.0倍。
[20]如上述[18]或[19]之附各向異性導電性膜之半導體晶圓,其中上述各向異性導電性膜包含覆蓋上述電路電極之絕緣性接著劑層及導電性粒子層,該導電性粒子層係上述導電性粒子於絕緣性樹脂中以大致平面狀分散排列1層。
[21]如上述[20]之附各向異性導電性膜之半導體晶圓,其中於20℃~100℃之溫度範圍內,上述絕緣性接著劑層之樹脂成分之黏度低於上述導電性粒子層之絕緣性樹脂之黏度。
[22]如上述[20]或[21]之附各向異性導電性膜之半導體晶圓,其中上述導電性粒子層之絕緣性樹脂之厚度為上述導電性粒子之平均直徑的0.4~2.0倍。
[23]如上述[20]至[22]中任一項之附各向異性導電性膜之半導體晶圓,其中上述導電性粒子層中之全導電性粒子數的90%以上為單獨存在,鄰接之導電性粒子間之平均粒子間距離為該導電性粒子之平均直徑的1.0~20倍。
[24]如上述[18]至[23]中任一項之附各向異性導電性膜之半導體晶圓,其中上述全導電性粒子數之70%以上自上述各向異性導電性膜之表面露出其一部分。
[25]如上述[18]至[24]中任一項之附各向異性導電性膜之半導體晶圓,其中上述導電性粒子為平均直徑2~50 μm之大致球狀之粒子,且選自由對塑膠製之粒子被覆金屬之粒 子、金屬粒子、合金粒子、及對金屬製之粒子或合金製之粒子被覆金屬或合金之粒子所組成之群。
[26]一種如[18]之附各向異性導電性膜之半導體晶圓之製造方法,其包含以下步驟:於依序積層支持體及導電性粒子在剖面厚度方向上偏向存在於支持體側之各向異性導電性膜層而成之積層體上,將於單面具有複數個電路電極之半導體晶圓的該電路電極面進行層壓之步驟;及將經該層壓之該半導體晶圓與該各向異性導電性膜層一起自該支持體剝離之步驟。
[27]如上述[26]之方法,其中上述各向異性導電性膜層包含絕緣性接著劑層及導電性粒子層,該導電性粒子層係上述導電性粒子於絕緣性樹脂中以大致平面狀分散排列1層。
[28]如上述[20]之附各向異性導電性膜之半導體晶圓之製造方法,其包含以下步驟:於單面具有複數個電路電極之半導體晶圓的電路電極面,填充絕緣性接著劑之步驟;於所獲得之附絕緣性接著劑層之半導體晶圓上,將形成於支持體上且導電性粒子於絕緣性樹脂中以大致平面狀分散排列1層之導電性粒子層進行層壓之步驟;及將上述附絕緣性接著劑層之半導體晶圓與上述導電性粒子層一起自上述支持體剝離之步驟。
[29]如上述[20]之附各向異性導電性膜之半導體晶圓之 製造方法,其包含以下步驟:於單面具有複數個電路電極之半導體晶圓的電路電極面,填充絕緣性接著劑之步驟;於所獲得之附絕緣性接著劑層之半導體晶圓上,將分散排列形成於積層在支持體上之黏著劑層上的導電性粒子進行層壓之步驟;及將上述附絕緣性接著劑層之半導體晶圓與上述導電性粒子一起自積層在上述支持體上之黏著劑層剝離之步驟。
[30]如上述[26]至[29]中任一項之方法,其中於上述層壓步驟中,以20℃~100℃進行真空層壓。
[31]一種附各向異性導電性膜之半導體晶片之製造方法,其包含下述步驟:將如上述[18]至[25]中任一項之附各向異性導電性膜之半導體晶圓切晶。
[32]如上述[31]之方法,其中於將上述附各向異性導電性膜之半導體晶圓切晶之步驟之前,包含目視檢查上述電路電極上之導電性粒子數之步驟。
[33]一種半導體裝置,其係包含於單面具有複數個電路電極之半導體晶片、具有與該電路電極對應之連接電極之電路基板、及接著劑者;該接著劑係包含絕緣性樹脂及導電性粒子,且配置於該半導體晶片與該電路基板之間,於該半導體晶片上之距離最短之電路電極間的沿厚度方向切斷之剖面中距半導體晶片最近之導電性粒子、與距半導體晶片最遠之導電性粒子的厚度方向上之粒子間距離為該導電性粒子之平均直徑的1倍以下。
[34]如上述[33]之半導體裝置,其中上述導電性粒子為平均直徑2~50 μm之大致球狀之粒子,且選自由對塑膠製之粒子被覆金屬之粒子、金屬粒子、合金粒子、及對金屬製之粒子或合金製之粒子被覆金屬或合金之粒子所組成之群。
[35]如上述[33]或[34]之半導體裝置,其中上述接著劑自上述半導體晶片之外形的最大伸出長度為50 μm以下。
[36]如上述[33]至[35]中任一項之半導體裝置,其中上述熱壓接後上述連接電極之每單位面積之導電性粒子數為上述電路電極以外之部分之每單位面積之導電性粒子數的65%以上。
本發明之附各向異性導電性膜之半導體晶片或晶圓可於連接前進行連接部之檢查,可預測有助於連接之導電性粒子數,且連接時之對準標記之辨識性優異。
以下,就用於實施本發明之形態(以下,簡稱為「實施形態」)進行詳細說明。另,本發明並非限於以下之實施形態者,可於其要旨之範圍內進行種種變形而實施。
本實施形態之附各向異性導電性膜之半導體晶片包含於單面(至少一個主面)具有複數個電路電極之半導體晶片、及覆蓋電路電極之各向異性導電性膜(參照圖1)。
本實施形態中,各向異性導電性膜包含絕緣性樹脂成分及導電性粒子,且該導電性粒子於剖面厚度方向上偏向存 在。具體而言,全導電性粒子數的60%以上,較佳為70%以上,更佳為80%以上,進而更佳為90%以上存在於較半導體晶片之電路電極之平均高度更靠該各向異性導電性膜之表面側。此處,電路電極之平均高度係指於半導體晶片剖面中,以未配置有電路電極之部分為基準之各電路電極之高度的平均值。各向異性導電性膜之表面側係指各向異性導電性膜剖面中,與接觸半導體晶片之側相反之側。於連接電阻穩定化方面而言,較佳為全導電性粒子數的60%以上存在於較半導體晶片之電路電極之平均高度更靠該各向異性導電性膜之表面側。
各向異性導電性膜之絕緣性樹脂成分中亦可包含硬化性樹脂或硬化劑。
作為導電性粒子,可使用金屬粒子、對塑膠製之粒子被覆金屬薄膜所成之粒子。作為金屬粒子,可舉出例如:金、銀、銅、鎳、鋁、鋅、錫、鉛、銦、鈀等之單獨體,或2種以上該等金屬組合成層狀或傾斜狀之粒子,或者將2種以上組合所成之合金、焊錫等。於使用熔點為150℃以上500℃以下之合金粒子、焊錫之情形時,較佳為預先對粒子表面被覆焊劑等。藉由使用焊劑,可除去表面之氧化物等。作為焊劑,可使用松香亭酸等之脂肪酸。
作為對塑膠製之粒子被覆金屬薄膜所成之粒子,可例示對選自環氧樹脂、苯乙烯樹脂、聚矽氧樹脂、丙烯酸系樹脂、聚烯烴樹脂、三聚氰胺樹脂、苯胍樹脂、胺基甲酸酯樹脂、酚樹脂、聚酯樹脂、二乙烯基苯樹脂、 NBR(acrylonitrile-butadiene rubber:丁腈橡膠)、SBR(styrene-butadiene rubber:苯乙烯-丁二烯橡膠)等之聚合物之1種或2種以上之組合,藉由鍍敷等被覆金屬所成之粒子。作為金屬薄膜之厚度,自連接穩定性及粒子之凝集性之觀點而言,較佳為0.005 μm以上1 μm以下之範圍。亦可使用於該導電性粒子之表面進而進行絕緣被覆所成之粒子或於表面形成微小突起之金平糖型粒子。
作為導電性粒子,較佳為使用球狀者,此時,更佳為近似於圓球者。短軸相對於長軸之比以0.5以上為佳,更佳為0.7以上,進而較佳為0.9以上。短軸相對於長軸之比之最大值為1。
導電性粒子之平均直徑需小於欲連接之鄰接電極間距離,同時較佳為大於所連接之電子零件之電極高度之偏差值。因此,導電性粒子之平均直徑較佳為2.0 μm以上50 μm以下之範圍,更佳為2.5 μm以上40 μm以下,進而更佳為3.0 μm以上35 μm以下,尤佳為4.0 μm以上30 μm以下。又,導電性粒子之粒徑分佈之標準偏差較佳為平均直徑的50%以下。
又,各向異性導電性膜中,亦可進而含有絕緣粒子、填充劑、軟化劑、硬化促進劑、穩定劑、著色劑、阻燃劑、流動調節劑、偶合劑等。
於調配絕緣性粒子或填充劑等固形物之情形時,該等之最大直徑較佳為小於導電性粒子之平均直徑。作為偶合劑,自密接性之觀點考慮,較佳為含有環氧基、酮亞胺 基、乙烯基、丙烯醯基、胺基、異氰酸酯基等之矽烷偶合劑。
各向異性導電性膜中位於較電路電極之平均高度更靠表面側之絕緣性樹脂成分的高度(厚度)較佳為所包含之導電性粒子之平均直徑的1.0~2.0倍,更佳為1.0~1.5倍,進而更佳為1.0~1.2倍。此處,導電性粒子之平均直徑係指導電性粒子之長徑之平均值。自控制各向異性導電性膜之黏性、及控制導電性粒子保持性之觀點考慮,該厚度較佳為導電性粒子之平均直徑的1.0倍以上,另一方面,自抑制連接時導電性粒子移動之觀點考慮,較佳為2.0倍以下。
又,該厚度較佳為電路電極之平均高度的1.05倍~1.5倍。自控制各向異性導電性膜之黏性、及控制導電性粒子保持性之觀點考慮,該厚度較佳為電路電極之平均高度的1.05倍以上,另一方面,自抑制連接時導電性粒子移動之觀點考慮,較佳為1.5倍以下。
各向異性導電性膜較佳為包含絕緣性接著劑層、及導電性粒子於絕緣性樹脂中以大致平面狀分散排列1層之導電性粒子層(參照圖2)。
導電性粒子層之絕緣性樹脂之厚度較佳為導電性粒子之平均直徑的0.4~2.0倍,更佳為0.5~1.8倍,進而更佳為0.7~1.0倍。自控制導電性粒子層之黏性、或控制導電性粒子保持性之觀點考慮,該厚度較佳為0.4倍以上,另一方面,自連接穩定性之觀點考慮,較佳為2.0倍以下。
本實施形態之附各向異性導電性膜之半導體晶片中,以 各向異性導電性膜自半導體晶片外形伸出之量為指標之最大伸出長度較佳為-20~50 μm,更佳為-10~30 μm,進而更佳為0~20 μm。自電性連接性及機械連接性之觀點考慮,該伸出長度較佳為-20 μm以上,另一方面,自操作性及連接時樹脂伸出之觀點考慮,較佳為50 μm以下。
本實施形態之各向異性導電性膜中全導電性粒子數的70%以上較佳為其一部分自各向異性導電性膜之表面露出。露出之粒子數更佳為80%以上,進而更佳為90%以上。自連接時與相對之電極之連接性之觀點考慮,導電性粒子較佳為自各向異性導電性膜之表面露出。以所露出之每1粒子之露出程度為指標之露出高度較佳為小於該粒子之平均直徑的50%。當該露出高度小於50%時,於導電性粒子不易脫落之方面較佳。
本實施形態所使用之絕緣性接著劑可包含選自由熱硬化性樹脂、熱塑性樹脂、光硬化性樹脂、電子束硬化性樹脂所組成之群之1種以上之樹脂。作為該等之樹脂,例如可舉出:環氧樹脂、氧雜環丁烷樹脂、酚樹脂、聚矽氧樹脂、胺基甲酸酯樹脂、丙烯酸系樹脂、聚醯亞胺樹脂、苯氧基樹脂、聚乙烯丁醛樹脂、SBR、SBS(styrene-butadiene-styrene,苯乙烯-丁二烯-苯乙烯嵌段共聚物)、NBR、聚對苯二甲酸乙二酯樹脂、聚醯胺樹脂、聚苯乙烯樹脂、聚異丁烯樹脂、烷基酚樹脂、苯乙烯丁二烯樹脂、羧基改性腈樹脂等或該等之改性樹脂。自密接性之觀點而言,絕緣性接著劑較佳為包含環氧樹脂、氧雜環丁烷樹 脂。
作為此處使用之環氧樹脂,例如有雙酚A型環氧樹脂、雙酚F型環氧樹脂、雙酚S型環氧樹脂、四亞甲基雙酚A型環氧樹脂、聯苯型環氧樹脂、萘型環氧樹脂、間苯二酚型環氧樹脂、茀型環氧樹脂、苯酚酚醛清漆型環氧樹脂、甲酚酚醛清漆型環氧樹脂、雙酚A型酚醛清漆型環氧樹脂、脂肪族醚型環氧樹脂等縮水甘油醚型環氧樹脂、縮水甘油醚酯型環氧樹脂、縮水甘油酯型環氧樹脂、縮水甘油基胺型環氧樹脂、脂環式環氧樹脂,該等環氧樹脂亦可經鹵化或氫化,又,亦可為胺基甲酸酯改性、橡膠改性、聚矽氧改性等之改性環氧樹脂。
又,較佳為以賦予膜形成性、接著性、硬化時之應力緩和為目的,而於絕緣性接著劑中調配熱塑性樹脂。作為熱塑性樹脂,較佳為分子量為5000~1000000者,更佳為8000~80000者,進而更佳為9000~60000者。熱塑性樹脂成分之含量相對於各向異性導電性膜中之全樹脂成分,較佳為5~80質量份,更佳為10~70質量份,進而更佳為20~60質量份。自膜形成性之觀點而言,該含量較佳為5質量份以上,另一方面,自連接穩定性之觀點而言,較佳為80質量份以下。作為使用環氧樹脂、氧雜環丁烷樹脂之情形時之硬化劑,較佳為潛在性硬化劑。作為潛在性硬化劑,較佳為使用微膠囊型潛在性硬化劑、熱陽離子硬化劑等。
微膠囊型硬化劑係藉由樹脂皮膜等使硬化劑之表面變得穩定者,在連接時之熱或荷重下樹脂皮膜受到破壞,硬化 劑擴散至微膠囊外,與環氧樹脂、氧雜環丁烷樹脂進行反應。微膠囊型潛在性硬化劑中,將胺加合物、咪唑加合物等之加合物型硬化劑進行微膠囊化而成之潛在性硬化劑的穩定性與硬化性之平衡優異,就此方面而言較佳。微膠囊型硬化劑係以相對於環氧樹脂100質量份為2~100質量份之量使用。
作為熱陽離子硬化劑,較佳為芳香族鋶鹽型硬化劑。因熱陽離子硬化劑可均勻調配於硬化性樹脂中,並可以觸媒型進行硬化,故可於低溫、短時間內硬化,且溶劑穩定性亦良好,故而較佳。作為芳香族鋶鹽型硬化劑之陰離子,可使用六氟銻酸鹽、六氟磷酸鹽、四氟硼酸鹽、四(五鹵代苯基)硼酸鹽等,而於可減少雜質離子之方面而言,較佳為四(五鹵代苯基)硼酸鹽,尤佳為四(五氟苯基)硼酸鹽。
又,於絕緣性接著劑層中,亦可為抗靜電等目的而在不損壞絕緣性之範圍內添加導電性粒子。
關於導電性粒子之分散排列,較佳為鄰近之導電性粒子之平均粒子間隔為導電性粒子之平均直徑的1.0倍以上20倍以下,更佳為2倍以上10倍以下。於難以產生短路之方面而言,較佳為1.0倍以上,另一方面,於容易確保連接穩定性所必需之導電性粒子數方面而言,較佳為20倍以下。
對於導電性粒子所分佈之平面中之分散排列狀態,較佳為分散排列成大致正三角形狀。於分散排列成大致正三角 形狀之情形時,鄰近之導電性粒子之間隔接近於等間隔,位於連接電極上之導電性粒子數大致一定,連接部之導電性粒子數之不均較小,連接電阻變得穩定,故而較佳。
又,導電性粒子較佳為全數之90%以上為單獨存在,而不相互凝集。即便凝集,亦較佳為凝集粒子不為4個以上導電性粒子凝集而成者。
導電性粒子層包含導電性粒子及絕緣性樹脂,亦可含有硬化性樹脂或硬化劑。導電性粒子層之絕緣性樹脂於100℃下之黏度為3000 Pa.s~500000 Pa.s之範圍內,更佳為5000 Pa.s~300000 Pa.s,進而更佳為10000 Pa.s~200000 Pa.s。於容易於抑制導電性粒子流動之方面而言,該黏度較佳為3000 Pa.s以上。另一方面,於連接電阻值良好之方面而言,較佳為500000 Pa.s以下。
導電性粒子層之絕緣性樹脂於100℃下之黏度、及20℃~100℃下之黏度分別可利用流變儀進行測定。較佳為製作自導電性粒子層除去導電性粒子後之薄片,在60℃/min之升溫條件下進行測定。
絕緣性接著劑層在100℃下之黏度較佳為100 Pa.s~10000 Pa.s之範圍內,更佳為200 Pa.s~5000 Pa.s之範圍內,進而更佳為300 Pa.s~1000 Pa.s之範圍內。自操作性之觀點考慮,絕緣性接著劑層在100℃下之黏度較佳為100 Pa.s,另一方面,自連接穩定性之觀點考慮,較佳為10000 Pa.s以下。
絕緣性接著劑層之樹脂成分在100℃下之黏度、及 20℃~100℃下之黏度的測定方法分別可採用與導電性粒子層之絕緣性樹脂之黏度的測定相同之方法。導電性粒子層之絕緣性樹脂在100℃下之黏度較佳為絕緣性接著劑層之樹脂成分在100℃下之黏度的2倍~1000倍,更佳為5倍~500倍之範圍內,進而更佳為8倍~400倍之範圍,尤佳為10倍~300倍之範圍內。於可抑制連接時導電性粒子流出之方面而言,該黏度比較佳為2倍以上,另一方面,自連接電阻穩定化之觀點考慮,較佳為1000倍以下。
導電性粒子層之絕緣性樹脂成分亦可與絕緣性接著劑層之樹脂成分相同,於不同之情形時,較佳為於20~100℃之溫度範圍內,導電性粒子層之絕緣性樹脂成分之黏度高於絕緣性接著劑層之樹脂成分之黏度,更佳為於該溫度範圍之各溫度下導電性粒子層之絕緣性樹脂成分之黏度與絕緣性接著劑層之樹脂成分之黏度的比為2~1000倍,該比進而更佳為10~500倍,該比尤佳為20~100倍。
自減低連接時自各向異性導電性膜之樹脂伸出量、及抑制連接時導電性粒子移動之觀點考慮,導電性粒子層之絕緣性樹脂成分之黏度較佳為高於絕緣性接著劑層之樹脂成分之黏度。又,自抑制灰塵附著於導電性粒子層上、及連接前之操作性之觀點考慮,導電性粒子層之絕緣性樹脂成分之黏度較佳為高於絕緣性接著劑層之樹脂成分之黏度。自連接穩定性之觀點考慮,該黏度比較佳為1000倍以下。
以下,就本實施形態之附各向異性導電性膜之半導體晶片之製造方法進行說明。作為本實施形態之附各向異性導 電性膜之晶片之製造方法,可採用以下之方法。
方法1
方法1係一種附各向異性導電性膜之半導體晶片之製造方法(參照圖3),其包含以下步驟:於以支持體、導電性粒子在剖面厚度方向上偏向存在於支持體側之各向異性導電性膜層的順序積層而成之積層體上,將於單面具有複數個電路電極之半導體晶片的該電路電極面進行層壓之步驟;及將經該層壓之該半導體晶片與該各向異性導電性膜層一起自該支持體上剝離之步驟。自連接可靠性之觀點考慮,上述各向異性導電性膜層較佳為包含絕緣性接著劑層、及上述導電性粒子以大致平面狀分散排列1層之導電性粒子層。
作為於支持體上形成導電性粒子以大致平面狀分散排列之導電性粒子層之方法,較適合使用以下之方法。
於可雙軸延伸之支持體(支持膜)上形成黏著層,於黏著層上最密填充導電性粒子,於導電性粒子上塗佈絕緣性樹脂清漆且乾燥,製作導電性粒子填充樹脂片材。其後,將該導電性粒子填充片材進行雙軸延伸,藉此獲得形成於支持體上之導電性粒子層。於如此獲得之導電性粒子層上,將形成於剝離片材上之絕緣性接著劑層進行層壓,除去剝離片材,藉此可獲得形成於支持體上之各向異性導電性膜。又,亦可藉由如下方式獲得形成於支持體上之各向異性導電性膜:製作導電性粒子分散排列於支持體上之導電 性粒子分散排列片材,於如此獲得之導電性粒子分散排列片材上,將另外形成於剝離膜上之絕緣性樹脂片材進行層壓而形成導電性粒子層,除去剝離膜,藉此製作形成於支持體上之導電性粒子層,於如此獲得之導電性粒子層上,將另外形成於剝離片材上之絕緣性接著劑層進行層壓,除去該剝離片材。
作為上述之導電性粒子分散排列片材之製造方法,可舉出如下方法:於可雙軸延伸之支持膜上形成黏著層,於黏著層上最密填充導電性粒子,其後將該導電性粒子填充片材進行雙軸延伸;或者,製作以特定之排列圖案形成有深度為導電性粒子之平均直徑的0.8~1.2倍之凹部,且於該凹部內填充有導電性粒子之片材,進而於填充有該導電性粒子之片材上,將於支持膜上形成有黏著層之黏著膜之黏著層面進行層壓,將填充上述導電性粒子之片材剝離,藉此製作導電性粒子轉印至支持膜上之黏著層上之膜。
方法2
方法2係一種附各向異性導電性膜之半導體晶片之製造方法(參照圖4),其包含以下步驟:於單面具有複數個電路電極之半導體晶片的電路電極面,填充絕緣性接著劑之步驟;於所獲得之附絕緣性接著劑層之半導體晶片上,將形成於支持體上,且導電性粒子於絕緣性樹脂中以大致平面狀分散排列1層之導電性粒子層進行層壓之步驟;及將上述附絕緣性接著劑層之半導體晶片與上述導電性粒 子層一起自上述支持體上剝離之步驟。作為導電性粒子層之形成方法,可採用上述之方法。
方法3
方法3係一種附各向異性導電性膜之半導體晶片之製造方法(參照圖5),其包含以下步驟:於單面具有複數個電路電極之半導體晶片的電路電極面,填充絕緣性接著劑之步驟;於所獲得之附絕緣性接著劑層之半導體晶片上,將分散排列形成於積層在支持體上之黏著劑層上的導電性粒子進行層壓之步驟;及將上述附絕緣性接著劑層之半導體晶片與上述導電性粒子一起自積層在上述支持體上之黏著劑層剝離之步驟。作為分散排列形成於積層在支持體上之黏著劑層上的導電性粒子之製作方法,可採用上述之導電性粒子分散排列片材之製作方法。
於方法1~3之層壓步驟中,較佳為於20℃~100℃,更佳為30~80℃,進而更佳為40~70℃下進行真空層壓。自保存穩定性之觀點考慮,該層壓步驟之溫度較佳為100℃以下,另一方面,自層壓性之觀點考慮,較佳為20℃以上。
將本實施形態之附各向異性導電性膜之半導體晶片,壓接於具有相對之電極的電路基板上製造半導體裝置之情形時,適合使用將電極彼此位置對準後進行熱壓接之方法。
作為用於本實施形態之電路基板,可使用有機基板、無機基板,較佳為使用矽、氧化鋁、鎵砷、玻璃等之無機基 板。又,電路基板為半導體晶片,採用半導體晶片積層之結構的情況亦較佳。於積層複數個半導體晶片之情形時,較佳為於半導體晶片內設置貫通電路,於上表面側設置連接電極,於下表面側形成電路電極。又,亦可於連接電極面另外設置打線結合用之電極,而藉由打線結合與其他電路基板形成電性連接。關於電路基板之線膨脹係數,自因與半導體晶片連接所成之連接結構體之翹曲引起之特性變化的觀點考慮,較佳為2.5×10-6 K-1~8×10-6 K-1之範圍內。
半導體晶片之電路電極配置可舉出如下配置:於晶片之下表面之大致整個面上配置電極之整面配置;於晶片下表面除去中心部之部分配置電極之周邊面配置;於下表面端部之2個邊或4個邊上配置電極之2邊配置或4邊配置等。進而,2邊配置或4邊配置中,亦可舉出電極之一部分或全部配置成2列以上之鋸齒狀配置等。
作為半導體晶片之形狀,可使用正方形或長方形之形狀者。於長方形之情形時,長邊與短邊之比較佳為在1~30之範圍內。
將本實施形態之附各向異性導電性膜之半導體晶片,壓接具有相對之電極之電路基板時,以各向異性導電性膜自半導體晶片外周之伸出量為指標之伸出長度較佳為在連接電極高度的0.5~100倍之範圍內,更佳為1~80倍之範圍內,進而更佳為2倍~70倍之範圍內。自高密度封裝之觀點考慮,該伸出長度較佳為100倍以下,自電性連接、機械連接之觀點考慮,較佳為0.5倍以上。壓接時之伸出量可 藉由對電路電極高度、電極面積、各向異性導電性膜厚度、各向異性導電性膜之伸出量(長度)、各向異性導電性膜之樹脂黏度、連接溫度等進行調整而控制。
半導體晶片之電路電極較佳為使用於包含選自鋁、銅、鎳、鎢、鈦、銀之1種或2種以上金屬的單層或多層之電極上,形成有包含金、焊錫或銅之凸電極者。半導體晶片之凸電極以外之部分較佳為由氧化矽、氮化矽、氮氧化矽、聚醯亞胺等之絕緣膜覆蓋。電路基板之連接電極較佳為包含選自鋁、鎳、銅、鎢、鈦、鉭、鉬、氧化銦錫、氧化銦鋅之1種或2種以上的單層或多層之電極。
電路基板之連接電極以外之部分較佳為由氧化矽、氮化矽、氮氧化矽、聚醯亞胺等之絕緣膜覆蓋。
電路電極之凸電極之面積較佳為在500 μm2~10000 μm2之範圍內,更佳為在1000 μm2~5000 μm2之範圍內。
本實施形態之附各向異性導電性膜之半導體晶片較佳為於熱壓接前,目視檢查電路電極上之導電性粒子數。藉由目視檢查,可預先確認導電性粒子之個數,且亦可確認異物混入等之異常。
將本實施形態之附各向異性導電性膜之半導體晶片連接於電路基板之情形時,連接後電路電極上每單位面積之導電性粒子數較佳為電路電極以外之部分中每單位面積之導電性粒子數的65%以上,更佳為80%以上,進而更佳為90%以上。自連接電極上導電性粒子難以移動,連接性、絕緣性容易取得平衡之方面而言,該導電性粒子數較佳為 65%以上。
本實施形態之附各向異性導電性膜之半導體晶圓包含:於單面(至少一個主面)具有複數個電路電極之半導體晶圓、及覆蓋電路電極之各向異性導電性膜(參照圖6)。
本實施形態中,各向異性導電性膜包含絕緣性樹脂成分及導電性粒子,且該導電性粒子於剖面厚度方向上偏向存在。具體而言,全導電性粒子數之60%以上,較佳為70%以上,更佳為80%以上,進而更佳為90%以上係存在於較半導體晶圓之電路電極之平均高度更靠該各向異性導電性膜之表面側。此處,電路電極之平均高度係指於半導體晶片剖面中,以未配置電路電極之部分為基準之各電路電極之高度的平均值。各向異性導電性膜之表面側係指各向異性導電性膜剖面中,與接觸半導體晶片之側相反之側。於連接電阻穩定化方面而言,較佳為全導電性粒子數之60%以上存在於較半導體晶圓之電路電極之平均高度更靠該各向異性導電性膜之表面側。
各向異性導電性膜之絕緣性樹脂成分中亦可包含硬化性樹脂或硬化劑。
導電性粒子可與上述中關於附各向異性導電性膜之半導體晶片而記載者相同。
又,於各向異性導電性膜中,亦可進而含有與上述中關於附各向異性導電性膜之半導體晶片而記載者相同的絕緣粒子、填充劑、軟化劑、硬化促進劑、穩定劑、著色劑、阻燃劑、流動調節劑、偶合劑等。
各向異性導電性膜中較電路電極平均高度更靠表面側之絕緣性樹脂成分的高度(厚度)可與上述中關於附各向異性導電性膜之半導體晶片而記載者相同。
各向異性導電性膜較佳為如上述中關於附各向異性導電性膜之半導體晶片所記載般,包含絕緣性接著劑層、及導電性粒子於絕緣性樹脂中以大致平面狀分散排列1層之導電性粒子層(參照圖7)。
電性粒子層之絕緣性樹脂之厚度可與上述中關於附各向異性導電性膜之半導體晶片而記載者相同。
本實施形態之各向異性導電性膜中之全導電性粒子數之比例亦可與上述中關於附各向異性導電性膜之半導體晶片而記載者相同。又,導電性粒子較佳為自各向異性導電性膜之表面露出,以露出之每1粒子之露出程度為指標之露出高度亦可與上述中關於附各向異性導電性膜之半導體晶片而記載者相同。
用於本實施形態之絕緣性接著劑亦可與上述中關於附各向異性導電性膜之半導體晶片而記載者相同。
又,較佳為如上述中關於附各向異性導電性膜之半導體晶片所記載般,以賦予膜形成性、接著性、硬化時之應力緩和為目的而於絕緣性接著劑中調配熱塑性樹脂,可使用之熱塑性樹脂硬化劑等亦可與上述者相同。
導電性粒子之分散排列亦可與上述中關於附各向異性導電性膜之半導體晶片而記載者相同。
導電性粒子層包含如上述中關於附各向異性導電性膜之 半導體晶片而記載的導電性粒子及絕緣性樹脂,且亦可包含硬化性樹脂或硬化劑。
導電性粒子層之絕緣性樹脂成分之黏度亦可與上述中關於附各向異性導電性膜之半導體晶片而記載者相同。
以下,由於本實施形態之附各向異性導電性膜之半導體晶片可藉由在製造本實施形態之附各向異性導電性膜之半導體晶圓後,將其單片化(切出、切晶)而進行製造,故關於附各向異性導電性膜之半導體晶片,故而本實施形態之附各向異性導電性膜之半導體晶圓之製造方法除單片化步驟之外,實質上與上述中關於附各向異性導電性膜之半導體晶片而記載者相同。
本實施形態之附各向異性導電性膜之半導體晶圓較佳為於切晶前目視檢查電路電極上的導電性粒子數。藉由目視檢查,可預先確認導電性粒子之個數,且亦可確認異物混入等之異常。又,可藉由規定異常部分而區分切晶後之良品、不良品。進而,於附各向異性導電性膜之半導體晶圓之不良部位較多之情形時,可除去各向異性導電性膜,再次貼附各向異性導電性膜,藉此減少半導體晶圓之損失。
本實施形態之半導體裝置係包含於單面具有複數個電路電極2之半導體晶片1、具有與該電路電極2對應之連接電極12之電路基板11、及接著劑10者,該接著劑10包含絕緣性樹脂及導電性粒子4,且配置於該半導體晶片1與該電路基板11之間,於該半導體晶片1上之距離最短之電路電極間的沿厚度方向切斷之剖面中,距半導體晶片最近之導電 性粒子、與距半導體晶片最遠之導電性粒子的厚度方向上之粒子間距離為該導電性粒子之平均直徑的1倍以下(參照圖11)。
此處,距半導體晶片最近之導電性粒子、與距半導體晶片最遠之導電性粒子的厚度方向上之粒子間距離係指自距半導體晶片最遠之粒子之中心垂直於厚度方向劃出之假想直線15、與自距半導體晶片最近之粒子之中心垂直於厚度方向劃出之假想直線16間的距離(參照圖11)。
本實施形態之半導體裝置藉由採用上述中規定之導電性粒子之配置,而可靠性試驗後之連接電阻、絕緣性優異。自該觀點而言,距半導體晶片最近之導電性粒子、與距半導體晶片最遠之導電性粒子的厚度方向上之粒子間距離較佳為該導電性粒子之平均直徑的0.9倍以下,更佳為0.8倍以下,進而更佳為0.5倍以下,尤佳為0.35倍以下。上述距離之最小值為0倍。
上述中規定之半導體裝置係例如可藉由下述方式而獲得:將於單面具有複數個電路電極,且各向異性導電性膜中之導電性粒子在剖面厚度方向上偏向存在的附各向異性導電性膜之半導體晶片壓接於具有相對之連接電極的電路基板上。
電路電極可與上述中關於附各向異性導電性膜之半導體晶片而記載者相同。
導電性粒子之平均直徑必需小於欲連接之鄰接電極間距離,同時較佳為大於所連接之電子零件之電極高度之偏差 值。因此,導電性粒子之平均直徑較佳為2.0 μm以上50 μm以下之範圍,更佳為2.5 μm以上40 μm以下,進而更佳為3.0 μm以上35 μm以下,尤佳為4.0 μm以上30 μm以下。又,導電性粒子之粒徑分佈之標準偏差較佳為平均直徑之50%以下。
本實施形態之半導體裝置中,以接著劑自半導體晶片外形伸出之量為指標的最大伸出長度較佳為-20~50 μm,更佳為-10~30 μm,進而更佳為0~20 μm。自電性連接性及機械連接性之觀點考慮,該伸出長度較佳為-20 μm以上,另一方面,自操作性及連接時樹脂伸出之觀點考慮,較佳為50 μm以下。
本實施形態之半導體裝置中電路電極上每單位面積之導電性粒子數較佳為電路電極以外之部分中每單位面積之導電性粒子數的65%以上,更佳為80%以上,進而更佳為90%以上。於連接性、絕緣性容易取得平衡之方面而言,該導電性粒子數較佳為65%以上。
[實施例]
以下,藉由實施例及比較例具體說明本發明,但本發明並非限定於以下之實施例者。
(半導體晶片之製作)
於縱橫為1.6 mm×15.1 mm之矽片(厚度0.28 mm)之整個面上形成氧化膜,於距外邊部20 μm之內側,以分別為2 μm間隔之方式沿長邊側各形成橫58 μm、縱120 μm之鋁薄膜(厚度1000 Å)480個。為於該等鋁薄膜上以成為10 μm間 隔之方式分別形成2個橫20 μm、縱100 μm之金凸塊(厚度15 μm),而於距各金凸塊配置部位之外周部7 μm之內側,除留出橫6 μm、縱86 μm之開口部以外之部分形成包含氧化矽/氮化矽的厚度0.1 μm之保護膜。其後,形成上述金凸塊,獲得半導體晶片。作為電路電極之金凸塊以未配置有電極之保護膜面為基準之平均高度為15.0 μm。
(附各向異性導電性膜之半導體晶片之檢查評估)
檢查性評估:使用顯微鏡,自該附各向異性導電性膜之晶圓的各向異性導電性膜表面計測金凸塊上之導電性粒子數。將可計測者評估為OK,將不可計測者評估為NG。
檢查結果評估:以與上述相同之方法,對50個凸塊計測連接凸塊上之導電性粒子數,將標準偏差/平均值小於0.3之情形評估為○,將0.3以上之情形評估為×。
(捕捉粒子數評估)
與上述同樣地對50個凸塊計測壓接後金凸塊上之導電性粒子數,算出其平均捕捉粒子數與連接前計測之連接凸塊上之導電性粒子數的比例。將65%以上且小於90%之情形評估為○,將90%以上之情形評估為◎,且將小於65%之情形評估為×。
(連接電阻試驗)
於厚度0.5 mm之無鹼玻璃上,藉由以使半導體晶片之鋁薄膜上之金凸塊與鄰接之鋁薄膜上之金凸塊成對之位置關係而連接之方式形成鉭配線(0.8 μm),繼而形成氧化銦錫膜(1400 Å)之連接墊(橫42 μm、縱120 μm)。每連接20個金 凸塊而於上述連接墊上形成氧化銦錫薄膜之引出配線,於引出配線上形成鋁鈦薄膜(鈦1%、3000 Å),獲得連接評估基板。將該連接評估基板之連接墊與附各向異性導電性膜之半導體晶片之金凸塊位置對準,或者於連接評估基板上暫時壓接各向異性導電性膜後,將連接評估基板之連接墊與半導體晶片之金凸塊位置對準,以190℃、10秒、40 MPa之荷重進行壓接,而作成半導體裝置。壓接後,利用四端子法之電阻計對上述引出配線間(20個金凸塊之菊鏈(daisy chain))之電阻值進行測定,作為初期連接電阻值。將該連接電阻測定基板於85℃、85%RH之環境下保持500小時,取出後在25℃下放置1小時後測定連接電阻值,作為可靠性試驗後連接電阻值。
(絕緣性試驗評估)
於厚度0.5 mm之無鹼玻璃上,以半導體晶片之鋁薄膜上之2個金凸塊分別連接之位置關係形成鉭配線(0.8 μm),繼而形成氧化銦錫膜(1400 Å)之連接墊(橫42 μm、縱120 μm)。以可將上述連接墊每隔1個連接5個之方式形成氧化銦錫薄膜之連接配線。於各連接配線上形成氧化銦錫薄膜(1400 Å)之引出配線,於引出配線上形成鋁鈦薄膜(鈦1%、3000 Å),獲得絕緣性評估基板。將該絕緣電阻評估基板之連接墊與附各向異性導電性膜之半導體晶片之金凸塊位置對準,或者於連接評估基板上暫時壓接各向異性導電性膜後,將連接評估基板之連接墊與半導體晶片之金凸塊位置對準,以190℃、10秒、40 MPa之荷重進行壓接, 獲得絕緣電阻試驗基板。一面將該絕緣電阻試驗基板保持於85℃、85%RH,一面使用低電壓低電流電源,於成對之引出配線間施加30 V之直流電壓。每5分鐘測定該配線間之絕緣電阻,測定至絕緣電阻變為10 MΩ以下為止之時間,將該值作為絕緣下降時間。將該絕緣下降時間小於500小時之情形評估為NG,將500小時以上之情形評估為OK。
(位置對準性評估)
將以壓接裝置進行壓接時,產生對準標記讀取誤差之情形評估為NG,將不產生誤差之情形評估為OK。產生誤差之情形時,進行重複操作,計測至可正常壓接為止之次數。
(厚度方向上之導電性粒子間距離之測定)
藉由靶剖面試樣製作裝置(LEICA製造EM TXP),將藉由上述連接電阻試驗製作之半導體裝置之電極中電極間距離最窄、距長邊方向之中心最近之電極間於厚度方向上割斷。使用研磨紙研磨至觀察部位附近為止後,利用寬幅離子束裝置(日立製作所製造型號:E-3500)使所獲得之剖面平滑化。測定對象之割斷面係上述電極間含有5個以上導電性粒子之割斷面。其後於割斷面使用蒸鍍裝置(Vacuum Device製造型號:HPC-1s Osmium coat)蒸鍍鋨,藉此進行導電化處理。使用掃描型電子顯微鏡(日立製作所製造型號:S-4700)進行剖面觀察。
對電極間自距半導體晶片最遠之粒子之中心垂直於厚度 方向地劃出之假想直線、與自距半導體晶片最近之粒子之中心垂直於厚度方向地劃出之假想直線的距離,作為距半導體晶片最近之導電性粒子、與距半導體晶片最遠之導電性粒子的厚度方向上之粒子間距離。距半導體晶片之距離係採用該割斷面中自導電性粒子之中心垂下至Si基板之垂線的長度。
[實施例1]
接著層A
將苯氧基樹脂(玻璃轉移溫度84℃、數量平均分子量9500)90 g、雙酚A型液體環氧樹脂(環氧當量190、25℃下之黏度:14000 mPa.s)10 g、γ-縮水甘油氧基丙基三甲氧基矽烷1.5 g、及乙酸乙酯250 g混合,獲得導電性粒子層用絕緣性樹脂清漆。將該導電性粒子層用絕緣性樹脂清漆塗佈於經剝離處理之厚度38 μm之聚對苯二甲酸乙二酯膜上,在60℃下乾燥15分鐘,獲得膜厚2.8 μm之接著層A。以相同之方法製作黏度測定用薄片,利用流變儀(60℃/min、升溫)測定100℃下之黏度,結果為35000 Pa.s。
絕緣性接著劑層B
將苯氧基樹脂(玻璃轉移溫度91℃、數量平均分子量11300)40 g、雙酚A型液體環氧樹脂(環氧當量190、25℃下之黏度:14000 mPa.s)10 g、及γ-縮水甘油氧基丙基三甲氧基矽烷1.0 g溶解於乙酸乙酯-甲苯之混合溶劑(混合比1:1)中,獲得固形物成分50%之溶液。將含有微膠囊型潛 在性咪唑硬化劑之液體環氧樹脂(微膠囊之平均粒徑5 μm、活性溫度123度、液體環氧樹脂)50 g(含液體環氧樹脂33.5 g)混合分散於上述固形物成分50%之溶液中。然後,將其塗佈於經剝離處理之厚度38 μm之聚對苯二甲酸乙二酯膜上,在60℃下進行15分鐘鼓風乾燥,獲得厚度16 μm之絕緣性接著劑層B。以相同之方法製作黏度測定用薄片,利用流變儀(60℃/min、升溫)測定100℃下之黏度,結果為450 Pa.s。
導電性粒子分散排列片材C
於厚度100 μm之未延伸共聚合聚丙烯膜上,以4 μm之厚度塗佈腈橡膠乳膠-甲基丙烯酸甲酯之接枝共聚物接著劑作為黏著層。於該附黏著層之聚丙烯膜上,將平均直徑3.8 μm之鍍金塑膠粒子(丙烯酸系樹脂、導電性粒子)以導電性粒子形成複數層之方式敷填於該黏著劑表面,其後,用包含軟質橡膠之刮板將過剩之導電性粒子刮落,藉此進行大致無間隙之單層填充。填充率為80%。使用雙軸延伸裝置(東洋精機X6H-S、縮放儀方式之角拉伸型雙軸延伸裝置)並使用縱橫各10個之夾頭固定該膜,在125℃下進行120秒預熱後,以10%/s之速度延伸2.4倍且固定,獲得導電性粒子分散排列片材C。使用顯微鏡測定導電性粒子數,結果100 μm×100 μm之範圍內之導電性粒子數為134個。導電性粒子之平均粒子間隔為12.0 μm,導電性粒子分散排列成大致正三角形,凝集粒子為0。
各向異性導電性膜D
於上述導電性粒子分散排列片材C之導電性粒子分散排列面積層接著層A,在80℃、0.4 MPa之條件下進行真空層壓而製作導電性粒子層,剝離聚對苯二甲酸乙二酯膜,於其剝離面積層絕緣性接著劑層B,並以55℃、0.6 MPa之條件進行真空層壓,其後剝離聚對苯二甲酸乙二酯膜,獲得各向異性導電性膜D。
附各向異性導電性膜之半導體晶片E
於上述各向異性導電性膜D之接著層A側,將上述半導體晶片之金凸塊配置面側進行真空層壓(55℃、1.0 MPa),其後,將半導體晶片與各向異性導電性膜一起自附黏著層之聚丙烯膜剝離,獲得附各向異性導電性膜之半導體晶片E。
利用雷射顯微鏡對附各向異性導電性膜之半導體晶片E中各向異性導電性膜之絕緣性樹脂成分之厚度進行測定,結果為18.8 μm。又,金凸塊上之各向異性導電性膜之絕緣性樹脂成分之厚度為3.8 μm。將該附各向異性導電性膜之半導體晶片E冷凍割斷,進行剖面觀察,確認50個導電性粒子之位置。確認到50個中50個均位於較凸塊之平均高度更靠表面側。
[實施例2]
導電性粒子層F
於厚度100 μm之未延伸共聚合聚丙烯膜上,以4 μm之厚度塗佈腈橡膠乳膠-甲基丙烯酸甲酯之接枝共聚物接著劑作為黏著層。於該附黏著層之聚丙烯膜上,將平均直徑 3.8 μm之鍍金塑膠粒子(丙烯酸系樹脂、導電性粒子),以導電性粒子形成複數層之方式敷填於該黏著劑表面,其後,用包含軟質橡膠之刮板將過剩之導電性粒子刮落,藉此進行大致無間隙之單層填充。填充率為80%。將苯氧基樹脂(玻璃轉移溫度84℃、數量平均分子量9500)95 g、雙酚A型液體環氧樹脂(環氧當量190、25℃下之黏度:14000 mPa.s)5 g、及γ-縮水甘油氧基丙基三甲氧基矽烷1.2 g、甲基乙基酮250 g混合,獲得導電性粒子層用絕緣性樹脂清漆。將該導電性粒子層用絕緣性樹脂清漆塗佈於上述敷填有導電性粒子之膜上,在60℃下乾燥15分鐘,獲得厚度11 μm之導電性粒子填充膜。
使用雙軸延伸裝置(東洋精機X6H-S、縮放儀方式之角拉伸型雙軸延伸裝置)並於縱橫方向上各使用10個夾頭將上述導電性粒子填充膜固定,在125℃下進行120秒預熱後,以10%/s之速度延伸2.4倍且固定,獲得導電性粒子層F。使用顯微鏡測定導電性粒子數,結果100 μm×100 μm之範圍內之導電性粒子數為139個。導電性粒子之平均粒子間隔為12.0 μm,導電性粒子分散排列成大致正三角形,凝集粒子為0。切斷該膜,利用電子顯微鏡測定導電性粒子層F之絕緣性樹脂之膜厚,結果為1.8 μm。
附絕緣性接著劑層之半導體晶片G
除設膜厚為18 μm之外,與實施例1相同地製作絕緣性接著劑層。
於該絕緣性接著劑層上將該半導體晶片之金凸塊配置面 側進行真空層壓(55℃、1.0 MPa),其後,將半導體晶片與絕緣性接著劑層一起自聚對苯二甲酸乙二酯膜剝離,除去多餘之絕緣性接著劑層,獲得附絕緣性接著劑層之半導體晶片G。
附各向異性導電性膜之半導體晶片H
於導電性粒子層F上將附絕緣性接著劑層之半導體晶片G之絕緣性接著劑層面側進行層壓(55℃、1.0 MPa),其後,將附絕緣性接著劑層之半導體晶片與導電性粒子層一起自附黏著層之聚丙烯膜剝離,獲得附各向異性導電性膜之半導體晶片H。
利用雷射顯微鏡對附各向異性導電性膜之半導體晶片H中各向異性導電性膜之絕緣性樹脂成分之厚度進行測定,結果為19.1 μm。又,金凸塊上之各向異性導電性膜之絕緣性樹脂成分之厚度為4.1 μm。將該附各向異性導電性膜之半導體晶片H冷凍割斷,進行剖面觀察,確認50個導電性粒子之位置。確認到50個中50個均位於較凸塊之平均高度更靠表面側。
[實施例3]
除設接著層A之厚度為4.0 μm之外,與實施例1相同地獲得附各向異性導電性膜之半導體晶片I。
利用雷射顯微鏡對附各向異性導電性膜之半導體晶片I中各向異性導電性膜之絕緣性樹脂成分的厚度進行測定,結果為19.8 μm。又,金凸塊上之各向異性導電性膜之絕緣性樹脂成分之厚度為4.8 μm。將該附各向異性導電性膜 之半導體晶片I冷凍割斷,進行剖面觀察,確認50個導電性粒子之位置。確認到50個中50個均位於較凸塊之平均高度更靠表面側。
[實施例4]
附各向異性導電性膜之半導體晶片J
除設膜厚為19.5 μm之外,與實施例2相同地製作附絕緣性接著劑層之半導體晶片,並真空層壓(40℃、0.5 MPa)於與實施例1相同地製作之導電性粒子分散排列片材C上,其後,將附絕緣性接著劑層之半導體晶片與導電性粒子一起自附黏著層之聚丙烯膜剝離,獲得附各向異性導電性膜之半導體晶片J。
利用雷射顯微鏡對附各向異性導電性膜之半導體晶片J之各向異性導電性膜之絕緣性樹脂成分之厚度進行測定,結果為18.8 μm。又,金凸塊上之各向異性導電性膜之絕緣性樹脂成分之厚度為3.8 μm。自各向異性導電性膜表面,使用顯微鏡測定導電性粒子自表面之露出量。測定50個導電性粒子後發現其全數露出,平均露出高度為0.3 μm。
[比較例1]
除設膜厚為19 μm之外,與實施例1相同地製作絕緣性接著劑層,並層壓(50℃、0.5 MPa)於與實施例1相同地製作之導電性粒子分散排列片材C上,而獲得各向異性導電性膜K。將該各向異性導電性膜K以寬度1.6 mm切縫。以覆蓋連接評估基板上之連接電極,且使導電性粒子層配置於 基板側之方式,以80℃、1秒、0.2 MPa之條件暫時壓接經切縫之各向異性導電性膜K。於連接電阻試驗、絕緣性試驗評估中,除使用以上述方法暫時壓接於連接評估基板上者,並使用半導體晶片上未附有各向異性導電性膜者以外,以與其他實施例、比較例相同之條件、方法進行。
[比較例2]
將苯氧基樹脂(玻璃轉移溫度91℃、數量平均分子量11300)40 g、雙酚A型液狀環氧樹脂(環氧當量190、25℃下之黏度:14000 mPa.s)10 g、及γ-縮水甘油氧基丙基三甲氧基矽烷1.0 g溶解於乙酸乙酯-甲苯之混合溶劑(混合比1:1)中,獲得固形物成分50%之溶液。將含有微膠囊型潛在性咪唑硬化劑之液體環氧樹脂(微膠囊之平均粒徑5 μm、活性溫度123度、液體環氧樹脂)50 g(含液狀環氧樹脂33.5 g)混合分散於上述固形物成分50%之溶液中,獲得各向異性導電性膜用清漆。於該各向異性導電性膜用清漆中,以導電性粒子密度成為50000個/mm2之方式添加平均直徑3.8 μm之鍍金塑膠粒子(丙烯酸系樹脂、導電性粒子),塗佈於厚度50 μm之聚對苯二甲酸乙二酯膜上,在60℃下乾燥15分鐘,獲得膜厚20 μm之各向異性導電性膜L。
於該各向異性導電性膜L上將該半導體晶片之金凸塊配置面側進行真空層壓(55℃、1.0 MPa),其後,將半導體晶片與各向異性導電性膜L一起自聚對苯二甲酸乙二酯膜剝離,除去多餘之各向異性導電性膜,獲得附各向異性導電性膜之半導體晶片M。
利用雷射顯微鏡對附各向異性導電性膜之半導體晶片M中之各向異性導電性膜之絕緣性樹脂成分之厚度進行測定,結果為19.8 μm。又,金凸塊上之各向異性導電性膜之絕緣性樹脂成分之厚度為4.8 μm。將該半導體晶片M冷凍割斷,進行剖面觀察。觀察到導電性粒子於厚度方向上大致均勻分佈。
[比較例3]
除於各向異性導電性膜用清漆中,以導電性粒子密度成為10000個/mm2之方式添加平均直徑3.8 μm之鍍金塑膠粒子(丙烯酸系樹脂、導電性粒子)以外,與比較例2相同地獲得各向異性導電性膜N。於該各向異性導電性膜N上將該半導體晶片之金凸塊配置面側進行真空層壓(55℃、1.0 MPa),其後,將半導體晶片與各向異性導電性膜N一起自聚對苯二甲酸乙二酯膜剝離,並除去多餘之各向異性導電性膜,獲得附各向異性導電性膜之半導體晶片O。
利用雷射顯微鏡對附各向異性導電性膜之半導體晶片O中各向異性導電性膜之絕緣性樹脂成分之厚度進行測定,結果為19.7 μm。又,金凸塊上之各向異性導電性膜之絕緣性樹脂成分之厚度為4.7 μm。將該半導體晶片O冷凍割斷,進行剖面觀察。觀察到導電性粒子於厚度方向上大致均勻分佈。
將各實施例、比較例之各項目之評估結果示於以下之表1。
自表1可知,示於各實施例之附各向異性導電性膜之半導體晶片其半導體裝置之厚度方向上的導電性粒子間距離為導電性粒子之平均直徑的2倍以下,於檢查性、可靠性試驗後之連接電阻、絕緣性試驗評估結果、位置對準性之任一項皆優異。
(半導體晶圓之製作)
於直徑6英吋、厚度0.28 mm之矽晶圓上整個面地形成氧化膜,形成切出後之外形尺寸為縱橫1.6 mm×15.1 mm之晶片530個。於各晶片區域之距外邊部20 μm之內側,以分別為2 μm間隔之方式沿長邊側各形成橫58 μm、縱120 μm之鋁薄膜(厚度1000 Å)480個。為於該等鋁薄膜上以成為10 μm間隔之方式分別形成2個橫20 μm、縱100 μm之金凸塊(厚度15 μm),而於距各金凸塊配置部位之外周部7 μm之內側,除留出橫6 μm、縱86 μm之開口部以外之部分形成包含氧化矽/氮化矽的厚度0.1 μm之保護膜。其後,形成上 述金凸塊。然後,研磨至厚度0.28 mm為止,並於背面貼附切晶膜(Lintec公司製造,D-650),獲得半導體晶圓。作為電路電極之金凸塊以未配置有電極之保護膜面為基準之平均高度為15.0 μm。
(切晶性評價)
使用切晶裝置(DISCO公司製造、DAD3350、刀片NBC ZH2060、30000 rpm,切削速度50 mm/s),將藉由各實施例製造之附各向異性導電性膜之半導體晶圓,以切出530個晶片(1.6 mm×15.1 mm)之方式進行切晶(切晶膜之切入量為20 μm)。將切晶所得之晶片作為評估用晶片。
外觀評估:將切出之晶片中附著有切晶屑者為5%以上之情形評估為×,將5%以下之情形評估為○。
剝離評估:觀察所切出之晶片的切晶端面,將各向異性導電性膜自切晶端面之平均剝離量小於25 μm之情形評估為○,將25 μm以上之情形評估為×。
(附各向異性導電性膜之半導體晶圓之檢查評估)
檢查性評估:使用顯微鏡,自該附各向異性導電性膜之晶圓的各向異性導電性膜表面計測金凸塊上之導電性粒子數。將可計測者評估為OK,將不可計測者評估為NG。
檢查結果評估:以與上述相同之方法,對50個凸塊計測連接凸塊上之導電性粒子數,將標準偏差/平均值小於0.3之情形評估為○,將0.3以上之情形評估為×。
(捕捉粒子數評估)
與上述同樣地對50個凸塊計測壓接後金凸塊上之導電性 粒子數,算出其平均捕捉粒子數與連接前計測之連接凸塊上之導電性粒子數的比例。將65%以上且小於90%之情形評估為○,將90%以上之情形評估為◎,且將小於65%之情形評估為×。
(連接電阻試驗)
於厚度0.5 mm之無鹼玻璃上,藉由以使評估用晶片之鋁薄膜上之金凸塊與鄰接之鋁薄膜上之金凸塊成對之位置關係而連接之方式形成鉭配線(0.8 μm),繼而形成氧化銦錫膜(1400 Å)之連接墊(橫42 μm、縱120 μm)。每連接20個金凸塊而於上述連接墊上形成氧化銦錫薄膜之引出配線,於引出配線上形成鋁鈦薄膜(鈦1%、3000 Å),獲得連接評估基板。將該連接評估基板之連接墊與附各向異性導電性膜之半導體晶片之金凸塊位置對準,以190℃、10秒、40 MPa之荷重進行壓接。壓接後,利用四端子法之電阻計對上述引出配線間(20個金凸塊之菊鏈)之電阻值進行測定,作為初期連接電阻值。將該連接電阻測定基板於85℃、85%RH之環境下保持500小時,取出後在25℃下放置1小時後測定連接電阻值,作為可靠性試驗後電阻值。
(絕緣性試驗評估)
於厚度0.5 mm之無鹼玻璃上,以評估用晶片之鋁薄膜上之2個金凸塊分別連接之位置關係形成鉭配線(0.8 μm),繼而形成氧化銦錫膜(1400 Å)之連接墊(橫42 μm、縱120 μm)。以可將上述連接墊每隔1個連接5個之方式形成氧化銦錫薄膜之連接配線。於各連接配線上形成氧化銦錫薄膜 (1400 Å)之引出配線,於引出配線上形成鋁鈦薄膜(鈦1%、3000 Å),獲得絕緣性評估基板。將該絕緣電阻評估基板之連接墊與附各向異性導電性膜之半導體晶片之金凸塊位置對準,以190℃、10秒、40 MPa之荷重進行壓接,獲得絕緣電阻試驗基板。一面將該絕緣電阻試驗基板保持於85℃、85%RH,一面使用低電壓低電流電源,於成對之引出配線間施加30 V之直流電壓。每5分鐘測定該配線間之絕緣電阻,測定至絕緣電阻變為10 MΩ以下為止之時間,將該值作為絕緣下降時間。將該絕緣下降時間小於500小時之情形評估為NG,將500小時以上之情形評估為OK。
(位置對準性評價)
將以壓接裝置進行壓接時,產生對準標記讀取誤差之情形評估為NG,將不產生誤差之情形評估為OK。產生誤差之情形時,進行重複操作,計測至可正常壓接為止之次數。
[實施例5]
接著層A
將苯氧基樹脂(玻璃轉移溫度84℃、數量平均分子量9500)90 g、雙酚A型液體環氧樹脂(環氧當量190、25℃下之黏度:14000 mPa.s)10 g、γ-縮水甘油氧基丙基三甲氧基矽烷1.5 g、及乙酸乙酯250 g混合,獲得導電性粒子層用絕緣性樹脂清漆。將該導電性粒子層用絕緣性樹脂清漆塗佈於經剝離處理之厚度38 μm之聚對苯二甲酸乙二酯膜 上,在60℃下乾燥15分鐘,獲得膜厚2.8 μm之接著層A。以相同之方法製作黏度測定用薄片,以流變儀(60℃/min、升溫)測定100℃下之黏度,結果為35000 Pa.s。
絕緣性接著劑層B
將苯氧基樹脂(玻璃轉移溫度91℃、數量平均分子量11300)40 g、雙酚A型液體環氧樹脂(環氧當量190、25℃下之黏度:14000 mPa.s)10 g、及γ-縮水甘油氧基丙基三甲氧基矽烷1.0 g溶解於乙酸乙酯-甲苯之混合溶劑(混合比1:1)中,獲得固形物成分50%之溶液。將含有微膠囊型潛在性咪唑硬化劑之液體環氧樹脂(微膠囊之平均粒徑5 μm、活性溫度123度、液體環氧樹脂)50 g(含液體環氧樹脂33.5 g)混合分散於上述固形物成分50%之溶液中。然後,將其塗佈於厚度38 μm之經剝離處理之聚對苯二甲酸乙二酯膜上,在60℃下進行15分鐘鼓風乾燥,獲得厚度16 μm之絕緣性接著劑層B。以相同之方法製作黏度測定用薄片,利用流變儀(60℃/min、升溫)測定100℃下之黏度,結果為450 Pa.s。
導電性粒子分散排列片材C
於厚度100 μm之未延伸共聚合聚丙烯膜上,以4 μm之厚度塗佈腈橡膠乳膠-甲基丙烯酸甲酯之接枝共聚物接著劑作為黏著層。於該附黏著層之聚丙烯膜上,將平均直徑3.8 μm之鍍金塑膠粒子(丙烯酸系樹脂、導電性粒子)以導電性粒子形成複數層之方式敷填於該黏著劑表面,其後,用包含軟質橡膠之刮板將過剩之導電性粒子刮落,藉此進 行大致無間隙之單層填充。填充率為80%。使用雙軸延伸裝置(東洋精機X6H-S、縮放儀方式之角拉伸型雙軸延伸裝置)並於縱橫方向上各使用10個夾頭將該膜固定,在125℃下進行120秒預熱後,以10%/s之速度延伸2.4倍且固定,獲得導電性粒子分散排列片材C。使用顯微鏡測定導電性粒子數,結果100 μm×100 μm之範圍內之導電性粒子數為134個。導電性粒子之平均粒子間隔為12.0 μm,導電性粒子分散排列成大致正三角形,凝集粒子為0。
各向異性導電性膜D
於上述導電性粒子分散排列片材C之導電性粒子分散排列面積層接著層A,在80℃、0.4 MPa之條件下進行真空層壓而製作導電性粒子層,剝離聚對苯二甲酸乙二酯膜,於其剝離面積層絕緣性接著劑層B,並以55℃、0.6 MPa之條件進行真空層壓,其後剝離聚對苯二甲酸乙二酯膜,獲得各向異性導電性膜D。
附各向異性導電性膜之半導體晶圓E
於上述各向異性導電性膜D上,將上述半導體晶圓之金凸塊配置面側進行真空層壓(55℃、1.0 MPa),其後,將半導體晶圓與各向異性導電性膜一起自附黏著層之聚丙烯膜剝離,獲得附各向異性導電性膜之半導體晶圓E。
利用雷射顯微鏡對附各向異性導電性膜之半導體晶圓E中各向異性導電性膜之絕緣性樹脂成分之厚度進行測定,結果為18.8 μm。又,金凸塊上之各向異性導電性膜之絕緣性樹脂成分之厚度為3.8 μm。將該附各向異性導電性膜 之半導體晶圓E冷凍割斷,進行剖面觀察,確認50個導電性粒子之位置。確認到50個中50個均位於較凸塊之平均高度更靠表面側。
[實施例6]
導電性粒子層F
於厚度100 μm之未延伸共聚合聚丙烯膜上,以4 μm之厚度塗佈腈橡膠乳膠-甲基丙烯酸甲酯之接枝共聚物接著劑作為黏著層。於該附黏著層之聚丙烯膜上,將平均直徑3.8 μm之鍍金塑膠粒子(丙烯酸系樹脂、導電性粒子),以導電性粒子形成複數層之方式敷填於該黏著劑表面,其後,用包含軟質橡膠之刮板將過剩之導電性粒子刮落,藉此進行大致無間隙之單層填充。填充率為80%。將苯氧基樹脂(玻璃轉移溫度84℃、數量平均分子量9500)95 g、雙酚A型液體環氧樹脂(環氧當量190、25℃下之黏度:14000 mPa.s)5 g、及γ-縮水甘油氧基丙基三甲氧基矽烷1.2 g、甲基乙基酮250 g混合,獲得導電性粒子層用絕緣性樹脂清漆。將該導電性粒子層用絕緣性樹脂清漆塗佈於上述敷填有導電性粒子之膜上,在60℃下乾燥15分鐘,獲得厚度11 μm之導電性粒子填充膜。
使用雙軸延伸裝置(東洋精機X6H-S、縮放儀方式之角拉伸型雙軸延伸裝置)並於縱橫方向上各使用10個夾頭將上述導電性粒子填充膜固定,在125℃下進行120秒預熱後,以10%/s之速度延伸2.4倍且固定,獲得導電性粒子層F。使用顯微鏡測定導電性粒子數,結果100 μm×100 μm之範 圍內之導電性粒子數為139個。導電性粒子之平均粒子間隔為12.0 μm,導電性粒子分散排列成大致正三角形,凝集粒子為0。切斷該膜,利用電子顯微鏡測定導電性粒子層F之絕緣性樹脂之膜厚,結果為1.8 μm。
附絕緣性接著劑層之半導體晶圓G
除設膜厚為18 μm之外,與實施例1相同地製作絕緣性接著劑層。
於該絕緣性接著劑層上將該半導體晶圓之金凸塊配置面側進行真空層壓(55℃、1.0 MPa),其後,將半導體晶圓與絕緣性接著劑層一起自聚對苯二甲酸乙二酯膜剝離,除去多餘之絕緣性接著劑層,獲得附絕緣性接著劑層之半導體晶圓G。
附各向異性導電性膜之半導體晶圓H
於導電性粒子層F上將附絕緣性接著劑層之半導體晶圓G之絕緣性接著劑層面側進行層壓(55℃、1.0 MPa),其後,將附絕緣性接著劑層之半導體晶圓與導電性粒子層一起自附黏著層之聚丙烯膜剝離,獲得附各向異性導電性膜之半導體晶圓H。
利用雷射顯微鏡對附各向異性導電性膜之半導體晶圓H中各向異性導電性膜之絕緣性樹脂成分之厚度進行測定,結果為19.0 μm。又,金凸塊上之各向異性導電性膜之絕緣性樹脂成分之厚度為4.0 μm。將該附各向異性導電性膜之半導體晶圓H冷凍割斷,進行剖面觀察,確認50個導電性粒子之位置。確認到50個中50個均位於較凸塊之平均高 度更靠表面側。
[實施例7]
除設接著層A之厚度為4.0 μm之外,與實施例1相同地獲得附各向異性導電性膜之半導體晶圓I。
利用雷射顯微鏡對附各向異性導電性膜之半導體晶圓I中各向異性導電性膜之絕緣性樹脂成分的厚度進行測定,結果為19.8 μm。又,金凸塊上之各向異性導電性膜之絕緣性樹脂成分之厚度為4.8 μm。將該附各向異性導電性膜之半導體晶圓I冷凍割斷,進行剖面觀察,確認50個導電性粒子之位置。確認到50個中50個均位於較凸塊之平均高度更靠表面側。
[實施例8]
附各向異性導電性膜之半導體晶圓J
除設膜厚為19.5 μm之外,與實施例2相同地製作附絕緣性接著劑層之半導體晶圓,真空層壓(40℃、0.5 MPa)於與實施例1相同地製作之導電性粒子分散排列片材C上,其後,將附絕緣性接著劑層之半導體晶圓與導電性粒子一起自附黏著層之聚丙烯膜剝離,獲得附各向異性導電性膜之半導體晶圓J。
利用雷射顯微鏡對附各向異性導電性膜之半導體晶圓J中各向異性導電性膜之絕緣性樹脂成分之厚度進行測定,結果為18.7 μm。又,金凸塊上之各向異性導電性膜之絕緣性樹脂成分之厚度為3.7 μm。自各向異性導電性膜表面,使用顯微鏡測定導電性粒子自表面之露出量。測定50 個導電性粒子,結果50個全部露出,平均露出高度為0.25 μm。
[比較例4]
將苯氧基樹脂(玻璃轉移溫度91℃、數量平均分子量11300)40 g、雙酚A型液狀環氧樹脂(環氧當量190、25℃下之黏度:14000 mPa.s)10 g、及γ-縮水甘油氧基丙基三甲氧基矽烷1.0 g溶解於乙酸乙酯-甲苯之混合溶劑(混合比1:1)中,獲得固形物成分50%之溶液。將含有微膠囊型潛在性咪唑硬化劑之液體環氧樹脂(微膠囊之平均粒徑5 μm、活性溫度123度、液體環氧樹脂)50 g(含液體環氧樹脂33.5 g)混合分散於上述固形物成分50%之溶液中,獲得各向異性導電性膜用清漆。於該各向異性導電性膜用清漆中,以導電性粒子密度成為50000個/mm2之方式添加平均直徑3.8 μm之鍍金塑膠粒子(丙烯酸系樹脂、導電性粒子),塗佈於厚度50 μm之聚對苯二甲酸乙二酯膜上,在60℃下乾燥15分鐘,獲得膜厚20 μm之各向異性導電性膜K。
於該各向異性導電性膜K上將該半導體晶圓之金凸塊配置面側進行真空層壓(55℃、1.0 MPa),其後,將半導體晶圓與各向異性導電性膜K一起自聚對苯二甲酸乙二酯膜剝離,除去多餘之各向異性導電性膜,獲得附各向異性導電性膜之半導體晶圓L。
利用雷射顯微鏡對附各向異性導電性膜之半導體晶圓L中各向異性導電性膜之絕緣性樹脂成分之厚度進行測定,結果為19.7 μm。又,金凸塊上之各向異性導電性膜之絕 緣性樹脂成分之厚度為4.7 μm。將該半導體晶圓L冷凍割斷,進行剖面觀察。觀察到導電性粒子於厚度方向上並不偏向存在而為大致均勻分佈。
[比較例5]
除於各向異性導電性膜用清漆中,以導電性粒子密度成為10000個/mm2之方式添加平均直徑3.8 μm之鍍金塑膠粒子(丙烯酸系樹脂、導電性粒子)以外,與比較例1相同地獲得各向異性導電性膜M。於該各向異性導電性膜M上將該半導體晶片之金凸塊配置面側進行真空層壓(55℃、1.0 MPa),其後,將半導體晶圓與各向異性導電性膜M一起自聚對苯二甲酸乙二酯膜剝離,並除去多餘之各向異性導電性膜,獲得附各向異性導電性膜之半導體晶圓N。
利用雷射顯微鏡對附各向異性導電性膜之半導體晶圓N中各向異性導電性膜之絕緣性樹脂成分之厚度進行測定,結果為19.8 μm。又,金凸塊上之各向異性導電性膜之絕緣性樹脂成分之厚度為4.8 μm。將該半導體晶圓N冷凍割斷,進行剖面觀察。導電性粒子於厚度方向上並不偏向存在而為大致均勻分佈。
將各實施例、比較例之各項目之評估結果示於以下之表2。
自表2可知,示於各實施例之附各向異性導電性膜之半導體晶圓於檢查性、切晶性、可靠性試驗後之連接電阻、絕緣性試驗評估結果、位置對準性之任一項皆優異。
[產業上之可利用性]
本發明可適合地利用於半導體晶片積層化連接、半導體晶片與內插器之連接等。
1‧‧‧半導體晶片
2‧‧‧電路電極
3‧‧‧各向異性導電性膜
4‧‧‧導電性粒子
5‧‧‧絕緣性接著劑層
6‧‧‧導電性粒子層
7‧‧‧支持體
8‧‧‧黏著劑層
9‧‧‧半導體晶圓
10‧‧‧接著劑
11‧‧‧電路基板
12‧‧‧連接電極
13‧‧‧半導體元件部
14‧‧‧Si基板
15‧‧‧自距半導體晶片最遠之粒子之中心垂直於厚度方向地劃出之假想直線
16‧‧‧自距半導體晶片最近之粒子之中心垂直於厚度方向地劃出之假想直線
圖1係表示本實施形態之附各向異性導電性膜之半導體晶片之一例的剖面圖。
圖2係表示本實施形態之附各向異性導電性膜之半導體晶片(包含導電性粒子層/絕緣性接著劑層之結構)之一例的剖面圖。
圖3係表示本實施形態之附各向異性導電性膜之半導體晶片之製造方法(方法1)之一例的概略圖。(a)係表示於以支持體、導電性粒子在剖面厚度方向上偏向存在於支持體 側之各向異性導電性膜層的順序積層而成之積層體上,將於單面具有複數個電路電極之半導體晶片的該電路電極面進行層壓之步驟。(b)係表示將經該層壓之該半導體晶片與該各向異性導電性膜層一起自該支持體上剝離之步驟。
圖4係表示本實施形態之附各向異性導電性膜之半導體晶片之製造方法(方法2)之一例的概略圖。(a)係表示於單面具有複數個電路電極之半導體晶片的電路電極面,填充絕緣性接著劑之步驟。(b)係表示於所獲得之附絕緣性接著劑層之半導體晶片上,將形成於支持體上,且導電性粒子於絕緣性樹脂中以大致平面狀分散排列1層之導電性粒子層進行層壓之步驟。
圖5係表示本實施形態之附各向異性導電性膜之半導體晶片之製造方法(方法3)之一例的概略圖。(a)係表示於單面具有複數個電路電極之半導體晶片的電路電極面,填充絕緣性接著劑之步驟。(b)係表示於所獲得之附絕緣性接著劑層之半導體晶片上,將分散排列形成於積層在支持體上之黏著劑層上的導電性粒子進行層壓之步驟。
圖6係表示本實施形態之附各向異性導電性膜之半導體晶圓之一例的剖面圖。
圖7係表示本實施形態之附各向異性導電性膜之半導體晶圓(包含導電性粒子層/絕緣性接著劑層之結構)之一例的剖面圖。
圖8係表示本實施形態之附各向異性導電性膜之半導體晶圓之製造方法(方法1)之一例的概略圖。(a)係表示於以 支持體、導電性粒子在剖面厚度方向上偏向存在於支持體側之各向異性導電性膜層的順序積層而成之積層體上,將於單面具有複數個電路電極之半導體晶片的該電路電極面進行層壓之步驟。(b)係表示將經該層壓之該半導體晶片與該各向異性導電性膜層一起自該支持體上剝離之步驟。
圖9係表示本實施形態之附各向異性導電性膜之半導體晶圓之製造方法(方法2)之一例的概略圖。(a)係表示於單面具有複數個電路電極之半導體晶圓的電路電極面,填充絕緣性接著劑之步驟。(b)係表示於所獲得之附絕緣性接著劑層之半導體晶圓上,將形成於支持體上,且導電性粒子於絕緣性樹脂中以大致平面狀分散排列1層之導電性粒子層進行層壓之步驟。
圖10係表示本實施形態之附各向異性導電性膜之半導體晶圓之製造方法(方法3)之一例的概略圖。(a)係表示於單面具有複數個電路電極之半導體晶圓的電路電極面,填充絕緣性接著劑之步驟。(b)係表示於所獲得之附絕緣性接著劑層之半導體晶圓上,將分散排列形成於積層在支持體上之黏著劑層上的導電性粒子進行層壓之步驟。
圖11係表示本實施形態之半導體裝置之一例的剖面圖。
1‧‧‧半導體晶片
2‧‧‧電路電極
3‧‧‧各向異性導電性膜
4‧‧‧導電性粒子

Claims (10)

  1. 一種附各向異性導電性膜之半導體晶片之製造方法,該附各向異性導電性膜之半導體晶片包含單面具有複數個電路電極之半導體晶片、及覆蓋該電路電極之各向異性導電性膜;該各向異性導電性膜包含絕緣性樹脂成分及導電性粒子,且該各向異性導電性膜中所含之全導電性粒子數之60%以上存在於較該電路電極之平均高度更靠該各向異性導電性膜之表面側;且該方法包含以下步驟:於依序積層支持體及導電性粒子在剖面厚度方向上偏向存在於支持體側之各向異性導電性膜層而成的積層體上,將單面具有複數個電路電極之半導體晶片的該電路電極面進行層壓之步驟;及將經該層壓之該半導體晶片與該各向異性導電性膜層一起自該支持體剝離之步驟。
  2. 如請求項1之方法,其中該各向異性導電性膜層包含絕緣性接著劑層及導電性粒子層,該導電性粒子層係該導電性粒子於絕緣性樹脂中以大致平面狀分散排列1層。
  3. 一種附各向異性導電性膜之半導體晶片之製造方法,該附各向異性導電性膜之半導體晶片包含單面具有複數個電路電極之半導體晶片、及覆蓋該電路電極之各向異性導電性膜;該各向異性導電性膜包含絕緣性樹脂成分及導電性粒子,且該各向異性導電性膜中所含之全導電性 粒子數之60%以上存在於較該電路電極之平均高度更靠該各向異性導電性膜之表面側;且該各向異性導電性膜包含覆蓋該電路電極之絕緣性接著劑層及導電性粒子層,該導電性粒子層係該導電性粒子於絕緣性樹脂中以大致平面狀分散排列1層;且該方法包含以下步驟:於單面具有複數個電路電極之半導體晶片的電路電極面,填充絕緣性接著劑之步驟;於所獲得之附絕緣性接著劑層之半導體晶片上,將形成於支持體上且導電性粒子於絕緣性樹脂中以大致平面狀分散排列1層之導電性粒子層進行層壓之步驟;及將該附絕緣性接著劑層之半導體晶片與該導電性粒子層一起自該支持體剝離之步驟。
  4. 一種附各向異性導電性膜之半導體晶片之製造方法,該附各向異性導電性膜之半導體晶片包含單面具有複數個電路電極之半導體晶片、及覆蓋該電路電極之各向異性導電性膜;該各向異性導電性膜包含絕緣性樹脂成分及導電性粒子,且該各向異性導電性膜中所含之全導電性粒子數之60%以上存在於較該電路電極之平均高度更靠該各向異性導電性膜之表面側;且該各向異性導電性膜包含覆蓋該電路電極之絕緣性接著劑層及導電性粒子層,該導電性粒子層係該導電性粒子於絕緣性樹脂中以大致平面狀分散排列1層;且該方法包含以下步驟: 於單面具有複數個電路電極之半導體晶片的電路電極面,填充絕緣性接著劑之步驟;於所獲得之附絕緣性接著劑層之半導體晶片上,將分散排列形成於積層在支持體上之黏著劑層上的導電性粒子進行層壓之步驟;及將該附絕緣性接著劑層之半導體晶片與該導電性粒子一起自積層在該支持體上之黏著劑層剝離之步驟。
  5. 如請求項1至4中任一項之方法,其中於該層壓步驟中,以20℃~100℃進行真空層壓。
  6. 一種附各向異性導電性膜之半導體晶圓之製造方法,該附各向異性導電性膜之半導體晶圓包含單面具有複數個電路電極之半導體晶圓、及覆蓋該電路電極之各向異性導電性膜;該各向異性導電性膜包含絕緣性樹脂成分及導電性粒子,且該各向異性導電性膜中所含之全導電性粒子數之60%以上存在於較該電路電極之平均高度更靠該各向異性導電性膜之表面側;且該方法包含以下步驟:於依序積層支持體及導電性粒子在剖面厚度方向上偏向存在於支持體側之各向異性導電性膜層而成的積層體上,將單面具有複數個電路電極之半導體晶圓的該電路電極面進行層壓之步驟;及將經該層壓之該半導體晶圓與該各向異性導電性膜層一起自該支持體剝離之步驟。
  7. 如請求項6之方法,其中 該各向異性導電性膜層包含絕緣性接著劑層及導電性粒子層,該導電性粒子層係該導電性粒子於絕緣性樹脂中以大致平面狀分散排列1層。
  8. 一種附各向異性導電性膜之半導體晶圓之製造方法,該附各向異性導電性膜之半導體晶圓包含單面具有複數個電路電極之半導體晶圓、及覆蓋該電路電極之各向異性導電性膜;該各向異性導電性膜包含絕緣性樹脂成分及導電性粒子,且該各向異性導電性膜中所含之全導電性粒子數之60%以上存在於較該電路電極之平均高度更靠該各向異性導電性膜之表面側;且該各向異性導電性膜包含覆蓋該電路電極之絕緣性接著劑層及導電性粒子層,該導電性粒子層係該導電性粒子於絕緣性樹脂中以大致平面狀分散排列1層;且該方法包含以下步驟:於單面具有複數個電路電極之半導體晶圓的電路電極面,填充絕緣性接著劑之步驟;於所獲得之附絕緣性接著劑層之半導體晶圓上,將形成於支持體上且導電性粒子於絕緣性樹脂中以大致平面狀分散排列1層之導電性粒子層進行層壓之步驟;及將該附絕緣性接著劑層之半導體晶圓與該導電性粒子層一起自該支持體剝離之步驟。
  9. 一種附各向異性導電性膜之半導體晶圓之製造方法,該附各向異性導電性膜之半導體晶圓包含單面具有複數個電路電極之半導體晶圓、及覆蓋該電路電極之各向異性 導電性膜;該各向異性導電性膜包含絕緣性樹脂成分及導電性粒子,且該各向異性導電性膜中所含之全導電性粒子數之60%以上存在於較該電路電極之平均高度更靠該各向異性導電性膜之表面側;且該各向異性導電性膜包含覆蓋該電路電極之絕緣性接著劑層及導電性粒子層,該導電性粒子層係該導電性粒子於絕緣性樹脂中以大致平面狀分散排列1層;且該方法包含以下步驟:於單面具有複數個電路電極之半導體晶圓的電路電極面,填充絕緣性接著劑之步驟;於所獲得之附絕緣性接著劑層之半導體晶圓上,將分散排列形成於積層在支持體上之黏著劑層上的導電性粒子進行層壓之步驟;及將該附絕緣性接著劑層之半導體晶圓與該導電性粒子一起自積層在該支持體上之黏著劑層剝離之步驟。
  10. 如請求項6至9中任一項之方法,其中於該層壓步驟中,以20℃~100℃進行真空層壓。
TW101147680A 2011-12-16 2012-12-14 A semiconductor wafer having an anisotropic conductive film, a semiconductor wafer having an anisotropic conductive film, and a semiconductor device TWI541958B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011275962 2011-12-16
JP2011275930 2011-12-16

Publications (2)

Publication Number Publication Date
TW201332070A TW201332070A (zh) 2013-08-01
TWI541958B true TWI541958B (zh) 2016-07-11

Family

ID=48612640

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101147680A TWI541958B (zh) 2011-12-16 2012-12-14 A semiconductor wafer having an anisotropic conductive film, a semiconductor wafer having an anisotropic conductive film, and a semiconductor device

Country Status (5)

Country Link
JP (2) JPWO2013089199A1 (zh)
KR (1) KR20140100511A (zh)
CN (1) CN103988289A (zh)
TW (1) TWI541958B (zh)
WO (1) WO2013089199A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI750238B (zh) * 2016-10-06 2021-12-21 日商日東電工股份有限公司 各向異性導電性片材

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015079586A (ja) 2013-10-15 2015-04-23 デクセリアルズ株式会社 異方性導電フィルム
JP2015135878A (ja) 2014-01-16 2015-07-27 デクセリアルズ株式会社 接続体、接続体の製造方法、接続方法、異方性導電接着剤
JP2015149451A (ja) * 2014-02-07 2015-08-20 デクセリアルズ株式会社 アライメント方法、電子部品の接続方法、接続体の製造方法、接続体、異方性導電フィルム
JP2015179831A (ja) * 2014-02-27 2015-10-08 デクセリアルズ株式会社 接続体、接続体の製造方法及び検査方法
JP2016131245A (ja) * 2015-01-13 2016-07-21 デクセリアルズ株式会社 多層基板
JP6719176B2 (ja) * 2015-03-30 2020-07-08 株式会社村田製作所 アルミニウム部材の接合方法
WO2016190424A1 (ja) * 2015-05-27 2016-12-01 デクセリアルズ株式会社 異方導電性フィルム及び接続構造体
US10304803B2 (en) * 2016-05-05 2019-05-28 Invensas Corporation Nanoscale interconnect array for stacked dies
WO2017203884A1 (ja) * 2016-05-27 2017-11-30 富士フイルム株式会社 異方導電材、電子素子、半導体素子を含む構造体および電子素子の製造方法
CN107221770A (zh) * 2017-05-10 2017-09-29 武汉华星光电技术有限公司 连接器、连接器的制作方法、连接组件及面板组件
WO2019065118A1 (ja) * 2017-09-29 2019-04-04 富士フイルム株式会社 半導体デバイスの製造方法および接合部材
KR102187881B1 (ko) * 2018-07-26 2020-12-07 주식회사 에이엔케이 마이크로 led 검사용 프로브 소켓 디바이스 제조 방법
KR20210138332A (ko) * 2020-05-12 2021-11-19 안성룡 전도체 본딩 방법
CN115388786A (zh) * 2022-08-08 2022-11-25 安徽承禹半导体材料科技有限公司 一种碲锌镉晶片损伤层厚度的检测方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3417110B2 (ja) * 1994-12-30 2003-06-16 カシオ計算機株式会社 電子部品の接続方法
KR100273499B1 (ko) * 1995-05-22 2001-01-15 우찌가사끼 이사오 배선기판에전기접속된반도체칩을갖는반도체장치
JP4574631B2 (ja) * 1996-08-06 2010-11-04 日立化成工業株式会社 マルチチップ実装法
JPH10125725A (ja) * 1996-10-18 1998-05-15 Mitsubishi Electric Corp 半導体装置およびその製造方法
CN1135610C (zh) * 1998-12-02 2004-01-21 精工爱普生株式会社 各向异性导电膜和半导体芯片的安装方法以及半导体装置
JP3684886B2 (ja) * 1998-12-17 2005-08-17 セイコーエプソン株式会社 半導体チップの実装構造、液晶装置及び電子機器
KR100650284B1 (ko) * 2005-02-22 2006-11-27 제일모직주식회사 도전성능이 우수한 고분자 수지 미립자, 전도성 미립자 및이를 포함한 이방 전도성 접속재료
JP2007217503A (ja) * 2006-02-15 2007-08-30 Asahi Kasei Electronics Co Ltd 異方導電性接着フィルム
KR101063710B1 (ko) * 2006-09-26 2011-09-07 히다치 가세고교 가부시끼가이샤 이방 도전성 접착제 조성물, 이방 도전성 필름, 회로 부재의 접속 구조, 및 피복 입자의 제조 방법
JP4880533B2 (ja) * 2007-07-03 2012-02-22 ソニーケミカル&インフォメーションデバイス株式会社 異方性導電膜及びその製造方法、並びに接合体
KR100838647B1 (ko) * 2007-07-23 2008-06-16 한국과학기술원 Acf/ncf 이중층을 이용한 웨이퍼 레벨 플립칩패키지의 제조방법
JP5192194B2 (ja) * 2007-07-26 2013-05-08 デクセリアルズ株式会社 接着フィルム
JP2009147231A (ja) * 2007-12-17 2009-07-02 Hitachi Chem Co Ltd 実装方法、半導体チップ、及び半導体ウエハ

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI750238B (zh) * 2016-10-06 2021-12-21 日商日東電工股份有限公司 各向異性導電性片材

Also Published As

Publication number Publication date
JP2015159333A (ja) 2015-09-03
JPWO2013089199A1 (ja) 2015-04-27
WO2013089199A1 (ja) 2013-06-20
CN103988289A (zh) 2014-08-13
KR20140100511A (ko) 2014-08-14
TW201332070A (zh) 2013-08-01

Similar Documents

Publication Publication Date Title
TWI541958B (zh) A semiconductor wafer having an anisotropic conductive film, a semiconductor wafer having an anisotropic conductive film, and a semiconductor device
KR101115271B1 (ko) 도전 입자 배치 시트 및 이방성 도전 필름
JP4789738B2 (ja) 異方導電性フィルム
TWI649764B (zh) 異向性導電膜及其製造方法
TWI396205B (zh) A circuit connecting material, a connecting structure using the circuit member, and a connection method of the circuit member
WO2014136836A1 (ja) 接着フィルム、ダイシングシート一体型接着フィルム、バックグラインドテープ一体型接着フィルム、バックグラインドテープ兼ダイシングシート一体型接着フィルム、積層体、積層体の硬化物、および半導体装置、並び半導体装置の製造方法
TWI550640B (zh) 以含有導電微球之各向異性導電膜連接的半導體元件
TWI686999B (zh) 異向性導電膜、其製造方法及連接構造體
TW201638970A (zh) 異向性導電膜
KR102067957B1 (ko) 접속체, 접속체의 제조 방법, 검사 방법
TWI771331B (zh) 異向性導電膜及其製造方法、以及連接構造體及其製造方法
TW200816335A (en) Production method of semiconductor device and bonding film
JP6959303B2 (ja) 接続体、接続体の製造方法及び検査方法
US10023775B2 (en) Film adhesive and semiconductor device including the same
JP7330768B2 (ja) 接続体の製造方法、接続方法
TW201728012A (zh) 異向性導電膜及連接結構體
KR102700783B1 (ko) 접속체, 접속체의 제조 방법, 접속 방법
TWI391460B (zh) Adhesive film, and circuit structure of the connection structure and connection method
TW202300569A (zh) 含填料膜
JP5516016B2 (ja) 異方導電性接着フィルム及びその製造方法
JP2022118147A (ja) 異方性導電フィルム
TWI781213B (zh) 異向性導電膜、連接結構體及彼等之製造方法
JP5682720B2 (ja) 異方導電性接着フィルム及びその製造方法
JP5370694B2 (ja) 接続構造体
JP2008130588A (ja) 半導体用接着組成物付き電子デバイス基板、それを用いた電子デバイスシステムおよび電子デバイスシステムの製造方法