JP2009211088A - 電子表示装置 - Google Patents
電子表示装置 Download PDFInfo
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Abstract
【解決手段】薄膜トランジスタは、第一のゲート電極の端部と、第一のゲート電極の端部に対向する第二のゲート電極の端部とを有するゲート電極を含む。TFTはまた、第一のゲート電極の端部と重複する第一のドレイン電極の端部と、第二のゲート電極の端部と重複する第二のドレイン電極の端部とを有するドレイン電極を含む。表示装置に用いられるダイオードアレイの製造方法は、基板に隣接した導電層の成膜と、基板に隣接したドープド半導体層の成膜と、基板に隣接したアンドープド半導体層の成膜とを含む。表示画素単位により、画素電極とソース線との間の容量結合を低減する。この単位は、トランジスタと、画素電極と、ソース線とを含む。ソース線は、トランジスタに電源を供給する延長線を含む。パターン形成した導電部を、ソース線に隣接して配置する。
【選択図】なし
Description
e)1991年、353、737、およびD.ウッド(Wood)、情報表示装置(Information Display)、18(3)、24(2002年3月)を参照のこと。また、U.バッハ(Bach)他、Adv. Mater,2002年、14(11),845を参照のこと。この種類のナノクロミック薄膜については、例えば、米国特許第6,301,038号明細書および公開国際出第01/27690号パンフレット、2003年3月18日出願の米国同時継続出願第10/249,128号明細書に記載されている。また、この種類の媒体は典型的には双安定性である。
基板上に導電層を成膜し、
基板上に第一のドープド半導体層を導電層の上に成膜し、
導電層とドープド半導体層とをパターン形成して、複数の個別の導電層/第一のドープド半導体層領域を形成し、
基板上にアンドープド半導体層を複数の個別の導電層/第一のドープド半導体層領域の上に成膜し、
複数の第二のドープド半導体層領域を複数の個別の導電層/第一のドープド半導体層領域からアンドープド半導体層の反対側に形成し、
よって、複数の個別の導電層/第一のドープド半導体層領域と、アンドープド半導体層と、複数の第二のドープド半導体層領域とが、基板上に複数のダイオードを形成する。
アンドープド半導体材料から成る2つの間隔をおいた領域を基板からドープド半導体層の反対側に形成し、
導電性材料から成る2つの間隔をおいた領域を形成し、これらの領域はそれぞれ、ドープド半導体層からその対向する側の一方のアンドープド半導体材料の領域に接触している。
ソース線に印加する電圧極性を表す符号ビットを受信するよう構成された第二の入力と、
少なくとも1つのデジタル/アナログ変換器と、
ソース線電圧を出力するよう構成された第一の出力であって、その大きさおよび極性は、第一および第二の入力それぞれで受信した信号により判定し、
ソース線電圧の反対の極性の平衡線電圧を出力するように構成された第二の出力であって、平衡線電圧の大きさは、ソース線電圧の大きさに対する所定の関係を有する。
ソース線に印加する電圧極性を表す符号ビットを受信するよう構成された第二の入力と、
平衡線に印加する電圧の大きさを表すデジタル信号を受信するよう構成された第三の入力と、
第一の正の出力デジタル/アナログ変換器と、
第二の負の出力デジタル/アナログ変換器と、
ソース線電圧を出力するよう構成された第一の出力であって、その大きさおよび極性は、第一および第二の入力それぞれで受信した信号により判定し、
ソース線電圧と反対の極性の平衡線電圧を出力するように構成された第二の出力であって、平衡線電圧の大きさは、第三の入力で受信した信号により判定し、
第一および第三の入力と、第一および第二のデジタル/アナログ変換器の入力とに接続する第一の転極スイッチであって、第一の転極スイッチは、第一の入力が第一のデジタル/アナログ変換器に接続し、第三の入力が第二のデジタル/アナログ変換器に接続する第一の位置と、第三の入力が第一のデジタル/アナログ変換器に接続する第二の位置とを有し、
第一および第二のデジタル/アナログ変換器の出力と、第一および第二の出力とに接続する第二の転極スイッチであって、第二の転極スイッチは、第一のデジタル/アナログ変換器が第一の出力に接続し、第二のデジタル/アナログ変換器が第二の出力に接続する第一の位置と、第一のデジタル/アナログ変換器が第二の出力に接続し、第二のデジタル/アナログ変換器が第一の出力に接続する第二の位置とを有する。
(項目1)
ソース電極(208;308;408;508)と、ソース電極(208;308;408;508)からチャネル分間隔を置いて配置するドレイン電極(212;312;412;512)と、チャネルに延設された半導体層(224A,224B;324;424)と、チャネルに隣接して配置されるゲート電極(206A,206A,206;306;406;506)とを備え、ゲート電極(206A,206A,206;306;406;506)に印加する電圧がチャネルに延設された半導体層(224A,224B;324;424)の導電性を変えるトランジスタ(200;300;400;500)であって、ゲート電極(206A,206A,206;306;406;506)は、第一のゲート電極の端部と、第一のゲート電極の端部から間隔をおいて配置する第二のゲート電極の端部とを有し、ドレイン電極(212;312;412;512)は、第一のゲート電極の端部と重複して第一の重複する領域(226A)を形成する第一のドレイン電極の端部を有し、ドレイン電極はまた、第二のゲート電極の端部と重複して第二の重複する領域(226B)を形成する第二のドレイン電極の端部を有し、第一の重複する領域(226A)が増加する方向でドレイン電極(212;312;412;512)に対しゲート電極(206A,206A,206;306;406;506)が移動することにより、第二の重複する領域(226B)を減少させ、またはこの逆の場合であることを特徴とするトランジスタ(200;300;400;500)。
(項目2)
薄膜トランジスタであって、ソース電極(208;308;408;508)と、ドレイン電極(212;312;412;512)と、ゲート電極(206A,206A,206;306,406;506)と半導体層(224A,224B;324;424)とが、基板(220;320;420)上に成膜した薄膜層である項目1に記載のトランジスタ(200;300;400;500)。
(項目3)
ゲート電極は、ベース部(204’)と、ベース部(204’)から離れて1つの方向に延設し、実質的に互いに平行である第一および第二の突起部(206A,206B)を備え、第一および第二のゲート電極の端部は、それぞれ他の突起部から離れている第一および第二の突起部(206A,206B)の端部から構成されていることを特徴とする前出の項目のいずれかに記載のトランジスタ(200)。
(項目4)
ソース電極(208)を第一の突起部と第二の突起部(206A,206B)との間に延設し、これらの突起部それぞれの内向きの端部と重複させる、項目3に記載のトランジスタ(200)。
(項目5)
ゲート電極(306;406;506)は中央開口部(307;407)を有する多角形で、ドレイン電極(312;412;512)の中央部分は少なくとも一部の中央開口部(307;407)と重複し、第一のおよび第二の重複する領域はドレイン電極(312;412;512)と中央開口部(307;407)に隣接するゲート電極(306;406;506)の部分との間の重複により形成されることを特徴とする前出の項目のいずれか1つに記載のトランジスタ(300;400;500)。
(項目6)
中央開口部(307;407)は開口部の対向する辺にまっすぐな2つの端部を有し、これらのまっすぐな端部が第一および第二のゲート電極の端部を形成することを特徴とする項目5に記載のトランジスタ(300;400;500)。
(項目7)
ドレイン電極(506)と部分的に重複するキャパシタ電極(526)と、キャパシタ電極(526)とドレイン電極(506)との間に配置され、キャパシタ電極(526)とドレイン電極(506)とが共にキャパシタを形成する誘電体層とを特徴とする前出の項目のいずれか1つに記載のトランジスタ(500)。
(項目8)
ゲート電極(506)は実質的に中央開口部を有する多角形で、ドレイン電極の中央部分は少なくとも一部の中央開口部と重複し、第一のおよび第二の重複する領域は、ドレイン電極(506)と中央開口部に隣接するゲート電極の部分との間の重複により形成され、キャパシタ電極(526)は中央開口部内に配置され、ゲート電極(506)内のギャップ(530)を通過する導体(528’)によりキャパシタ電極線(528)に接続することを特徴とする項目7に記載のトランジスタ(500)。
(項目9)
画素電極がドレイン電極(212;312;412;512)に接続することを特徴とする前出の項目のいずれか1つに記載のトランジスタ(200;300;400;500)。
(項目10)
ドレイン電極(212;312;412;512)と画素電極との間に配置された誘電体層と、誘電体層を介してドレイン電極(212;312;412;512)から画素電極に延設する導電性バイア(214;314;414;514)を特徴とする項目9に記載のトランジスタ(200;300;400;500)。
(項目11)
画素電極はゲート(206A,206B;306;406;506)電極とドレイン(212;312;412;512)電極との両方に重なることを特徴とする項目10に記載のトランジスタ(200;300;400;500)。
(項目12)
電気光学表示装置用バックプレーンであって、バックプレーンは基板(220;320;420)と、少なくとも1つの前出の項目のいずれか1つに記載のトランジスタとを備える。
(項目13)
電気光学表示装置であって、項目12に記載のバックプレーンと、バックプレーンに配置され、少なくとも1つのトランジスタを覆う電気光学媒体層と、基板から電気光学媒体層の反対側に配置され、少なくとも1つのトランジスタに配置される前面電極を備える。
(項目14)
電気光学媒体は、回転する2色部材またはエレクトロクロミック媒体であることを特徴とする項目13に記載の電気光学表示装置。
(項目15)
電気光学媒体は、電気泳動媒体であること項目13に記載の電気光学表示装置。
(項目16)
電気光学媒体は、封止電気泳動媒体であることを特徴とする項目15に記載の電気光学表示装置。
(項目17)
基板(602)上に複数のダイオード(600)を形成するプロセスであって、
基板上(602)に導電層(604)を成膜し、
基板(602)上に第一のドープド半導体層(608)を導電層(604)の上に成膜し、
導電層(604)とドープド半導体層(608)とをパターン形成して、複数の個別の導電層/第一のドープド半導体層領域を形成するプロセスは以下を特徴とする。
基板(602)上にアンドープド半導体層(612)を複数の個別の導電層/第一のドープド半導体層領域の上に成膜し、
複数の第二のドープド半導体層領域(610)を複数の個別の導電層/第一のドープド半導体層領域からアンドープド半導体層(612)の反対側に形成し、
よって、複数の個別の導電層/第一のドープド半導体層領域と、アンドープド半導体層(612)と、複数の第二のドープド半導体層領域(610)とが、基板(602)上に複数のダイオード(600)を形成する。
(項目18)
基板(702)上にダイオード(700)を形成するプロセスであって、該プロセスは以下を特徴とする。
基板(702)上にドープド半導体層(708)を成膜し、
アンドープド半導体材料から成る2つの間隔をおいた領域(706A,706B)を基板(702)からドープド半導体層(708)の反対側に形成し、
導電性材料から成る2つの間隔をおいた領域(704A,704B)を形成し、これらの領域(704A,704B)はそれぞれ、ドープド半導体層(708)からその対向する側の一方のアンドープド半導体材料の領域(706A,706B)に接触している。
(項目19)
ソース線(906)と、トランジスタ(908,918,912)と、トランジスタ(908,918,912)を介してソース線(906)に接続する画素電極(902)とを備え、画素電極(902)は、ソース線(906)の一部に延設して重複する領域を形成する電気光学表示装置用バックプレーン(1000)であって、導電部(1032)はソース線(906)と画素電極(902)との間に配置され、導電部(1032)がソース線/画素電極の静電容量を低減することを特徴とするバックプレーン(1000)。
(項目20)
電気光学表示装置用バックプレーン(1100;1300;1500)であって、バックプレーン(1100;1300;1500)は、ソース線(906;1406)と、トランジスタ(908,918,912;1408,1418)と、トランジスタ(908,918,912;1408,1418)を介してソース線(906;1406)に接続する画素電極(902;1402)とを備え、ソース線(906;1406)の隣接部にあって、ソース線/画素電極の静電容量を供給する画素電極(902,1402)と、少なくとも一部が画素電極(902;1402)と隣接して配置され、平衡線/画素電極の静電容量を供給する平衡線(1134;1334;1534)と、ソース線(906;1406)に印加するものと逆の極性の電圧を平衡線(1134;1334;1534)に印加する電圧供給手段とを特徴とするバックプレーン(1100;1300;1500)。
(項目21)
以下を特徴とする、ソース線(S1)および平衡線を有する電気光学表示装置を駆動するドライバ(1800;1900)。
ソース線(S1)に印加する電圧の大きさを表すデジタル信号(1706,1806)を受信するよう構成された第一の入力と、
ソース線(S1)に印加する電圧極性を表す符号ビット(1708;1808)を受信するよう構成された第二の入力と、
少なくとも1つのデジタル/アナログ変換器(1702,1704;1802,1804)と、
ソース線電圧を出力するよう構成された第一の出力であって、その大きさおよび極性は、第一および第二の入力それぞれで受信した信号により判定し、
ソース線電圧の反対の極性の平衡線電圧を出力するように構成された第二の出力であって、平衡線電圧の大きさは、ソース線電圧の大きさに対する所定の関係を有する。
(項目22)
以下を特徴とする、ソース線(S1)および平衡線(B1)を有する電気光学表示装置を駆動するドライバ(2000)。
ソース線(S1)に印加する電圧の大きさを表すデジタル信号(1806)を受信するよう構成された第一の入力と、
ソース線(S1)に印加する電圧極性を表す符号ビット(1808)を受信するよう構成された第二の入力と、
平衡線(B1)に印加する電圧の大きさを表すデジタル信号(2016)を受信するよう構成された第三の入力と、
第一の正の出力デジタル/アナログ変換器(1804)と、
第二の負の出力デジタル/アナログ変換器(1802)と、
ソース線電圧を出力するよう構成された第一の出力であって、その大きさおよび極性は、第一および第二の入力それぞれで受信した信号により判定し、
ソース線電圧と反対の極性の平衡線電圧を出力するように構成された第二の出力であって、平衡線電圧の大きさは、第三の入力で受信した信号により判定し、
第一および第三の入力と、第一および第二のデジタル/アナログ変換器(1804,1802)の入力とに接続する第一の転極スイッチ(2018)であって、第一の転極スイッチ(2018)は、第一の入力が第一のデジタル/アナログ変換器(1804)に接続し、第三の入力が第二のデジタル/アナログ変換器(1802)に接続する第一の位置と、第三の入力が第一のデジタル/アナログ変換器(1804)に接続する第二の位置とを有し、
第一および第二のデジタル/アナログ変換器(1804,1802)の出力と、第一および第二の出力とに接続する第二の転極スイッチ(1810)であって、第二の転極スイッチ(1810)は、第一のデジタル/アナログ変換器(1804)が第一の出力に接続し、第二のデジタル/アナログ変換器(1802)が第二の出力に接続する第一の位置と、第一のデジタル/アナログ変換器(1804)が第二の出力に接続し、第二のデジタル/アナログ変換器(1802)が第一の出力に接続する第二の位置とを有する。
すでに述べたように、本発明により、レジストレーション許容型トランジスタを提供する。このトランジスタでは、ゲート電極は2つの間隔をおいた端部を有し、ドレイン電極は、ゲート電極の2つの間隔をおいた端部と重複して2つの別々の重複する領域を形成する第一および第二の電極端部を有し、一方の重複する領域が増加する方向でドレイン電極に対しゲート電極が移動すること(例えば、TFTアレイの製造中のレジストレーション異常による)により、他方の重複する領域を減少させる。従って、本発明のレジストレーション許容型トランジスタにより、TFTのゲート導電層とソースドレイン導電層との間の小さなレジストレーション異常に依存しないゲート画素の静電容量、あるいはわずかに反応するゲート画素の静電容量を提供できる。従来技術のレジストレーション許容型の設計とは異なり、このレジストレーション許容範囲は、ゲート電極とドレイン電極とが完全に重複することなく達成できる。好適な実施の形態では、電極の端部の一部が重複するだけである。従って、比較的小さなゲート画素の静電容量を達成できる。
ョン206Aと206Bとの間にあって、事実上ゲート電極のベース部分を形成している。
、矩形の中央開口部307を有する中空矩形のゲート電極を形成する。
306と、ドレイン電極312とを含む。ソース電極308およびドレイン電極312は共に、第二のパターン形成した金属層に形成されている。しかしながら、図3Bおよび3Cからわかるように、ソース電極308およびドレイン電極312の形は、実質的に図1B,1C,2Bおよび2Cに示す対応する電極の形から変形している。ソース電極308は実質的にU字型で、ソース線310の隣接する断面310'と共に、ゲート電極304',306の外端部とわずかに重複して取り囲む中空矩形である。ドレイン電極312は矩形で、その中央部分がゲート電極の中央開口部307と重なるが、その周辺部分は中央開口部307を形成するゲート電極の内端部を外側に向かって延長する。従って、ゲート電極のこれらの内端部は、TFT300のゲート電極の端部を構成し、ドレイン電極312とゲート電極の内部との間の重複する領域は、TFTの重複する領域を構成する。明らかなように、前述のTFT200とは異なり、TFT300、4つのゲート電極の端部(矩形の開口部307の4つの辺に沿った端部)と、同様に4つの重複する領域とを有すると考えられる。
層322は第一の金属層302と重なり、ソース電極308と、ゲート誘電体層322の上に形成されたドレイン電極312とを含む第二の金属層を有する。ソース電極308とドレイン電極312との間の「環状」ギャップは、TFT300のチャネルを形成するドープドシリコンから成る領域324(図3Bから省略)で埋められている。TFT300は前述のTFT100および200と同じ埋込み型で、バイア314(図3B)と、TFT300と重なる画素電極を有しているが、バイア314および対応する画素電極は共に、説明を簡単にするため図3Cから省略している。同等のトップゲート構造はもちろん可能で、TFT300は、例えば、ドレイン電極と同じ面にある画素電極に対しある種のブリッジ構造でドレイン電極312接続することにより、非埋込み型にも変更できる。
形成している。電極の内周および外周の正確な形は、もちろん実施の形態と変えることができる。例えば、円形、正方形、楕円形、多角形等の形にできる。
406と、ドレイン電極412とを含む。ソース電極408およびドレイン電極412は共に、第二のパターン形成した金属層に形成される。図4Bおよび4Cから明らかなように、ソース電極408およびドレイン電極412の形は共に、図3Bおよび3Cに示す対応する電極の形から変形したものである。ソース電極408は、ソース線410の隣接する断面410と共に、ゲート電極404',406の外端部とわずかに重複して取り囲む
中空変形多角形の形をしている。ドレイン電極412はまた、変形多角形をしており、その中央部分がゲート電極の中央開口部407と重なるが、その周辺部分は中央開口部407を形成するゲート電極の内端部を外側に向かって延長している。従って、ゲート電極のこれらの内端部は、TFT400のゲート電極の端部を構成し、ドレイン電極412とゲート電極の内部との間の重複する領域は、TFTの重複する領域を構成している。TFT400は、複数のゲート電極の端部(多角形の開口部407の辺に沿った端部)と、同様に、複数の重複する領域とを有すると考えられる。
層422は、第二の金属層と共に第一の金属層402に重なり、ソース電極408と、ゲート誘電体層422の上に形成されたドレイン電極412とを含む。ソース電極408とドレイン電極412との間の「環状」ギャップは、TFT400のチャネルを形成するドープドシリコンの領域424(図4Bから省略)で埋められている。TFT400は前述のTFT100,200および300と同じ埋込み型で、バイア414(図4B)と、TFT400に重なる画素電極とを有するが、バイア414および対応する画素電極は、説明を簡単にするため図4Cから省略している。同等のトップゲート構造はもちろん可能で、前述のTFT300と同じ非埋込み型にも当然変更することができる。
いる。非線形表示装置を駆動するTFTにキャパシタに含める根拠は、前述の同時継続出願第09/565,413号明細書、出願公開第2002/0106847号明細書および2002/0060321号明細書に記載されている。キャパシタ電極線528は、典型的には接地する。
図6A−6Cおよび7A−7Bは、本発明のプロセスにより製造されたダイオードアレイを示している。これらのダイオードアレイは、低コストで高いスループットの製造プロセスにより製造して、領域が広いダイオードマトリックスベースの表示装置を構成することができる。いくつかの実施の形態では、ダイオードアレイは、わずかに1つまたは2つのリソグラフィ工程を用いて製造することができる。このプロセスは、ガラス、ポリイミド、金属ホイルおよび他の基板材料と互換性がある。バッチまたはロールツーロールプロセスを用いることができる。このアレイには、各種の表示媒体を用いることができる。
(A:スクリーンソース線バックプレーン)
すでに述べたように、別の側面では、本発明により、ソース線結合を低減したバックプレーンの設計を提供する。すなわち、画素電極に対するソース線の結合を低減する。これらのバックプレーンには主に2つの種類があり、すなわち、スクリーンソース線バックプレーンおよび平衡線バックプレーンで、これらの2つの種類について、以下に別々に説明するが、所望の場合には、1つのバックプレーンに、本発明のこれらの側面を共に利用することもできる。まず比較のために、図9Aおよび9Bを参照して、反射型電気光学表示装置に用いられる従来技術のバックプレーンについて説明する。
すでに示したように、本発明の一側面は、ソース線/画素電極結合による電圧シフトを低減する平衡線を含むバックプレーンに関する。反射型表示装置に用いられるのに好適な平衡線バックプレーンについて、図11−13を参照して説明し、透過型表示装置に用いられるのに好適な平衡線バックプレーンについて、図15を参照して説明する。
本発明の平衡線バックプレーンに用いられる平衡線は実際には、ソース線が行うようにドライバにより駆動する必要がある。ここに記載の平衡線を備えることにより、表示装置のアクティブ領域に供給するソースドライバ出力の数を2倍にできる。ソースドライバ出力の数を倍にすることは、ソースドライバのコストを大幅に増加することを意味する。
Claims (1)
- 本願明細書に記載のバックプレーン。
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WO2003092077A3 (en) | 2004-03-25 |
WO2003092077A2 (en) | 2003-11-06 |
JP2005524110A (ja) | 2005-08-11 |
EP1497867A2 (en) | 2005-01-19 |
US20030222315A1 (en) | 2003-12-04 |
KR100896167B1 (ko) | 2009-05-11 |
KR100867286B1 (ko) | 2008-11-06 |
US20070035532A1 (en) | 2007-02-15 |
US7605799B2 (en) | 2009-10-20 |
AU2003232018A8 (en) | 2003-11-10 |
AU2003232018A1 (en) | 2003-11-10 |
US7116318B2 (en) | 2006-10-03 |
KR20080080418A (ko) | 2008-09-03 |
KR20040104617A (ko) | 2004-12-10 |
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