JP2009038354A - 発光装置 - Google Patents
発光装置 Download PDFInfo
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- JP2009038354A JP2009038354A JP2008168472A JP2008168472A JP2009038354A JP 2009038354 A JP2009038354 A JP 2009038354A JP 2008168472 A JP2008168472 A JP 2008168472A JP 2008168472 A JP2008168472 A JP 2008168472A JP 2009038354 A JP2009038354 A JP 2009038354A
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Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- H—ELECTRICITY
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Abstract
【解決手段】逆スタガ型の薄膜トランジスタを有する発光装置において、逆スタガの薄膜トランジスタは、ゲート電極上にゲート絶縁膜が形成され、ゲート絶縁膜上にチャネル形成領域として機能する微結晶半導体膜が形成され、微結晶半導体膜上にバッファ層が形成され、バッファ層上に一対のソース領域及びドレイン領域が形成され、ソース領域及びドレイン領域の一部を露出するようにソース領域及びドレイン領域に接する一対のソース電極及びドレイン電極が形成される。
【選択図】図2
Description
本実施の形態では、発光装置に用いられる薄膜トランジスタの作製工程について、図1乃至図12を用いて説明する。図1乃至図4、図6乃至図8は、薄膜トランジスタの作製工程を示す断面図であり、図5、及び図9は、一画素における薄膜トランジスタ及び画素電極の接続領域の上面図である。
次に、発光装置の作製工程について、図2、及び図15を用いて説明する。発光装置としては、ここではエレクトロルミネッセンスを利用する発光素子を用いて示す。エレクトロルミネッセンスを利用する発光素子は、発光材料が有機化合物であるか、無機化合物であるかによって区別され、一般的に、前者は有機EL素子、後者は無機EL素子と呼ばれている。また、ここでは、薄膜トランジスタの作製工程として図1及び図2を用いるが、適宜図4、図6乃至図8を用いることができる。
次に、本発明の発光装置の一形態である発光パネルの構成について、以下に示す。
本発明により得られる発光装置等によって、アクティブマトリクス型ELモジュールに用いることができる。即ち、それらを表示部に組み込んだ電子機器全てに本発明を実施できる。
Claims (8)
- ゲート電極と、
前記ゲート電極上に形成されるゲート絶縁膜と、
前記ゲート絶縁膜上に形成される微結晶半導体膜と、
前記微結晶半導体膜上に形成され、且つ凹部を有するバッファ層と、
前記バッファ層上に形成されるソース領域及びドレイン領域と、
前記ソース領域及びドレイン領域に接するソース電極及びドレイン電極とを有し、
前記ソース領域及びドレイン領域の一部は、前記ソース電極及びドレイン電極に接し、
前記ソース領域及びドレイン領域の他部は、前記ソース電極及びドレイン電極に接せず、前記バッファ層は、前記ソース電極及びドレイン電極の外側で露出しており、
前記ゲート電極に重なる前記ソース領域及びドレイン領域の端部と、前記バッファ層の凹部側面は一致している薄膜トランジスタを有することを特徴とする発光装置。 - ゲート電極と、
前記ゲート電極上に形成されるゲート絶縁膜と、
前記ゲート絶縁膜上に形成される微結晶半導体膜と、
前記微結晶半導体膜上に形成され、且つ凹部を有するバッファ層と、
前記バッファ層上に形成されるソース領域及びドレイン領域と、
前記ソース領域及びドレイン領域に接するソース電極及びドレイン電極とを有し、
前記ソース電極及びドレイン電極の外側において、前記ソース領域及びドレイン領域の一部、並びに前記バッファ層の一部が露出しており、
前記ゲート電極に重なる前記ソース領域及びドレイン領域の端部と、前記バッファ層の凹部側面は一致している薄膜トランジスタを有することを特徴とする発光装置。 - ゲート電極と、
前記ゲート電極上に形成されるゲート絶縁膜と、
前記ゲート絶縁膜上に形成される微結晶半導体膜と、
前記微結晶半導体膜上に形成され、且つ凹部を有するバッファ層と、
前記バッファ層上に形成されるソース領域及びドレイン領域と、
前記ソース領域及びドレイン領域に接するソース電極及びドレイン電極と、
前記ソース電極及びドレイン電極、前記ソース領域及びドレイン領域の一部、並びに前記バッファ層の一部に接する絶縁膜と、
前記絶縁膜上に形成され、前記絶縁膜に形成されるコンタクトホールにおいて、前記ソース電極またはドレイン電極に接続する画素電極とを有し、
前記ソース領域及びドレイン領域の一部は、前記ソース電極及びドレイン電極に接し、
前記ソース領域及びドレイン領域の他部は、前記ソース電極及びドレイン電極に接せず、前記バッファ層は、前記ソース電極及びドレイン電極の外側で露出しており、
前記ゲート電極上に形成される前記ソース領域及びドレイン領域の端部と、前記バッファ層の凹部側面は一致している薄膜トランジスタを有することを特徴とする発光装置。 - ゲート電極と、
前記ゲート電極上に形成されるゲート絶縁膜と、
前記ゲート絶縁膜上に形成される微結晶半導体膜と、
前記微結晶半導体膜上に形成され、且つ凹部を有するバッファ層と、
前記バッファ層上に形成されるソース領域及びドレイン領域と、
前記ソース領域及びドレイン領域に接するソース電極及びドレイン電極と、
前記ソース電極及びドレイン電極、前記ソース領域及びドレイン領域の一部、並びに前記バッファ層の一部に接する絶縁膜と、
前記絶縁膜上に形成され、前記絶縁膜に形成されるコンタクトホールにおいて、前記ソース電極またはドレイン電極に接続する画素電極とを有し、
前記ソース領域及びドレイン領域の一部は、前記ソース電極及びドレイン電極に接し、
前記ソース領域及びドレイン領域の他部は、前記ソース電極及びドレイン電極に接せず、前記バッファ層は、前記ソース電極及びドレイン電極の外側で露出しており、
前記ゲート電極上に形成される前記ソース領域及びドレイン領域の端部と、前記バッファ層の凹部側面は一致している薄膜トランジスタを有することを特徴とする発光装置。 - 請求項1乃至4のいずれか一項において、前記バッファ層は、非晶質半導体膜で形成されることを特徴とする発光装置。
- 請求項1乃至4のいずれか一項において、前記バッファ層は、窒素を含む非晶質半導体膜で形成されることを特徴とする発光装置。
- 請求項1乃至4のいずれか一項において、前記バッファ層は、水素を含む非晶質半導体膜で形成されることを特徴とする発光装置。
- 請求項1乃至4のいずれか一項において、前記バッファ層は、フッ素、塩素、臭素、またはヨウ素を含む非晶質半導体膜で形成されることを特徴とする発光装置。
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JP7290769B2 (ja) | 2023-06-13 |
JP6640823B2 (ja) | 2020-02-05 |
CN101339960A (zh) | 2009-01-07 |
JP2020061573A (ja) | 2020-04-16 |
JP2018046300A (ja) | 2018-03-22 |
TW200915578A (en) | 2009-04-01 |
KR20090004555A (ko) | 2009-01-12 |
JP2023118704A (ja) | 2023-08-25 |
CN101339960B (zh) | 2012-07-04 |
JP2022089874A (ja) | 2022-06-16 |
KR101465188B1 (ko) | 2014-11-25 |
JP2015073106A (ja) | 2015-04-16 |
JP5953357B2 (ja) | 2016-07-20 |
US20090008645A1 (en) | 2009-01-08 |
TWI493720B (zh) | 2015-07-21 |
US8334537B2 (en) | 2012-12-18 |
JP2016192561A (ja) | 2016-11-10 |
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