JP5618468B2 - 表示装置の作製方法 - Google Patents
表示装置の作製方法 Download PDFInfo
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- JP5618468B2 JP5618468B2 JP2008185728A JP2008185728A JP5618468B2 JP 5618468 B2 JP5618468 B2 JP 5618468B2 JP 2008185728 A JP2008185728 A JP 2008185728A JP 2008185728 A JP2008185728 A JP 2008185728A JP 5618468 B2 JP5618468 B2 JP 5618468B2
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- semiconductor film
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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Description
本実施の形態では、表示装置に用いられる薄膜トランジスタの作製工程について、図1乃至図19を用いて説明する。図1乃至図3、図5乃至図7、図9乃至図11、図13乃至図15、図17乃至図19は、薄膜トランジスタの作製工程を示す断面図であり、図4、図8、図12、及び図16は、一画素における薄膜トランジスタ及び画素電極の接続領域の上面図である。
本実施の形態では、表示装置の一形態として、実施の形態1で示す薄膜トランジスタを有する液晶表示装置について、以下に示す。
次に、表示装置の一形態である発光装置について、図9乃至図11、及び図37を用いて説明する。発光装置としては、ここではエレクトロルミネッセンスを利用する発光素子を用いて示す。エレクトロルミネッセンスを利用する発光素子は、発光材料が有機化合物であるか、無機化合物であるかによって区別され、一般的に、前者は有機EL素子、後者は無機EL素子と呼ばれている。また、ここでは、薄膜トランジスタの作製工程として図9乃至図11を用いるが、適宜図1乃至図8、図12乃至図19を用いることができる。
次に、本発明の表示装置の一形態である表示パネルの構成について、以下に示す。
次に、本発明の表示装置の一形態に相当する液晶表示パネルの外観及び断面について、図46を用いて説明する。図46(A)は、第1の基板4001上に形成されたLPSAS膜を有する薄膜トランジスタ4010及び液晶素子4013を、第2の基板4006との間にシール材4005によって封止した、パネルの上面図であり、図46(B)は、図46(A)のA−A’における断面図相当する。
次に、本発明の表示装置の一形態に相当する発光表示パネルの外観及び断面について、図47を用いて説明する。図47(A)は、第1の基板上に形成されたLPSAS膜を用いた薄膜トランジスタ及び発光素子を、第2の基板との間にシール材によって封止した、パネルの上面図であり、図47(B)は、図47(A)のA−A’における断面図に相当する。
本発明により得られる表示装置等によって、アクティブマトリクス型表示装置モジュールに用いることができる。即ち、それらを表示部に組み込んだ電子機器全てに本発明を実施できる。
Claims (11)
- 基板上にゲート電極を形成し、
前記基板及び前記ゲート電極上にゲート絶縁膜を形成し、
前記ゲート絶縁膜上に微結晶半導体膜を形成し、
前記微結晶半導体膜にレーザビームを照射した後、前記レーザビームが照射された微結晶半導体膜上に第1のバッファ層を形成し、
前記第1のバッファ層上に、一導電型を付与する不純物元素が添加された第1の半導体膜を形成し、
前記一導電型を付与する不純物元素が添加された第1の半導体膜上に、第1のレジストマスクを形成し、
前記レーザビームが照射された微結晶半導体膜、前記第1のバッファ層、及び前記一導電型を付与する不純物元素が添加された第1の半導体膜を、前記第1のレジストマスクを用いて選択的にエッチングして、チャネル形成領域として機能する微結晶半導体膜、第2のバッファ層、及び一導電型を付与する不純物元素が添加された第2の半導体膜を形成し、
前記第1のレジストマスクを除去し、
前記一導電型を付与する不純物元素が添加された第2の半導体膜上に、導電膜を形成し、
前記導電膜上に第2のレジストマスクを形成し、
前記導電膜を、前記第2のレジストマスクを用いて選択的にエッチングして、前記一導電型を付与する不純物元素が添加された第2の半導体膜上にソース電極及びドレイン電極を形成し、
前記一導電型を付与する不純物元素が添加された第2の半導体膜を、前記第2のレジストマスクを用いて選択的にエッチングしてソース領域及びドレイン領域を形成し、
前記バッファ層を、前記第2のレジストマスクを用いて選択的にエッチングして前記バッファ層に凹部を形成し、
前記ソース電極または前記ドレイン電極に接する画素電極を形成し、
前記バッファ層の凹部の深さは、当該バッファ層の一番膜厚の厚い領域の1/2〜1/3であることを特徴とする表示装置の作製方法。 - 基板上にゲート電極を形成し、
前記基板及び前記ゲート電極上にゲート絶縁膜を形成し、
前記ゲート絶縁膜上に微結晶半導体膜を形成し、
前記微結晶半導体膜にレーザビームを照射した後、前記レーザビームが照射された微結晶半導体膜上にバッファ層を形成し、
前記バッファ層上に一導電型を付与する不純物元素が添加された半導体膜を形成し、
前記一導電型を付与する不純物元素が添加された半導体膜上に導電膜を形成し、
前記導電膜上に多階調マスクを用いたフォトリソグラフィ工程により第1のレジストマスクを形成し、
前記第1のレジストマスクを用いて前記導電膜、前記バッファ層、前記一導電型を付与する不純物元素が添加された半導体膜、及びレーザビームが照射された前記微結晶半導体膜を選択的にエッチングし、
前記第1のレジストマスクをアッシングして一対の第2のレジストマスクを形成し、
前記第2のレジストマスクを用いて前記エッチングされた導電膜をエッチングしてソース電極及びドレイン電極を形成し、
前記第2のレジストマスクを用いて前記エッチングされた一導電型を付与する不純物元素が添加された半導体膜をエッチングしてソース領域及びドレイン領域を形成し、
前記第2のレジストマスクを用いて前記エッチングされたバッファ層をエッチングして当該バッファ層に凹部を形成し、
前記ソース電極または前記ドレイン電極に接する画素電極を形成し、
前記バッファ層の凹部の深さは、当該バッファ層の一番膜厚の厚い領域の1/2〜1/3であることを特徴とする表示装置の作製方法。 - 請求項1または2において、
前記ソース電極及び前記ドレイン電極上に層間絶縁膜を形成し、
前記層間絶縁膜の一部を除去して前記ソース電極または前記ドレイン電極の一部を露出するコンタクトホールを形成し、
前記層間絶縁膜上に前記ソース電極または前記ドレイン電極に接続する前記画素電極を形成することを特徴とする表示装置の作製方法。 - 請求項1または2において、
前記ソース電極及び前記ドレイン電極上に層間絶縁膜を形成し、
前記層間絶縁膜の一部を除去して前記ソース電極及び前記ドレイン電極の一部を露出するコンタクトホールを形成し、
前記層間絶縁膜上に前記ソース電極または前記ドレイン電極の一方に接続する配線を形成し、
前記層間絶縁膜上に前記ソース電極または前記ドレイン電極の他方に接続する前記画素電極を形成することを特徴とする表示装置の作製方法。 - 請求項1乃至4のいずれか一項において、前記微結晶半導体膜は、結晶粒径が0.5nm以上50nm以下の半導体結晶で形成されることを特徴とする表示装置の作製方法。
- 請求項1乃至5のいずれか一項において、前記バッファ層は、非晶質半導体膜で形成されることを特徴とする表示装置の作製方法。
- 請求項6において、前記バッファ層は、窒素を含む非晶質半導体膜で形成されることを特徴とする表示装置の作製方法。
- 請求項6において、前記バッファ層は、水素を含む非晶質半導体膜で形成されることを特徴とする表示装置の作製方法。
- 請求項6において、前記バッファ層は、フッ素、または塩素を含む非晶質半導体膜で形成されることを特徴とする表示装置の作製方法。
- 請求項1乃至9のいずれか一項において、前記表示装置は液晶表示装置であることを特徴とする表示装置の作製方法。
- 請求項1乃至9のいずれか一項において、前記表示装置は発光装置であることを特徴とする表示装置の作製方法。
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CN101350331B (zh) | 2012-04-25 |
JP2009049388A (ja) | 2009-03-05 |
US8093112B2 (en) | 2012-01-10 |
US20090023236A1 (en) | 2009-01-22 |
CN101350331A (zh) | 2009-01-21 |
TW200919590A (en) | 2009-05-01 |
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