FR2828328B1 - Memoire semi-conductrice comprenant un circuit de compensation de cellule memoire defectueuse - Google Patents

Memoire semi-conductrice comprenant un circuit de compensation de cellule memoire defectueuse

Info

Publication number
FR2828328B1
FR2828328B1 FR0209943A FR0209943A FR2828328B1 FR 2828328 B1 FR2828328 B1 FR 2828328B1 FR 0209943 A FR0209943 A FR 0209943A FR 0209943 A FR0209943 A FR 0209943A FR 2828328 B1 FR2828328 B1 FR 2828328B1
Authority
FR
France
Prior art keywords
compensation circuit
cell compensation
memory cell
semiconductor memory
defective
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0209943A
Other languages
English (en)
Other versions
FR2828328A1 (fr
Inventor
Jun Ichi Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of FR2828328A1 publication Critical patent/FR2828328A1/fr
Application granted granted Critical
Publication of FR2828328B1 publication Critical patent/FR2828328B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/848—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by adjacent switching
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
FR0209943A 2001-08-03 2002-08-05 Memoire semi-conductrice comprenant un circuit de compensation de cellule memoire defectueuse Expired - Fee Related FR2828328B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001236638A JP5119563B2 (ja) 2001-08-03 2001-08-03 不良メモリセル救済回路を有する半導体記憶装置

Publications (2)

Publication Number Publication Date
FR2828328A1 FR2828328A1 (fr) 2003-02-07
FR2828328B1 true FR2828328B1 (fr) 2008-03-28

Family

ID=19067865

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0209943A Expired - Fee Related FR2828328B1 (fr) 2001-08-03 2002-08-05 Memoire semi-conductrice comprenant un circuit de compensation de cellule memoire defectueuse

Country Status (3)

Country Link
US (3) US6819604B2 (fr)
JP (1) JP5119563B2 (fr)
FR (1) FR2828328B1 (fr)

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US7286396B2 (en) * 2005-10-12 2007-10-23 Macronix International Co., Ltd. Bit line selection transistor layout structure
US7719872B2 (en) 2005-12-28 2010-05-18 Semiconductor Energy Laboratory Co., Ltd. Write-once nonvolatile memory with redundancy capability
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JP2008181634A (ja) 2006-12-26 2008-08-07 Semiconductor Energy Lab Co Ltd 半導体装置
TWI375959B (en) * 2007-11-06 2012-11-01 Nat Univ Tsing Hua Method for repairing memory and system thereof
TWI543177B (zh) 2010-08-19 2016-07-21 半導體能源研究所股份有限公司 半導體裝置及其檢驗方法與其驅動方法
US9208848B2 (en) * 2014-03-12 2015-12-08 Kabushiki Kaisha Toshiba Semiconductor storage device
US9715943B2 (en) * 2015-08-12 2017-07-25 Texas Instruments Incorporated Semiconductor memory cell multi-write avoidance encoding apparatus, systems and methods
US9601193B1 (en) * 2015-09-14 2017-03-21 Intel Corporation Cross point memory control
US9779796B1 (en) * 2016-09-07 2017-10-03 Micron Technology, Inc. Redundancy array column decoder for memory
JP2021044041A (ja) * 2019-09-12 2021-03-18 キオクシア株式会社 半導体記憶装置

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JP4748828B2 (ja) * 1999-06-22 2011-08-17 ルネサスエレクトロニクス株式会社 半導体記憶装置
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Also Published As

Publication number Publication date
US20050157572A1 (en) 2005-07-21
JP5119563B2 (ja) 2013-01-16
US6819604B2 (en) 2004-11-16
JP2003051199A (ja) 2003-02-21
US20040165456A1 (en) 2004-08-26
US6879529B2 (en) 2005-04-12
FR2828328A1 (fr) 2003-02-07
US20030026142A1 (en) 2003-02-06

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Effective date: 20160429