DE60336614D1 - Redundanz -Schaltung und -Verfahren für Halbleiterspeicher - Google Patents

Redundanz -Schaltung und -Verfahren für Halbleiterspeicher

Info

Publication number
DE60336614D1
DE60336614D1 DE60336614T DE60336614T DE60336614D1 DE 60336614 D1 DE60336614 D1 DE 60336614D1 DE 60336614 T DE60336614 T DE 60336614T DE 60336614 T DE60336614 T DE 60336614T DE 60336614 D1 DE60336614 D1 DE 60336614D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
redundancy circuit
redundancy
circuit
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60336614T
Other languages
English (en)
Inventor
David C Mcclure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Application granted granted Critical
Publication of DE60336614D1 publication Critical patent/DE60336614D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/846—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by choosing redundant lines at an output stage
DE60336614T 2002-05-31 2003-05-27 Redundanz -Schaltung und -Verfahren für Halbleiterspeicher Expired - Lifetime DE60336614D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/161,501 US6731550B2 (en) 2002-05-31 2002-05-31 Redundancy circuit and method for semiconductor memory devices

Publications (1)

Publication Number Publication Date
DE60336614D1 true DE60336614D1 (de) 2011-05-19

Family

ID=29419746

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60336614T Expired - Lifetime DE60336614D1 (de) 2002-05-31 2003-05-27 Redundanz -Schaltung und -Verfahren für Halbleiterspeicher

Country Status (4)

Country Link
US (1) US6731550B2 (de)
EP (1) EP1367599B1 (de)
JP (1) JP2004005992A (de)
DE (1) DE60336614D1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100472460B1 (ko) * 2002-07-04 2005-03-10 삼성전자주식회사 메모리의 결함 복구 방법 및 그에 적합한 장치
US7047381B2 (en) * 2002-07-19 2006-05-16 Broadcom Corporation System and method for providing one-time programmable memory with fault tolerance
DE10256487B4 (de) * 2002-12-03 2008-12-24 Infineon Technologies Ag Integrierter Speicher und Verfahren zum Testen eines integrierten Speichers
US20060077734A1 (en) * 2004-09-30 2006-04-13 Fong John Y Direct mapped repair cache systems and methods
US7619346B2 (en) * 2005-05-13 2009-11-17 Evigia Systems, Inc. Method and system for monitoring environmental conditions
US20070038805A1 (en) * 2005-08-09 2007-02-15 Texas Instruments Incorporated High granularity redundancy for ferroelectric memories
US8677802B2 (en) * 2006-02-04 2014-03-25 Evigia Systems, Inc. Sensing modules and methods of using
US20110009773A1 (en) * 2006-02-04 2011-01-13 Evigia Systems, Inc. Implantable sensing modules and methods of using
US20080291760A1 (en) * 2007-05-23 2008-11-27 Micron Technology, Inc. Sub-array architecture memory devices and related systems and methods
US9075111B2 (en) 2013-10-07 2015-07-07 King Fahd University Of Petroleum And Minerals Generalized modular redundancy fault tolerance method for combinational circuits
US20190393204A1 (en) * 2018-06-21 2019-12-26 Xcelsis Corporation Eliminating defects in stacks
US11710531B2 (en) * 2019-12-30 2023-07-25 Micron Technology, Inc. Memory redundancy repair

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4380066A (en) * 1980-12-04 1983-04-12 Burroughs Corporation Defect tolerant memory
JPH01224999A (ja) * 1988-03-04 1989-09-07 Mitsubishi Electric Corp 半導体記憶装置
US5179536A (en) * 1989-01-31 1993-01-12 Fujitsu Limited Semiconductor memory device having means for replacing defective memory cells
JPH06111596A (ja) * 1990-10-09 1994-04-22 Texas Instr Inc <Ti> メモリ
US5278793A (en) * 1992-02-25 1994-01-11 Yeh Tsuei Chi Memory defect masking device
JP2741824B2 (ja) * 1992-10-14 1998-04-22 三菱電機株式会社 半導体記憶装置
KR100230393B1 (ko) * 1996-12-05 1999-11-15 윤종용 반도체 메모리장치
US6188618B1 (en) * 1998-04-23 2001-02-13 Kabushiki Kaisha Toshiba Semiconductor device with flexible redundancy system
US6141267A (en) * 1999-02-03 2000-10-31 International Business Machines Corporation Defect management engine for semiconductor memories and memory systems
JP4141656B2 (ja) * 2000-06-07 2008-08-27 株式会社東芝 半導体メモリ集積回路および半導体メモリ装置をテストする方法
JP4345204B2 (ja) * 2000-07-04 2009-10-14 エルピーダメモリ株式会社 半導体記憶装置

Also Published As

Publication number Publication date
EP1367599A2 (de) 2003-12-03
US20030223282A1 (en) 2003-12-04
US6731550B2 (en) 2004-05-04
JP2004005992A (ja) 2004-01-08
EP1367599B1 (de) 2011-04-06
EP1367599A3 (de) 2005-07-27

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